From: Juergen Gross <jgross@suse.com>
To: linux-kernel@vger.kernel.org, x86@kernel.org
Cc: xin@zytor.com, Thomas Gleixner <tglx@linutronix.de>,
Ingo Molnar <mingo@redhat.com>, Borislav Petkov <bp@alien8.de>,
Dave Hansen <dave.hansen@linux.intel.com>,
"H. Peter Anvin" <hpa@zytor.com>, Juergen Gross <jgross@suse.com>
Subject: [PATCH v2 07/12] x86/opcode: Add immediate form MSR instructions
Date: Tue, 30 Sep 2025 09:03:51 +0200 [thread overview]
Message-ID: <20250930070356.30695-8-jgross@suse.com> (raw)
In-Reply-To: <20250930070356.30695-1-jgross@suse.com>
From: "Xin Li (Intel)" <xin@zytor.com>
Add the instruction opcodes used by the immediate form WRMSRNS/RDMSR
to x86-opcode-map.
Signed-off-by: Xin Li (Intel) <xin@zytor.com>
Signed-off-by: Juergen Gross <jgross@suse.com>
---
V2:
- new patch, taken from the RFC v2 MSR refactor series by Xin Li
---
arch/x86/lib/x86-opcode-map.txt | 5 +++--
tools/arch/x86/lib/x86-opcode-map.txt | 5 +++--
2 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/arch/x86/lib/x86-opcode-map.txt b/arch/x86/lib/x86-opcode-map.txt
index 262f7ca1fb95..65aeb18ad22d 100644
--- a/arch/x86/lib/x86-opcode-map.txt
+++ b/arch/x86/lib/x86-opcode-map.txt
@@ -839,7 +839,7 @@ f1: MOVBE My,Gy | MOVBE Mw,Gw (66) | CRC32 Gd,Ey (F2) | CRC32 Gd,Ew (66&F2)
f2: ANDN Gy,By,Ey (v)
f3: Grp17 (1A)
f5: BZHI Gy,Ey,By (v) | PEXT Gy,By,Ey (F3),(v) | PDEP Gy,By,Ey (F2),(v) | WRUSSD/Q My,Gy (66)
-f6: ADCX Gy,Ey (66) | ADOX Gy,Ey (F3) | MULX By,Gy,rDX,Ey (F2),(v) | WRSSD/Q My,Gy
+f6: ADCX Gy,Ey (66) | ADOX Gy,Ey (F3) | MULX By,Gy,rDX,Ey (F2),(v) | WRSSD/Q My,Gy | RDMSR Rq,Gq (F2),(11B) | WRMSRNS Gq,Rq (F3),(11B)
f7: BEXTR Gy,Ey,By (v) | SHLX Gy,Ey,By (66),(v) | SARX Gy,Ey,By (F3),(v) | SHRX Gy,Ey,By (F2),(v)
f8: MOVDIR64B Gv,Mdqq (66) | ENQCMD Gv,Mdqq (F2) | ENQCMDS Gv,Mdqq (F3) | URDMSR Rq,Gq (F2),(11B) | UWRMSR Gq,Rq (F3),(11B)
f9: MOVDIRI My,Gy
@@ -1014,7 +1014,7 @@ f1: CRC32 Gy,Ey (es) | CRC32 Gy,Ey (66),(es) | INVVPID Gy,Mdq (F3),(ev)
f2: INVPCID Gy,Mdq (F3),(ev)
f4: TZCNT Gv,Ev (es) | TZCNT Gv,Ev (66),(es)
f5: LZCNT Gv,Ev (es) | LZCNT Gv,Ev (66),(es)
-f6: Grp3_1 Eb (1A),(ev)
+f6: Grp3_1 Eb (1A),(ev) | RDMSR Rq,Gq (F2),(11B),(ev) | WRMSRNS Gq,Rq (F3),(11B),(ev)
f7: Grp3_2 Ev (1A),(es)
f8: MOVDIR64B Gv,Mdqq (66),(ev) | ENQCMD Gv,Mdqq (F2),(ev) | ENQCMDS Gv,Mdqq (F3),(ev) | URDMSR Rq,Gq (F2),(11B),(ev) | UWRMSR Gq,Rq (F3),(11B),(ev)
f9: MOVDIRI My,Gy (ev)
@@ -1103,6 +1103,7 @@ EndTable
Table: VEX map 7
Referrer:
AVXcode: 7
+f6: RDMSR Rq,Id (F2),(v1),(11B) | WRMSRNS Id,Rq (F3),(v1),(11B)
f8: URDMSR Rq,Id (F2),(v1),(11B) | UWRMSR Id,Rq (F3),(v1),(11B)
EndTable
diff --git a/tools/arch/x86/lib/x86-opcode-map.txt b/tools/arch/x86/lib/x86-opcode-map.txt
index 262f7ca1fb95..65aeb18ad22d 100644
--- a/tools/arch/x86/lib/x86-opcode-map.txt
+++ b/tools/arch/x86/lib/x86-opcode-map.txt
@@ -839,7 +839,7 @@ f1: MOVBE My,Gy | MOVBE Mw,Gw (66) | CRC32 Gd,Ey (F2) | CRC32 Gd,Ew (66&F2)
f2: ANDN Gy,By,Ey (v)
f3: Grp17 (1A)
f5: BZHI Gy,Ey,By (v) | PEXT Gy,By,Ey (F3),(v) | PDEP Gy,By,Ey (F2),(v) | WRUSSD/Q My,Gy (66)
-f6: ADCX Gy,Ey (66) | ADOX Gy,Ey (F3) | MULX By,Gy,rDX,Ey (F2),(v) | WRSSD/Q My,Gy
+f6: ADCX Gy,Ey (66) | ADOX Gy,Ey (F3) | MULX By,Gy,rDX,Ey (F2),(v) | WRSSD/Q My,Gy | RDMSR Rq,Gq (F2),(11B) | WRMSRNS Gq,Rq (F3),(11B)
f7: BEXTR Gy,Ey,By (v) | SHLX Gy,Ey,By (66),(v) | SARX Gy,Ey,By (F3),(v) | SHRX Gy,Ey,By (F2),(v)
f8: MOVDIR64B Gv,Mdqq (66) | ENQCMD Gv,Mdqq (F2) | ENQCMDS Gv,Mdqq (F3) | URDMSR Rq,Gq (F2),(11B) | UWRMSR Gq,Rq (F3),(11B)
f9: MOVDIRI My,Gy
@@ -1014,7 +1014,7 @@ f1: CRC32 Gy,Ey (es) | CRC32 Gy,Ey (66),(es) | INVVPID Gy,Mdq (F3),(ev)
f2: INVPCID Gy,Mdq (F3),(ev)
f4: TZCNT Gv,Ev (es) | TZCNT Gv,Ev (66),(es)
f5: LZCNT Gv,Ev (es) | LZCNT Gv,Ev (66),(es)
-f6: Grp3_1 Eb (1A),(ev)
+f6: Grp3_1 Eb (1A),(ev) | RDMSR Rq,Gq (F2),(11B),(ev) | WRMSRNS Gq,Rq (F3),(11B),(ev)
f7: Grp3_2 Ev (1A),(es)
f8: MOVDIR64B Gv,Mdqq (66),(ev) | ENQCMD Gv,Mdqq (F2),(ev) | ENQCMDS Gv,Mdqq (F3),(ev) | URDMSR Rq,Gq (F2),(11B),(ev) | UWRMSR Gq,Rq (F3),(11B),(ev)
f9: MOVDIRI My,Gy (ev)
@@ -1103,6 +1103,7 @@ EndTable
Table: VEX map 7
Referrer:
AVXcode: 7
+f6: RDMSR Rq,Id (F2),(v1),(11B) | WRMSRNS Id,Rq (F3),(v1),(11B)
f8: URDMSR Rq,Id (F2),(v1),(11B) | UWRMSR Id,Rq (F3),(v1),(11B)
EndTable
--
2.51.0
next prev parent reply other threads:[~2025-09-30 7:04 UTC|newest]
Thread overview: 43+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-30 7:03 [PATCH v2 00/12] x86/msr: Inline rdmsr/wrmsr instructions Juergen Gross
2025-09-30 7:03 ` [PATCH v2 01/12] coco/tdx: Rename MSR access helpers Juergen Gross
2025-09-30 9:07 ` Kiryl Shutsemau
2025-09-30 7:03 ` [PATCH v2 02/12] x86/sev: Replace call of native_wrmsr() with native_wrmsrq() Juergen Gross
2025-10-07 6:08 ` Nikunj A Dadhania
2025-09-30 7:03 ` [PATCH v2 03/12] x86/kvm: Remove the KVM private read_msr() function Juergen Gross
2025-09-30 16:04 ` Sean Christopherson
2025-10-01 9:14 ` Jürgen Groß
2025-09-30 7:03 ` [PATCH v2 04/12] x86/msr: Minimize usage of native_*() msr access functions Juergen Gross
2025-09-30 7:03 ` [PATCH v2 05/12] x86/msr: Move MSR trace calls one function level up Juergen Gross
2025-09-30 7:03 ` [PATCH v2 06/12] x86/cpufeatures: Add a CPU feature bit for MSR immediate form instructions Juergen Gross
2025-09-30 7:03 ` Juergen Gross [this message]
2025-09-30 7:03 ` [PATCH v2 08/12] x86/extable: Add support for immediate form MSR instructions Juergen Gross
2025-09-30 8:14 ` Peter Zijlstra
2025-09-30 8:31 ` Jürgen Groß
2025-09-30 7:03 ` [PATCH v2 09/12] x86/msr: Use the alternatives mechanism for WRMSR Juergen Gross
2025-09-30 8:31 ` Peter Zijlstra
2025-09-30 8:46 ` Jürgen Groß
2025-09-30 8:50 ` Peter Zijlstra
2025-09-30 12:51 ` Peter Zijlstra
2025-09-30 15:42 ` Jürgen Groß
2025-10-01 6:43 ` Peter Zijlstra
2025-10-01 7:23 ` Peter Zijlstra
2025-10-03 14:23 ` Dave Hansen
2025-10-03 16:53 ` H. Peter Anvin
2025-10-01 8:49 ` Juergen Gross
2025-10-01 10:50 ` Peter Zijlstra
2025-10-01 11:16 ` Jürgen Groß
2025-09-30 16:00 ` Sean Christopherson
2025-10-01 9:13 ` Jürgen Groß
2025-09-30 7:03 ` [PATCH v2 10/12] x86/msr: Use the alternatives mechanism for RDMSR Juergen Gross
2025-09-30 7:03 ` [PATCH v2 11/12] x86/paravirt: Don't use pv_ops vector for MSR access functions Juergen Gross
2025-09-30 8:38 ` Peter Zijlstra
2025-09-30 9:02 ` Jürgen Groß
2025-09-30 10:04 ` Peter Zijlstra
2025-09-30 10:43 ` Jürgen Groß
2025-09-30 19:49 ` H. Peter Anvin
2025-09-30 19:59 ` H. Peter Anvin
2025-10-01 6:45 ` Peter Zijlstra
2025-09-30 21:27 ` kernel test robot
2025-10-01 5:48 ` Jürgen Groß
2025-09-30 7:03 ` [PATCH v2 12/12] x86/msr: Reduce number of low level MSR access helpers Juergen Gross
2025-09-30 19:19 ` [PATCH v2 00/12] x86/msr: Inline rdmsr/wrmsr instructions H. Peter Anvin
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