[PATCH] ARM: dts: microchip: sama7d65: add Cortex-A7 PMU node

[PATCH] ARM: dts: microchip: sama7d65: add Cortex-A7 PMU node

[Mihai Sain]

Add the Performance Monitoring Unit (PMU) node with the appropriate
compatible string, interrupt line, and affinity so that perf and other
PMU‑based tooling can function correctly on this SoC.

[root@SAMA7D65 ~]$ dmesg | grep -i pmu
[    1.487869] hw-perfevents: enabled with armv7_cortex_a7 PMU driver, 5 (8000000f) counters available

[root@SAMA7D65 ~]$ perf list hw
List of pre-defined events (to be used in -e or -M):

branch-instructions OR branches                    [Hardware event]
branch-misses                                      [Hardware event]
bus-cycles                                         [Hardware event]
cache-misses                                       [Hardware event]
cache-references                                   [Hardware event]
cpu-cycles OR cycles                               [Hardware event]
instructions                                       [Hardware event]

Signed-off-by: Mihai Sain <mihai.sain@microchip.com>
---
 arch/arm/boot/dts/microchip/sama7d65.dtsi | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm/boot/dts/microchip/sama7d65.dtsi b/arch/arm/boot/dts/microchip/sama7d65.dtsi
index 868045c650a7..1e1ca4f93969 100644
--- a/arch/arm/boot/dts/microchip/sama7d65.dtsi
+++ b/arch/arm/boot/dts/microchip/sama7d65.dtsi
@@ -45,6 +45,12 @@ L2: l2-cache {
 		};
 	};
 
+	pmu {
+		compatible = "arm,cortex-a7-pmu";
+		interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-affinity = <&cpu0>;
+	};
+
 	clocks {
 		main_xtal: clock-mainxtal {
 			compatible = "fixed-clock";

base-commit: 63804fed149a6750ffd28610c5c1c98cce6bd377
-- 
2.52.0

Re: [PATCH] ARM: dts: microchip: sama7d65: add Cortex-A7 PMU node

[Claudiu Beznea]

Hi, Mihai,

On 1/26/26 15:10, Mihai Sain wrote:
> Add the Performance Monitoring Unit (PMU) node with the appropriate
> compatible string, interrupt line, and affinity so that perf and other
> PMU‑based tooling can function correctly on this SoC.
> 
> [root@SAMA7D65 ~]$ dmesg | grep -i pmu
> [    1.487869] hw-perfevents: enabled with armv7_cortex_a7 PMU driver, 5 (8000000f) counters available
> 
> [root@SAMA7D65 ~]$ perf list hw
> List of pre-defined events (to be used in -e or -M):
> 
> branch-instructions OR branches                    [Hardware event]
> branch-misses                                      [Hardware event]
> bus-cycles                                         [Hardware event]
> cache-misses                                       [Hardware event]
> cache-references                                   [Hardware event]
> cpu-cycles OR cycles                               [Hardware event]
> instructions                                       [Hardware event]
> 
> Signed-off-by: Mihai Sain <mihai.sain@microchip.com>
> ---
>   arch/arm/boot/dts/microchip/sama7d65.dtsi | 6 ++++++
>   1 file changed, 6 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/microchip/sama7d65.dtsi b/arch/arm/boot/dts/microchip/sama7d65.dtsi
> index 868045c650a7..1e1ca4f93969 100644
> --- a/arch/arm/boot/dts/microchip/sama7d65.dtsi
> +++ b/arch/arm/boot/dts/microchip/sama7d65.dtsi
> @@ -45,6 +45,12 @@ L2: l2-cache {
>   		};
>   	};
>   
> +	pmu {
> +		compatible = "arm,cortex-a7-pmu";
> +		interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
> +		interrupt-affinity = <&cpu0>;

According to the documentation [1] interrupt-affinity is not needed here. Could 
you please check?

[1] 
https://elixir.bootlin.com/linux/v7.0-rc4/source/Documentation/devicetree/bindings/arm/pmu.yaml#L107

Thank you,
Claudiu