From: David Heidelberg via B4 Relay <devnull+david.ixit.cz@kernel.org>
To: Robert Foss <rfoss@kernel.org>, Todor Tomov <todor.too@gmail.com>,
Bryan O'Donoghue <bryan.odonoghue@linaro.org>,
Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>,
Mauro Carvalho Chehab <mchehab@kernel.org>,
Luca Weiss <luca.weiss@fairphone.com>,
Petr Hodina <phodina@protonmail.com>,
Casey Connolly <casey.connolly@linaro.org>,
"Dr. Git" <drgitx@gmail.com>, Cory Keitz <ckeitz@amazon.com>,
Loic Poulain <loic.poulain@oss.qualcomm.com>
Cc: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>,
Joel Selvaraj <foss@joelselvaraj.com>,
Kieran Bingham <kbingham@kernel.org>,
Sakari Ailus <sakari.ailus@linux.intel.com>,
linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org,
linux-kernel@vger.kernel.org, phone-devel@vger.kernel.org,
David Heidelberg <david@ixit.cz>
Subject: [PATCH WIP v5 4/9] media: qcom: camss: Initialize lanes after lane configuration is available
Date: Sun, 31 May 2026 15:08:12 +0200 [thread overview]
Message-ID: <20260531-qcom-cphy-v5-4-6be0f62b4d65@ixit.cz> (raw)
In-Reply-To: <20260531-qcom-cphy-v5-0-6be0f62b4d65@ixit.cz>
From: David Heidelberg <david@ixit.cz>
The lanes must not be initialized before the driver has access to
the lane configuration, as it depends on whether D-PHY or C-PHY mode
is in use. Move the lane initialization to csiphy_lanes_enable which is
called when the configuration structures are available.
Co-developed-by: Petr Hodina <phodina@protonmail.com>
Signed-off-by: Petr Hodina <phodina@protonmail.com>
Signed-off-by: David Heidelberg <david@ixit.cz>
---
.../platform/qcom/camss/camss-csiphy-3ph-1-0.c | 133 +++++++++++++++------
1 file changed, 95 insertions(+), 38 deletions(-)
diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
index d4624417a7424..8bcba6107471f 100644
--- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
+++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
@@ -1164,16 +1164,110 @@ static int csiphy_lanes_enable(struct csiphy_device *csiphy,
{
struct device *dev = csiphy->camss->dev;
struct csiphy_lanes_cfg *c = &cfg->csi2->lane_cfg;
struct csiphy_device_regs *regs = csiphy->regs;
u8 settle_cnt;
u8 val;
int i;
+ switch (csiphy->camss->res->version) {
+ case CAMSS_845:
+ if (c->phy_cfg == V4L2_MBUS_CSI2_CPHY) {
+ regs->lane_regs = NULL;
+ regs->lane_array_size = 0;
+ } else {
+ regs->lane_regs = &lane_regs_sdm845[0];
+ regs->lane_array_size = ARRAY_SIZE(lane_regs_sdm845);
+ }
+ break;
+ case CAMSS_2290:
+ case CAMSS_6150:
+ if (c->phy_cfg == V4L2_MBUS_CSI2_CPHY) {
+ regs->lane_regs = NULL;
+ regs->lane_array_size = 0;
+ } else {
+ regs->lane_regs = &lane_regs_qcm2290[0];
+ regs->lane_array_size = ARRAY_SIZE(lane_regs_qcm2290);
+ }
+ break;
+ case CAMSS_6350:
+ if (c->phy_cfg == V4L2_MBUS_CSI2_CPHY) {
+ regs->lane_regs = NULL;
+ regs->lane_array_size = 0;
+ } else {
+ regs->lane_regs = &lane_regs_sm6350[0];
+ regs->lane_array_size = ARRAY_SIZE(lane_regs_sm6350);
+ }
+ break;
+ case CAMSS_7280:
+ case CAMSS_8250:
+ if (c->phy_cfg == V4L2_MBUS_CSI2_CPHY) {
+ regs->lane_regs = NULL;
+ regs->lane_array_size = 0;
+ } else {
+ regs->lane_regs = &lane_regs_sm8250[0];
+ regs->lane_array_size = ARRAY_SIZE(lane_regs_sm8250);
+ }
+ break;
+ case CAMSS_8280XP:
+ if (c->phy_cfg == V4L2_MBUS_CSI2_CPHY) {
+ regs->lane_regs = NULL;
+ regs->lane_array_size = 0;
+ } else {
+ regs->lane_regs = &lane_regs_sc8280xp[0];
+ regs->lane_array_size = ARRAY_SIZE(lane_regs_sc8280xp);
+ }
+ break;
+ case CAMSS_X1E80100:
+ if (c->phy_cfg == V4L2_MBUS_CSI2_CPHY) {
+ regs->lane_regs = NULL;
+ regs->lane_array_size = 0;
+ } else {
+ regs->lane_regs = &lane_regs_x1e80100[0];
+ regs->lane_array_size = ARRAY_SIZE(lane_regs_x1e80100);
+ }
+ break;
+ case CAMSS_8550:
+ if (c->phy_cfg == V4L2_MBUS_CSI2_CPHY) {
+ regs->lane_regs = NULL;
+ regs->lane_array_size = 0;
+ } else {
+ regs->lane_regs = &lane_regs_sm8550[0];
+ regs->lane_array_size = ARRAY_SIZE(lane_regs_sm8550);
+ }
+ break;
+ case CAMSS_8650:
+ if (c->phy_cfg == V4L2_MBUS_CSI2_CPHY) {
+ regs->lane_regs = NULL;
+ regs->lane_array_size = 0;
+ } else {
+ regs->lane_regs = &lane_regs_sm8650[0];
+ regs->lane_array_size = ARRAY_SIZE(lane_regs_sm8650);
+ }
+ break;
+ case CAMSS_8300:
+ case CAMSS_8775P:
+ if (c->phy_cfg == V4L2_MBUS_CSI2_CPHY) {
+ regs->lane_regs = NULL;
+ regs->lane_array_size = 0;
+ } else {
+ regs->lane_regs = &lane_regs_sa8775p[0];
+ regs->lane_array_size = ARRAY_SIZE(lane_regs_sa8775p);
+ }
+ break;
+ default:
+ break;
+ }
+
+ if (!regs->lane_regs && c->phy_cfg == V4L2_MBUS_CSI2_CPHY) {
+ dev_err(dev, "Missing lane_regs definition for C-PHY\n");
+ return -EINVAL;
+ }
+
settle_cnt = csiphy_settle_cnt_calc(link_freq, csiphy->timer_clk_rate);
val = 0;
switch (c->phy_cfg) {
case V4L2_MBUS_CSI2_CPHY:
for (i = 0; i < c->num_data; i++)
val |= BIT((c->data[i].pos * 2) + 1);
@@ -1235,63 +1329,26 @@ static int csiphy_init(struct csiphy_device *csiphy)
struct device *dev = csiphy->camss->dev;
struct csiphy_device_regs *regs;
regs = devm_kmalloc(dev, sizeof(*regs), GFP_KERNEL);
if (!regs)
return -ENOMEM;
csiphy->regs = regs;
- regs->offset = 0x800;
regs->common_status_offset = 0xb0;
switch (csiphy->camss->res->version) {
- case CAMSS_845:
- regs->lane_regs = &lane_regs_sdm845[0];
- regs->lane_array_size = ARRAY_SIZE(lane_regs_sdm845);
- break;
- case CAMSS_2290:
- case CAMSS_6150:
- regs->lane_regs = &lane_regs_qcm2290[0];
- regs->lane_array_size = ARRAY_SIZE(lane_regs_qcm2290);
- break;
- case CAMSS_6350:
- regs->lane_regs = &lane_regs_sm6350[0];
- regs->lane_array_size = ARRAY_SIZE(lane_regs_sm6350);
- break;
- case CAMSS_7280:
- case CAMSS_8250:
- regs->lane_regs = &lane_regs_sm8250[0];
- regs->lane_array_size = ARRAY_SIZE(lane_regs_sm8250);
- break;
- case CAMSS_8280XP:
- regs->lane_regs = &lane_regs_sc8280xp[0];
- regs->lane_array_size = ARRAY_SIZE(lane_regs_sc8280xp);
- break;
case CAMSS_X1E80100:
- regs->lane_regs = &lane_regs_x1e80100[0];
- regs->lane_array_size = ARRAY_SIZE(lane_regs_x1e80100);
- regs->offset = 0x1000;
- break;
case CAMSS_8550:
- regs->lane_regs = &lane_regs_sm8550[0];
- regs->lane_array_size = ARRAY_SIZE(lane_regs_sm8550);
- regs->offset = 0x1000;
- break;
case CAMSS_8650:
- regs->lane_regs = &lane_regs_sm8650[0];
- regs->lane_array_size = ARRAY_SIZE(lane_regs_sm8650);
regs->offset = 0x1000;
break;
- case CAMSS_8300:
- case CAMSS_8775P:
- regs->lane_regs = &lane_regs_sa8775p[0];
- regs->lane_array_size = ARRAY_SIZE(lane_regs_sa8775p);
- break;
default:
+ regs->offset = 0x800;
break;
}
return 0;
}
const struct csiphy_hw_ops csiphy_ops_3ph_1_0 = {
.get_lane_mask = csiphy_get_lane_mask,
--
2.53.0
next prev parent reply other threads:[~2026-05-31 13:08 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-31 13:08 [PATCH WIP v5 0/9] media: camss: Add support for C-PHY configuration on Qualcomm platforms David Heidelberg via B4 Relay
2026-05-31 13:08 ` [PATCH WIP v5 1/9] media: qcom: camss: csiphy: Introduce PHY configuration David Heidelberg via B4 Relay
2026-06-01 15:57 ` Bryan O'Donoghue
2026-05-31 13:08 ` [PATCH WIP v5 2/9] media: qcom: camss: csiphy-3ph: Use odd bits for configuring C-PHY lanes David Heidelberg via B4 Relay
2026-06-01 8:49 ` Sakari Ailus
2026-06-01 12:48 ` David Heidelberg
2026-06-01 15:59 ` Bryan O'Donoghue
2026-05-31 13:08 ` [PATCH WIP v5 3/9] media: qcom: camss: Prepare CSID for C-PHY support David Heidelberg via B4 Relay
2026-05-31 13:08 ` David Heidelberg via B4 Relay [this message]
2026-06-01 9:00 ` [PATCH WIP v5 4/9] media: qcom: camss: Initialize lanes after lane configuration is available Sakari Ailus
2026-06-01 12:52 ` David Heidelberg
2026-05-31 13:08 ` [PATCH WIP v5 5/9] media: qcom: camss: csiphy-3ph: Add Gen2 v1.1 MIPI CSI-2 C-PHY init David Heidelberg via B4 Relay
2026-05-31 13:08 ` [PATCH WIP v5 6/9] media: qcom: camss: csiphy-3ph: Update " David Heidelberg via B4 Relay
2026-06-01 16:03 ` Bryan O'Donoghue
2026-06-01 17:02 ` David Heidelberg
2026-05-31 13:08 ` [PATCH WIP v5 7/9] media: qcom: camss: csiphy-3ph: Add Gen2 v1.2.1 " David Heidelberg via B4 Relay
2026-05-31 13:08 ` [PATCH WIP v5 8/9] media: qcom: camss: Account for C-PHY when calculating link frequency David Heidelberg via B4 Relay
2026-05-31 13:08 ` [PATCH WIP v5 9/9] media: qcom: camss: Enable C-PHY where available David Heidelberg via B4 Relay
2026-06-01 16:06 ` Bryan O'Donoghue
2026-06-01 15:56 ` [PATCH WIP v5 0/9] media: camss: Add support for C-PHY configuration on Qualcomm platforms Bryan O'Donoghue
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