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From: David Heidelberg <david@ixit.cz>
To: Sakari Ailus <sakari.ailus@linux.intel.com>
Cc: Robert Foss <rfoss@kernel.org>, Todor Tomov <todor.too@gmail.com>,
	Bryan O'Donoghue <bryan.odonoghue@linaro.org>,
	Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>,
	Mauro Carvalho Chehab <mchehab@kernel.org>,
	Luca Weiss <luca.weiss@fairphone.com>,
	Petr Hodina <phodina@protonmail.com>,
	Casey Connolly <casey.connolly@linaro.org>,
	"Dr. Git" <drgitx@gmail.com>, Cory Keitz <ckeitz@amazon.com>,
	Loic Poulain <loic.poulain@oss.qualcomm.com>,
	Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>,
	Joel Selvaraj <foss@joelselvaraj.com>,
	Kieran Bingham <kbingham@kernel.org>,
	linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org,
	linux-kernel@vger.kernel.org, phone-devel@vger.kernel.org
Subject: Re: [PATCH WIP v5 2/9] media: qcom: camss: csiphy-3ph: Use odd bits for configuring C-PHY lanes
Date: Mon, 1 Jun 2026 14:48:22 +0200	[thread overview]
Message-ID: <c8cda422-1a02-4a2d-bd01-6c04ebebd0be@ixit.cz> (raw)
In-Reply-To: <ah1HhruI1Qc2FfwG@kekkonen.localdomain>

On 01/06/2026 10:49, Sakari Ailus wrote:
> Hi David,
> 
> Thanks for the patch.
> 
> On Sun, May 31, 2026 at 03:08:10PM +0200, David Heidelberg via B4 Relay wrote:
>> From: David Heidelberg <david@ixit.cz>
>>
>> So far, only D-PHY mode was supported, which uses even bits when enabling
>> or masking lanes. For C-PHY configuration, the hardware instead requires
>> using the odd bits.
>>
>> Since there can be unrecognized configuration allow returning failure.
>>
>> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
>> Acked-by: Cory Keitz <ckeitz@amazon.com>
>> Signed-off-by: David Heidelberg <david@ixit.cz>
>> ---
>>   .../platform/qcom/camss/camss-csiphy-2ph-1-0.c     |  8 ++--
>>   .../platform/qcom/camss/camss-csiphy-3ph-1-0.c     | 49 +++++++++++++++++-----
>>   drivers/media/platform/qcom/camss/camss-csiphy.c   |  5 +--
>>   drivers/media/platform/qcom/camss/camss-csiphy.h   |  6 +--
>>   4 files changed, 48 insertions(+), 20 deletions(-)
>>

[...]

>> -static void csiphy_lanes_enable(struct csiphy_device *csiphy,
>> -				struct csiphy_config *cfg,
>> -				s64 link_freq, u8 lane_mask)
>> +static int csiphy_lanes_enable(struct csiphy_device *csiphy,
>> +			       struct csiphy_config *cfg,
>> +			       s64 link_freq, u8 lane_mask)
>>   {
>> +	struct device *dev = csiphy->camss->dev;
>>   	struct csiphy_lanes_cfg *c = &cfg->csi2->lane_cfg;
>>   	struct csiphy_device_regs *regs = csiphy->regs;
>>   	u8 settle_cnt;
>>   	u8 val;
>>   	int i;
>>   
>>   	settle_cnt = csiphy_settle_cnt_calc(link_freq, csiphy->timer_clk_rate);
>>   
>> -	val = CSIPHY_3PH_CMN_CSI_COMMON_CTRL5_CLK_ENABLE;
>> -	for (i = 0; i < c->num_data; i++)
>> -		val |= BIT(c->data[i].pos * 2);
>> +	val = 0;
>> +
>> +	switch (c->phy_cfg) {
>> +	case V4L2_MBUS_CSI2_CPHY:
>> +		for (i = 0; i < c->num_data; i++)
>> +			val |= BIT((c->data[i].pos * 2) + 1);
>> +		break;
>> +	case V4L2_MBUS_CSI2_DPHY:
>> +		val = CSIPHY_3PH_CMN_CSI_COMMON_CTRL5_CLK_ENABLE;
>> +
>> +		for (i = 0; i < c->num_data; i++)
>> +			val |= BIT(c->data[i].pos * 2);
>> +		break;
>> +	default:
>> +		dev_err(dev, "Unsupported bus type %d\n", c->phy_cfg);
>> +		return -EINVAL;
> 
> If this is the only reason why you're changing the return type to int, I'd
> suggest using WARN_ON() in this case. I presume it'd take a driver bug for
> this to trigger?

Thank you for the review.

If others agree, I would also prefer WARN_ON instead of changing return values.

David

[...]

  reply	other threads:[~2026-06-01 12:48 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-05-31 13:08 [PATCH WIP v5 0/9] media: camss: Add support for C-PHY configuration on Qualcomm platforms David Heidelberg via B4 Relay
2026-05-31 13:08 ` [PATCH WIP v5 1/9] media: qcom: camss: csiphy: Introduce PHY configuration David Heidelberg via B4 Relay
2026-06-01 15:57   ` Bryan O'Donoghue
2026-05-31 13:08 ` [PATCH WIP v5 2/9] media: qcom: camss: csiphy-3ph: Use odd bits for configuring C-PHY lanes David Heidelberg via B4 Relay
2026-06-01  8:49   ` Sakari Ailus
2026-06-01 12:48     ` David Heidelberg [this message]
2026-06-01 15:59       ` Bryan O'Donoghue
2026-05-31 13:08 ` [PATCH WIP v5 3/9] media: qcom: camss: Prepare CSID for C-PHY support David Heidelberg via B4 Relay
2026-05-31 13:08 ` [PATCH WIP v5 4/9] media: qcom: camss: Initialize lanes after lane configuration is available David Heidelberg via B4 Relay
2026-06-01  9:00   ` Sakari Ailus
2026-06-01 12:52     ` David Heidelberg
2026-05-31 13:08 ` [PATCH WIP v5 5/9] media: qcom: camss: csiphy-3ph: Add Gen2 v1.1 MIPI CSI-2 C-PHY init David Heidelberg via B4 Relay
2026-05-31 13:08 ` [PATCH WIP v5 6/9] media: qcom: camss: csiphy-3ph: Update " David Heidelberg via B4 Relay
2026-06-01 16:03   ` Bryan O'Donoghue
2026-06-01 17:02     ` David Heidelberg
2026-05-31 13:08 ` [PATCH WIP v5 7/9] media: qcom: camss: csiphy-3ph: Add Gen2 v1.2.1 " David Heidelberg via B4 Relay
2026-05-31 13:08 ` [PATCH WIP v5 8/9] media: qcom: camss: Account for C-PHY when calculating link frequency David Heidelberg via B4 Relay
2026-05-31 13:08 ` [PATCH WIP v5 9/9] media: qcom: camss: Enable C-PHY where available David Heidelberg via B4 Relay
2026-06-01 16:06   ` Bryan O'Donoghue
2026-06-01 15:56 ` [PATCH WIP v5 0/9] media: camss: Add support for C-PHY configuration on Qualcomm platforms Bryan O'Donoghue

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