From: David Heidelberg via B4 Relay <devnull+david.ixit.cz@kernel.org>
To: Robert Foss <rfoss@kernel.org>, Todor Tomov <todor.too@gmail.com>,
Bryan O'Donoghue <bryan.odonoghue@linaro.org>,
Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>,
Mauro Carvalho Chehab <mchehab@kernel.org>,
Luca Weiss <luca.weiss@fairphone.com>,
Petr Hodina <phodina@protonmail.com>,
Casey Connolly <casey.connolly@linaro.org>,
"Dr. Git" <drgitx@gmail.com>, Cory Keitz <ckeitz@amazon.com>,
Loic Poulain <loic.poulain@oss.qualcomm.com>
Cc: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>,
Joel Selvaraj <foss@joelselvaraj.com>,
Kieran Bingham <kbingham@kernel.org>,
Sakari Ailus <sakari.ailus@linux.intel.com>,
linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org,
linux-kernel@vger.kernel.org, phone-devel@vger.kernel.org,
David Heidelberg <david@ixit.cz>
Subject: [PATCH WIP v5 7/9] media: qcom: camss: csiphy-3ph: Add Gen2 v1.2.1 MIPI CSI-2 C-PHY init
Date: Sun, 31 May 2026 15:08:15 +0200 [thread overview]
Message-ID: <20260531-qcom-cphy-v5-7-6be0f62b4d65@ixit.cz> (raw)
In-Reply-To: <20260531-qcom-cphy-v5-0-6be0f62b4d65@ixit.cz>
From: Luca Weiss <luca.weiss@fairphone.com>
Add a PHY configuration sequence for the sm8250 which uses a Qualcomm
Gen 2 version 1.2.1 CSI-2 PHY.
The PHY can be configured as two phase or three phase in C-PHY or D-PHY
mode. This configuration supports three-phase C-PHY mode.
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Acked-by: Cory Keitz <ckeitz@amazon.com>
Signed-off-by: David Heidelberg <david@ixit.cz>
---
.../platform/qcom/camss/camss-csiphy-3ph-1-0.c | 111 ++++++++++++++++++++-
1 file changed, 109 insertions(+), 2 deletions(-)
diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
index 9a0f009c033bb..081060026975c 100644
--- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
+++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
@@ -665,16 +665,123 @@ csiphy_lane_regs lane_regs_qcm2290[] = {
{0x0608, 0x04, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
{0x060C, 0xff, 0x00, CSIPHY_DNP_PARAMS},
{0x0610, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0638, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0660, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0664, 0x3f, 0x00, CSIPHY_DEFAULT_PARAMS},
};
+/* GEN2 1.2.1 3PH */
+/* 3 entries: 3 lanes (C-PHY) */
+static const struct
+csiphy_lane_regs lane_regs_sm8250_3ph[] = {
+ {0x0990, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0994, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0998, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0990, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0994, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0998, 0x1a, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x098c, 0xaf, 0x01, CSIPHY_DEFAULT_PARAMS},
+ {0x015c, 0x46, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0168, 0xa0, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0104, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x010c, 0x12, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
+ {0x0108, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE},
+ {0x0114, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0150, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0188, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x018c, 0x7f, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0190, 0x7f, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0118, 0x3e, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x011c, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0120, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0124, 0x7f, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0128, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x012c, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0160, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x01cc, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x01dc, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0984, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0988, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0980, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x09ac, 0x35, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x09b0, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0800, 0x0e, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0884, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
+
+ {0x0a90, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0a94, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0a98, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0a90, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0a94, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0a98, 0x1a, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0a8c, 0xaf, 0x01, CSIPHY_DEFAULT_PARAMS},
+ {0x035c, 0x46, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0368, 0xa0, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0304, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x030c, 0x12, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
+ {0x0308, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE},
+ {0x0314, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0350, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0388, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x038c, 0x7f, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0390, 0x7f, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0318, 0x3e, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x031c, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0320, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0324, 0x7f, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0328, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x032c, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0360, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x03cc, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x03dc, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0a84, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0a88, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0a80, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0aac, 0x35, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0ab0, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0800, 0x0e, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0884, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
+
+ {0x0b90, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0b94, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0b98, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0b90, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0b94, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0b98, 0x1a, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0b8c, 0xaf, 0x01, CSIPHY_DEFAULT_PARAMS},
+ {0x055c, 0x46, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0568, 0xa0, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0504, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x050c, 0x12, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
+ {0x0508, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE},
+ {0x0514, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0550, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0588, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x058c, 0x7f, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0590, 0x7f, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0518, 0x3e, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x051c, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0520, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0524, 0x7f, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0528, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x052c, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0560, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x05cc, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x05dc, 0x50, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0b84, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0b88, 0x05, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0b80, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0bac, 0x35, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0bb0, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0800, 0x0e, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0884, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},
+};
+
/* GEN2 2.1.2 2PH DPHY mode */
static const struct
csiphy_lane_regs lane_regs_sm8550[] = {
{0x0E90, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0E98, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0E94, 0x07, 0x01, CSIPHY_DEFAULT_PARAMS},
{0x00A0, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
{0x0090, 0x0F, 0x00, CSIPHY_DEFAULT_PARAMS},
@@ -1262,18 +1369,18 @@ static int csiphy_lanes_enable(struct csiphy_device *csiphy,
} else {
regs->lane_regs = &lane_regs_sm6350[0];
regs->lane_array_size = ARRAY_SIZE(lane_regs_sm6350);
}
break;
case CAMSS_7280:
case CAMSS_8250:
if (c->phy_cfg == V4L2_MBUS_CSI2_CPHY) {
- regs->lane_regs = NULL;
- regs->lane_array_size = 0;
+ regs->lane_regs = &lane_regs_sm8250_3ph[0];
+ regs->lane_array_size = ARRAY_SIZE(lane_regs_sm8250_3ph);
} else {
regs->lane_regs = &lane_regs_sm8250[0];
regs->lane_array_size = ARRAY_SIZE(lane_regs_sm8250);
}
break;
case CAMSS_8280XP:
if (c->phy_cfg == V4L2_MBUS_CSI2_CPHY) {
regs->lane_regs = NULL;
--
2.53.0
next prev parent reply other threads:[~2026-05-31 13:08 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-31 13:08 [PATCH WIP v5 0/9] media: camss: Add support for C-PHY configuration on Qualcomm platforms David Heidelberg via B4 Relay
2026-05-31 13:08 ` [PATCH WIP v5 1/9] media: qcom: camss: csiphy: Introduce PHY configuration David Heidelberg via B4 Relay
2026-06-01 15:57 ` Bryan O'Donoghue
2026-05-31 13:08 ` [PATCH WIP v5 2/9] media: qcom: camss: csiphy-3ph: Use odd bits for configuring C-PHY lanes David Heidelberg via B4 Relay
2026-06-01 8:49 ` Sakari Ailus
2026-06-01 12:48 ` David Heidelberg
2026-06-01 15:59 ` Bryan O'Donoghue
2026-05-31 13:08 ` [PATCH WIP v5 3/9] media: qcom: camss: Prepare CSID for C-PHY support David Heidelberg via B4 Relay
2026-05-31 13:08 ` [PATCH WIP v5 4/9] media: qcom: camss: Initialize lanes after lane configuration is available David Heidelberg via B4 Relay
2026-06-01 9:00 ` Sakari Ailus
2026-06-01 12:52 ` David Heidelberg
2026-05-31 13:08 ` [PATCH WIP v5 5/9] media: qcom: camss: csiphy-3ph: Add Gen2 v1.1 MIPI CSI-2 C-PHY init David Heidelberg via B4 Relay
2026-05-31 13:08 ` [PATCH WIP v5 6/9] media: qcom: camss: csiphy-3ph: Update " David Heidelberg via B4 Relay
2026-06-01 16:03 ` Bryan O'Donoghue
2026-06-01 17:02 ` David Heidelberg
2026-05-31 13:08 ` David Heidelberg via B4 Relay [this message]
2026-05-31 13:08 ` [PATCH WIP v5 8/9] media: qcom: camss: Account for C-PHY when calculating link frequency David Heidelberg via B4 Relay
2026-05-31 13:08 ` [PATCH WIP v5 9/9] media: qcom: camss: Enable C-PHY where available David Heidelberg via B4 Relay
2026-06-01 16:06 ` Bryan O'Donoghue
2026-06-01 15:56 ` [PATCH WIP v5 0/9] media: camss: Add support for C-PHY configuration on Qualcomm platforms Bryan O'Donoghue
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