[PATCH 0/3] Add quad mode support for QPIC SNAND

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* [PATCH 0/3] Add quad mode support for QPIC SNAND
@ 2026-07-16  5:27 Md Sadre Alam
  2026-07-16  5:27 ` [PATCH 1/3] spi: spi-qpic-snand: move command mapping helper Md Sadre Alam
                   ` (2 more replies)
  0 siblings, 3 replies; 6+ messages in thread
From: Md Sadre Alam @ 2026-07-16  5:27 UTC (permalink / raw)
  To: Mark Brown; +Cc: linux-spi, linux-kernel, Md Sadre Alam, Md Sadre Alam

The Qualcomm QPIC SPI-NAND controller supports both single (x1) and
quad (x4) transfer modes, however the current driver operates only in
single-bit mode. This series adds support for quad data transfers and
includes a vendor-specific fix required for Macronix SPI-NAND devices.

Signed-off-by: Md Sadre Alam <mdalam@qti.qualcomm.com>
---
Md Sadre Alam (3):
      spi: spi-qpic-snand: move command mapping helper
      spi: spi-qpic-snand: add quad mode support
      spi: spi-qpic-snand: Handle Macronix quad read opcode 0x6b

 drivers/spi/spi-qpic-snand.c | 155 ++++++++++++++++++++++++++++---------------
 1 file changed, 103 insertions(+), 52 deletions(-)
---
base-commit: 19827e7930a5511c68e12aac6e4522f3661a1709
change-id: 20260716-quad-ec2765317214

Best regards,
-- 
Md Sadre Alam <mdalam@qti.qualcomm.com>


^ permalink raw reply	[flat|nested] 6+ messages in thread

* [PATCH 1/3] spi: spi-qpic-snand: move command mapping helper
  2026-07-16  5:27 [PATCH 0/3] Add quad mode support for QPIC SNAND Md Sadre Alam
@ 2026-07-16  5:27 ` Md Sadre Alam
  2026-07-16  5:27 ` [PATCH 2/3] spi: spi-qpic-snand: add quad mode support Md Sadre Alam
  2026-07-16  5:27 ` [PATCH 3/3] spi: spi-qpic-snand: Handle Macronix quad read opcode 0x6b Md Sadre Alam
  2 siblings, 0 replies; 6+ messages in thread
From: Md Sadre Alam @ 2026-07-16  5:27 UTC (permalink / raw)
  To: Mark Brown; +Cc: linux-spi, linux-kernel, Md Sadre Alam, Md Sadre Alam

Move qcom_spi_cmd_mapping() above qcom_spi_read_page() so it can be
used by read path changes added in a subsequent patch.

No functional change.

Signed-off-by: Md Sadre Alam <md.alam@oss.qualcomm.com>
---
 drivers/spi/spi-qpic-snand.c | 96 ++++++++++++++++++++++----------------------
 1 file changed, 48 insertions(+), 48 deletions(-)

diff --git a/drivers/spi/spi-qpic-snand.c b/drivers/spi/spi-qpic-snand.c
index 6cc53586b8a8..b96b6d149ca5 100644
--- a/drivers/spi/spi-qpic-snand.c
+++ b/drivers/spi/spi-qpic-snand.c
@@ -991,6 +991,54 @@ static int qcom_spi_read_page_oob(struct qcom_nand_controller *snandc,
 	return qcom_spi_check_error(snandc);
 }
 
+static int qcom_spi_cmd_mapping(struct qcom_nand_controller *snandc, u32 opcode, u32 *cmd)
+{
+	switch (opcode) {
+	case SPINAND_RESET:
+		*cmd = (SPI_WP | SPI_HOLD | SPI_TRANSFER_MODE_x1 | OP_RESET_DEVICE);
+		break;
+	case SPINAND_READID:
+		*cmd = (SPI_WP | SPI_HOLD | SPI_TRANSFER_MODE_x1 | OP_FETCH_ID);
+		break;
+	case SPINAND_GET_FEATURE:
+		*cmd = (SPI_TRANSFER_MODE_x1 | SPI_WP | SPI_HOLD | ACC_FEATURE);
+		break;
+	case SPINAND_SET_FEATURE:
+		*cmd = (SPI_TRANSFER_MODE_x1 | SPI_WP | SPI_HOLD | ACC_FEATURE |
+			QPIC_SET_FEATURE);
+		break;
+	case SPINAND_READ:
+		if (snandc->qspi->raw_rw) {
+			*cmd = (PAGE_ACC | LAST_PAGE | SPI_TRANSFER_MODE_x1 |
+					SPI_WP | SPI_HOLD | OP_PAGE_READ);
+		} else {
+			*cmd = (PAGE_ACC | LAST_PAGE | SPI_TRANSFER_MODE_x1 |
+					SPI_WP | SPI_HOLD | OP_PAGE_READ_WITH_ECC);
+		}
+
+		break;
+	case SPINAND_ERASE:
+		*cmd = OP_BLOCK_ERASE | PAGE_ACC | LAST_PAGE | SPI_WP |
+			SPI_HOLD | SPI_TRANSFER_MODE_x1;
+		break;
+	case SPINAND_WRITE_EN:
+		*cmd = SPINAND_WRITE_EN;
+		break;
+	case SPINAND_PROGRAM_EXECUTE:
+		*cmd = (PAGE_ACC | LAST_PAGE | SPI_TRANSFER_MODE_x1 |
+				SPI_WP | SPI_HOLD | OP_PROGRAM_PAGE);
+		break;
+	case SPINAND_PROGRAM_LOAD:
+		*cmd = SPINAND_PROGRAM_LOAD;
+		break;
+	default:
+		dev_err(snandc->dev, "Opcode not supported: %u\n", opcode);
+		return -EOPNOTSUPP;
+	}
+
+	return 0;
+}
+
 static int qcom_spi_read_page(struct qcom_nand_controller *snandc,
 			      const struct spi_mem_op *op)
 {
@@ -1255,54 +1303,6 @@ static int qcom_spi_program_execute(struct qcom_nand_controller *snandc,
 	return 0;
 }
 
-static int qcom_spi_cmd_mapping(struct qcom_nand_controller *snandc, u32 opcode, u32 *cmd)
-{
-	switch (opcode) {
-	case SPINAND_RESET:
-		*cmd = (SPI_WP | SPI_HOLD | SPI_TRANSFER_MODE_x1 | OP_RESET_DEVICE);
-		break;
-	case SPINAND_READID:
-		*cmd = (SPI_WP | SPI_HOLD | SPI_TRANSFER_MODE_x1 | OP_FETCH_ID);
-		break;
-	case SPINAND_GET_FEATURE:
-		*cmd = (SPI_TRANSFER_MODE_x1 | SPI_WP | SPI_HOLD | ACC_FEATURE);
-		break;
-	case SPINAND_SET_FEATURE:
-		*cmd = (SPI_TRANSFER_MODE_x1 | SPI_WP | SPI_HOLD | ACC_FEATURE |
-			QPIC_SET_FEATURE);
-		break;
-	case SPINAND_READ:
-		if (snandc->qspi->raw_rw) {
-			*cmd = (PAGE_ACC | LAST_PAGE | SPI_TRANSFER_MODE_x1 |
-					SPI_WP | SPI_HOLD | OP_PAGE_READ);
-		} else {
-			*cmd = (PAGE_ACC | LAST_PAGE | SPI_TRANSFER_MODE_x1 |
-					SPI_WP | SPI_HOLD | OP_PAGE_READ_WITH_ECC);
-		}
-
-		break;
-	case SPINAND_ERASE:
-		*cmd = OP_BLOCK_ERASE | PAGE_ACC | LAST_PAGE | SPI_WP |
-			SPI_HOLD | SPI_TRANSFER_MODE_x1;
-		break;
-	case SPINAND_WRITE_EN:
-		*cmd = SPINAND_WRITE_EN;
-		break;
-	case SPINAND_PROGRAM_EXECUTE:
-		*cmd = (PAGE_ACC | LAST_PAGE | SPI_TRANSFER_MODE_x1 |
-				SPI_WP | SPI_HOLD | OP_PROGRAM_PAGE);
-		break;
-	case SPINAND_PROGRAM_LOAD:
-		*cmd = SPINAND_PROGRAM_LOAD;
-		break;
-	default:
-		dev_err(snandc->dev, "Opcode not supported: %u\n", opcode);
-		return -EOPNOTSUPP;
-	}
-
-	return 0;
-}
-
 static int qcom_spi_write_page(struct qcom_nand_controller *snandc,
 			       const struct spi_mem_op *op)
 {

-- 
2.34.1


^ permalink raw reply	[flat|nested] 6+ messages in thread

* [PATCH 2/3] spi: spi-qpic-snand: add quad mode support
  2026-07-16  5:27 [PATCH 0/3] Add quad mode support for QPIC SNAND Md Sadre Alam
  2026-07-16  5:27 ` [PATCH 1/3] spi: spi-qpic-snand: move command mapping helper Md Sadre Alam
@ 2026-07-16  5:27 ` Md Sadre Alam
  2026-07-29 14:46   ` Mark Brown
  2026-07-16  5:27 ` [PATCH 3/3] spi: spi-qpic-snand: Handle Macronix quad read opcode 0x6b Md Sadre Alam
  2 siblings, 1 reply; 6+ messages in thread
From: Md Sadre Alam @ 2026-07-16  5:27 UTC (permalink / raw)
  To: Mark Brown; +Cc: linux-spi, linux-kernel, Md Sadre Alam, Md Sadre Alam

Add support for quad (x4) transfer mode in the QPIC SPI NAND driver.
The controller supports both single (x1) and quad (x4) SPI transfers,
but the driver currently operates only in x1 mode.

Track the QUAD enable state from the device configuration register
(0xB0) and switch the data transfer width accordingly. When the core
enables quad mode, use x4 transfers for read and program operations to
improve throughput.

Introduce a quad_mode flag in struct qpic_spi_nand to cache the current
device state. The flag is updated based on GET_FEATURE responses from
the configuration register.

Signed-off-by: Md Sadre Alam <md.alam@oss.qualcomm.com>
---
 drivers/spi/spi-qpic-snand.c | 67 ++++++++++++++++++++++++++++++++++++++------
 1 file changed, 58 insertions(+), 9 deletions(-)

diff --git a/drivers/spi/spi-qpic-snand.c b/drivers/spi/spi-qpic-snand.c
index b96b6d149ca5..5c077f7023f1 100644
--- a/drivers/spi/spi-qpic-snand.c
+++ b/drivers/spi/spi-qpic-snand.c
@@ -46,14 +46,19 @@
 
 #define SPINAND_RESET			0xff
 #define SPINAND_READID			0x9f
+#define SPINAND_FEATURE_ADDR		0xb0
 #define SPINAND_GET_FEATURE		0x0f
 #define SPINAND_SET_FEATURE		0x1f
+#define SPINAND_READ_CACHE		0x0b
 #define SPINAND_READ			0x13
+#define SPINAND_READ_QUAD		0xeb
 #define SPINAND_ERASE			0xd8
 #define SPINAND_WRITE_EN		0x06
 #define SPINAND_PROGRAM_EXECUTE		0x10
 #define SPINAND_PROGRAM_LOAD		0x84
+#define SPINAND_PROGRAM_LOAD_QUAD	0x34
 
+#define QUAD_WIDTH			0x4
 #define ACC_FEATURE			0xe
 #define BAD_BLOCK_MARKER_SIZE		0x2
 #define OOB_BUF_SIZE			128
@@ -114,6 +119,7 @@ struct qpic_spi_nand {
 	bool oob_rw;
 	bool page_rw;
 	bool raw_rw;
+	bool quad_mode;
 };
 
 static void qcom_spi_set_read_loc_first(struct qcom_nand_controller *snandc,
@@ -991,8 +997,15 @@ static int qcom_spi_read_page_oob(struct qcom_nand_controller *snandc,
 	return qcom_spi_check_error(snandc);
 }
 
-static int qcom_spi_cmd_mapping(struct qcom_nand_controller *snandc, u32 opcode, u32 *cmd)
+static int qcom_spi_cmd_mapping(struct qcom_nand_controller *snandc,
+				const struct spi_mem_op *op, u32 *cmd)
 {
+	u32 opcode = op->cmd.opcode;
+	u32 transfer_mode = SPI_TRANSFER_MODE_x1;
+
+	if (snandc->qspi->quad_mode && op->data.buswidth == QUAD_WIDTH)
+		transfer_mode = SPI_TRANSFER_MODE_x4;
+
 	switch (opcode) {
 	case SPINAND_RESET:
 		*cmd = (SPI_WP | SPI_HOLD | SPI_TRANSFER_MODE_x1 | OP_RESET_DEVICE);
@@ -1008,11 +1021,13 @@ static int qcom_spi_cmd_mapping(struct qcom_nand_controller *snandc, u32 opcode,
 			QPIC_SET_FEATURE);
 		break;
 	case SPINAND_READ:
+	case SPINAND_READ_QUAD:
+	case SPINAND_READ_CACHE:
 		if (snandc->qspi->raw_rw) {
-			*cmd = (PAGE_ACC | LAST_PAGE | SPI_TRANSFER_MODE_x1 |
+			*cmd = (PAGE_ACC | LAST_PAGE | transfer_mode |
 					SPI_WP | SPI_HOLD | OP_PAGE_READ);
 		} else {
-			*cmd = (PAGE_ACC | LAST_PAGE | SPI_TRANSFER_MODE_x1 |
+			*cmd = (PAGE_ACC | LAST_PAGE | transfer_mode |
 					SPI_WP | SPI_HOLD | OP_PAGE_READ_WITH_ECC);
 		}
 
@@ -1025,12 +1040,16 @@ static int qcom_spi_cmd_mapping(struct qcom_nand_controller *snandc, u32 opcode,
 		*cmd = SPINAND_WRITE_EN;
 		break;
 	case SPINAND_PROGRAM_EXECUTE:
-		*cmd = (PAGE_ACC | LAST_PAGE | SPI_TRANSFER_MODE_x1 |
-				SPI_WP | SPI_HOLD | OP_PROGRAM_PAGE);
+		if (snandc->qspi->quad_mode)
+			*cmd = (PAGE_ACC | LAST_PAGE | transfer_mode |
+					SPI_WP | SPI_HOLD | OP_PROGRAM_PAGE);
 		break;
 	case SPINAND_PROGRAM_LOAD:
 		*cmd = SPINAND_PROGRAM_LOAD;
 		break;
+	case SPINAND_PROGRAM_LOAD_QUAD:
+		*cmd = SPINAND_PROGRAM_LOAD_QUAD;
+		break;
 	default:
 		dev_err(snandc->dev, "Opcode not supported: %u\n", opcode);
 		return -EOPNOTSUPP;
@@ -1042,6 +1061,15 @@ static int qcom_spi_cmd_mapping(struct qcom_nand_controller *snandc, u32 opcode,
 static int qcom_spi_read_page(struct qcom_nand_controller *snandc,
 			      const struct spi_mem_op *op)
 {
+	int ret;
+	u32 cmd;
+	/* Call mapping once again to update the quad mode based on
+	 * buswidth
+	 */
+	ret = qcom_spi_cmd_mapping(snandc, op, &cmd);
+	if (ret < 0)
+		return ret;
+
 	if (snandc->qspi->page_rw && snandc->qspi->raw_rw)
 		return qcom_spi_read_page_raw(snandc, op);
 
@@ -1309,11 +1337,12 @@ static int qcom_spi_write_page(struct qcom_nand_controller *snandc,
 	int ret;
 	u32 cmd;
 
-	ret = qcom_spi_cmd_mapping(snandc, op->cmd.opcode, &cmd);
+	ret = qcom_spi_cmd_mapping(snandc, op, &cmd);
 	if (ret < 0)
 		return ret;
 
-	if (op->cmd.opcode == SPINAND_PROGRAM_LOAD)
+	if (op->cmd.opcode == SPINAND_PROGRAM_LOAD ||
+	    op->cmd.opcode == SPINAND_PROGRAM_LOAD_QUAD)
 		snandc->qspi->data_buf = (u8 *)op->data.buf.out;
 
 	return 0;
@@ -1325,7 +1354,7 @@ static int qcom_spi_send_cmdaddr(struct qcom_nand_controller *snandc,
 	u32 cmd;
 	int ret, opcode;
 
-	ret = qcom_spi_cmd_mapping(snandc, op->cmd.opcode, &cmd);
+	ret = qcom_spi_cmd_mapping(snandc, op, &cmd);
 	if (ret < 0)
 		return ret;
 
@@ -1430,6 +1459,22 @@ static int qcom_spi_io_op(struct qcom_nand_controller *snandc, const struct spi_
 		val = le32_to_cpu(*(__le32 *)snandc->reg_read_buf);
 		val >>= 8;
 		memcpy(op->data.buf.in, &val, snandc->buf_count);
+
+		/*
+		 * Track QUAD mode state from configuration register.
+		 * When core layer reads register 0xB0 (CFG), check if
+		 * QUAD enable bit (bit 0) is set and update our state
+		 * accordingly for future READ/WRITE operations.
+		 */
+		if (op->addr.val == SPINAND_FEATURE_ADDR) {
+			bool quad_enabled = !!((u8)val & BIT(0));
+
+			if (snandc->qspi->quad_mode != quad_enabled) {
+				snandc->qspi->quad_mode = quad_enabled;
+				dev_info(snandc->dev, "SPI NAND QUAD mode: %s\n",
+					 quad_enabled ? "enabled" : "disabled");
+			}
+		}
 	}
 
 	return 0;
@@ -1470,7 +1515,8 @@ static bool qcom_spi_supports_op(struct spi_mem *mem, const struct spi_mem_op *o
 
 	return ((!op->addr.nbytes || op->addr.buswidth == 1) &&
 		(!op->dummy.nbytes || op->dummy.buswidth == 1) &&
-		(!op->data.nbytes || op->data.buswidth == 1));
+		(!op->data.nbytes || op->data.buswidth == 1 ||
+		 op->data.buswidth == 4));
 }
 
 static int qcom_spi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
@@ -1521,6 +1567,9 @@ static int qcom_spi_probe(struct platform_device *pdev)
 	if (!qspi)
 		return -ENOMEM;
 
+	/* Initialize QUAD mode state */
+	qspi->quad_mode = false;
+
 	ctlr = __devm_spi_alloc_controller(dev, sizeof(*snandc), false);
 	if (!ctlr)
 		return -ENOMEM;

-- 
2.34.1


^ permalink raw reply	[flat|nested] 6+ messages in thread

* Re: [PATCH 2/3] spi: spi-qpic-snand: add quad mode support
  2026-07-16  5:27 ` [PATCH 2/3] spi: spi-qpic-snand: add quad mode support Md Sadre Alam
@ 2026-07-29 14:46   ` Mark Brown
  2026-08-07 16:22     ` Md Sadre Alam
  0 siblings, 1 reply; 6+ messages in thread
From: Mark Brown @ 2026-07-29 14:46 UTC (permalink / raw)
  To: Md Sadre Alam; +Cc: linux-spi, linux-kernel, Md Sadre Alam

[-- Attachment #1: Type: text/plain, Size: 1409 bytes --]

On Thu, Jul 16, 2026 at 10:57:46AM +0530, Md Sadre Alam wrote:
> Add support for quad (x4) transfer mode in the QPIC SPI NAND driver.
> The controller supports both single (x1) and quad (x4) SPI transfers,
> but the driver currently operates only in x1 mode.

> @@ -1025,12 +1040,16 @@ static int qcom_spi_cmd_mapping(struct qcom_nand_controller *snandc, u32 opcode,
>  		*cmd = SPINAND_WRITE_EN;
>  		break;
>  	case SPINAND_PROGRAM_EXECUTE:
> -		*cmd = (PAGE_ACC | LAST_PAGE | SPI_TRANSFER_MODE_x1 |
> -				SPI_WP | SPI_HOLD | OP_PROGRAM_PAGE);
> +		if (snandc->qspi->quad_mode)
> +			*cmd = (PAGE_ACC | LAST_PAGE | transfer_mode |
> +					SPI_WP | SPI_HOLD | OP_PROGRAM_PAGE);

This succeeds but does not initialize cmd, previously we'd accept and
use x1.

> @@ -1042,6 +1061,15 @@ static int qcom_spi_cmd_mapping(struct qcom_nand_controller *snandc, u32 opcode,
>  static int qcom_spi_read_page(struct qcom_nand_controller *snandc,
>  			      const struct spi_mem_op *op)
>  {
> +	int ret;
> +	u32 cmd;
> +	/* Call mapping once again to update the quad mode based on
> +	 * buswidth
> +	 */
> +	ret = qcom_spi_cmd_mapping(snandc, op, &cmd);
> +	if (ret < 0)
> +		return ret;
> +
>  	if (snandc->qspi->page_rw && snandc->qspi->raw_rw)
>  		return qcom_spi_read_page_raw(snandc, op);

We never reference cmd in the rest of the function, either we didn't
need to do the mapping or there's a missing update.

[-- Attachment #2: signature.asc --]
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^ permalink raw reply	[flat|nested] 6+ messages in thread

* Re: [PATCH 2/3] spi: spi-qpic-snand: add quad mode support
  2026-07-29 14:46   ` Mark Brown
@ 2026-08-07 16:22     ` Md Sadre Alam
  0 siblings, 0 replies; 6+ messages in thread
From: Md Sadre Alam @ 2026-08-07 16:22 UTC (permalink / raw)
  To: Mark Brown; +Cc: linux-spi, linux-kernel, Md Sadre Alam

On Wed, Jul 29, 2026 at 03:46:43PM +0100, Mark Brown wrote:
> On Thu, Jul 16, 2026 at 10:57:46AM +0530, Md Sadre Alam wrote:
> > Add support for quad (x4) transfer mode in the QPIC SPI NAND driver.
> > The controller supports both single (x1) and quad (x4) SPI transfers,
> > but the driver currently operates only in x1 mode.
> 
> > @@ -1025,12 +1040,16 @@ static int qcom_spi_cmd_mapping(struct qcom_nand_controller *snandc, u32 opcode,
> >  		*cmd = SPINAND_WRITE_EN;
> >  		break;
> >  	case SPINAND_PROGRAM_EXECUTE:
> > -		*cmd = (PAGE_ACC | LAST_PAGE | SPI_TRANSFER_MODE_x1 |
> > -				SPI_WP | SPI_HOLD | OP_PROGRAM_PAGE);
> > +		if (snandc->qspi->quad_mode)
> > +			*cmd = (PAGE_ACC | LAST_PAGE | transfer_mode |
> > +					SPI_WP | SPI_HOLD | OP_PROGRAM_PAGE);
> 
> This succeeds but does not initialize cmd, previously we'd accept and
> use x1.
> 
> > @@ -1042,6 +1061,15 @@ static int qcom_spi_cmd_mapping(struct qcom_nand_controller *snandc, u32 opcode,
> >  static int qcom_spi_read_page(struct qcom_nand_controller *snandc,
> >  			      const struct spi_mem_op *op)
> >  {
> > +	int ret;
> > +	u32 cmd;
> > +	/* Call mapping once again to update the quad mode based on
> > +	 * buswidth
> > +	 */
> > +	ret = qcom_spi_cmd_mapping(snandc, op, &cmd);
> > +	if (ret < 0)
> > +		return ret;
> > +
> >  	if (snandc->qspi->page_rw && snandc->qspi->raw_rw)
> >  		return qcom_spi_read_page_raw(snandc, op);
> 
> We never reference cmd in the rest of the function, either we didn't
> need to do the mapping or there's a missing update.

I have addressed both the comments in revision 2 [1]. Please review.

Thanks
Alam

1 - https://lore.kernel.org/linux-arm-msm/20260807-quad-v2-0-8ec821e2f22b@oss.qualcomm.com/

^ permalink raw reply	[flat|nested] 6+ messages in thread

* [PATCH 3/3] spi: spi-qpic-snand: Handle Macronix quad read opcode 0x6b
  2026-07-16  5:27 [PATCH 0/3] Add quad mode support for QPIC SNAND Md Sadre Alam
  2026-07-16  5:27 ` [PATCH 1/3] spi: spi-qpic-snand: move command mapping helper Md Sadre Alam
  2026-07-16  5:27 ` [PATCH 2/3] spi: spi-qpic-snand: add quad mode support Md Sadre Alam
@ 2026-07-16  5:27 ` Md Sadre Alam
  2 siblings, 0 replies; 6+ messages in thread
From: Md Sadre Alam @ 2026-07-16  5:27 UTC (permalink / raw)
  To: Mark Brown; +Cc: linux-spi, linux-kernel, Md Sadre Alam, Md Sadre Alam

Macronix SPI-NAND devices use opcode 0x6b for quad output cache reads,
while most other devices use opcode 0xeb. The QPIC SPI-NAND driver does
not currently recognize opcode 0x6b, causing read operations to fail
when Macronix devices select this cache read variant.

Add the Macronix-specific read opcode to the command mapping logic and
treat it the same as the existing quad read operations.

This allows Macronix SPI-NAND devices to operate correctly in quad read
mode.

Signed-off-by: Md Sadre Alam <md.alam@oss.qualcomm.com>
---
 drivers/spi/spi-qpic-snand.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/spi/spi-qpic-snand.c b/drivers/spi/spi-qpic-snand.c
index 5c077f7023f1..e2f5dce15946 100644
--- a/drivers/spi/spi-qpic-snand.c
+++ b/drivers/spi/spi-qpic-snand.c
@@ -52,6 +52,7 @@
 #define SPINAND_READ_CACHE		0x0b
 #define SPINAND_READ			0x13
 #define SPINAND_READ_QUAD		0xeb
+#define SPINAND_READ_MACRONIX		0x6b
 #define SPINAND_ERASE			0xd8
 #define SPINAND_WRITE_EN		0x06
 #define SPINAND_PROGRAM_EXECUTE		0x10
@@ -1023,6 +1024,7 @@ static int qcom_spi_cmd_mapping(struct qcom_nand_controller *snandc,
 	case SPINAND_READ:
 	case SPINAND_READ_QUAD:
 	case SPINAND_READ_CACHE:
+	case SPINAND_READ_MACRONIX:
 		if (snandc->qspi->raw_rw) {
 			*cmd = (PAGE_ACC | LAST_PAGE | transfer_mode |
 					SPI_WP | SPI_HOLD | OP_PAGE_READ);

-- 
2.34.1


^ permalink raw reply	[flat|nested] 6+ messages in thread

end of thread, other threads:[~2026-08-07 16:22 UTC | newest]

Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2026-07-16  5:27 [PATCH 0/3] Add quad mode support for QPIC SNAND Md Sadre Alam
2026-07-16  5:27 ` [PATCH 1/3] spi: spi-qpic-snand: move command mapping helper Md Sadre Alam
2026-07-16  5:27 ` [PATCH 2/3] spi: spi-qpic-snand: add quad mode support Md Sadre Alam
2026-07-29 14:46   ` Mark Brown
2026-08-07 16:22     ` Md Sadre Alam
2026-07-16  5:27 ` [PATCH 3/3] spi: spi-qpic-snand: Handle Macronix quad read opcode 0x6b Md Sadre Alam

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