[PATCH 1/5] arm64: dts: qcom: nord-embedded: Fix i2c9/i2c10 pin functions

[Shawn Guo <shengchao.guo@oss.qualcomm.com>]

The i2c9/i2c10 and uart9/uart10 pinctrl states shared the same pins and
the same "qup1_se2"/"qup1_se3" function name, so the I2C states were
indistinguishable from the UART ones and ended up muxing the UART lanes.
i2c9 and i2c10 therefore did not work.

Now that the TLMM driver names each lane pair separately, select the
lane 0/1 function for I2C and the lane 2/3 function for UART.

Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/nord-embedded.dtsi | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/nord-embedded.dtsi b/arch/arm64/boot/dts/qcom/nord-embedded.dtsi
index a03ee16c9cff..c7ac2e66632e 100644
--- a/arch/arm64/boot/dts/qcom/nord-embedded.dtsi
+++ b/arch/arm64/boot/dts/qcom/nord-embedded.dtsi
@@ -1056,14 +1056,14 @@ qup_i2c8_default: qup-i2c8-default-state {
 
 	qup_i2c9_default: qup-i2c9-default-state {
 		pins = "gpio127", "gpio128";
-		function = "qup1_se2";
+		function = "qup1_se2_01";
 		drive-strength = <2>;
 		bias-pull-up;
 	};
 
 	qup_i2c10_default: qup-i2c10-default-state {
 		pins = "gpio129", "gpio130";
-		function = "qup1_se3";
+		function = "qup1_se3_01";
 		drive-strength = <2>;
 		bias-pull-up;
 	};
@@ -1461,14 +1461,14 @@ qup_uart8_default: qup-uart8-default-state {
 
 	qup_uart9_default: qup-uart9-default-state {
 		pins = "gpio127", "gpio128";
-		function = "qup1_se2";
+		function = "qup1_se2_23";
 		drive-strength = <2>;
 		bias-disable;
 	};
 
 	qup_uart10_default: qup-uart10-default-state {
 		pins = "gpio129", "gpio130";
-		function = "qup1_se3";
+		function = "qup1_se3_23";
 		drive-strength = <2>;
 		bias-disable;
 	};
-- 
2.43.0