[PATCH 00/10] media: rcar-fcp, vsp1: Enable on R-Car X5H

[PATCH 00/10] media: rcar-fcp, vsp1: Enable on R-Car X5H

[Paul Elder]

This series is based on Geert's
"topic/rcar-x5h-ironhide-scmi-cpg-mdlc-remapping-v3" branch [0]. A
branch including this series is available here [1].

This series enables the FCPV[BI] and the VSP[BI] blocks on the Renesas
R-Car X5H SoC.

This has been tested on an Ironhide with the vsp-tests test suite [2]:
148 tests: 142 passed, 0 failed, 6 skipped

There was some odd behavior with the clocks, where from what I
understood was that the clocks for the FCPV[BI] and VSP[BI] are
always-on, but the tests would hang unless I explicitly enabled...  the
always-on clock (or fsleep). Then after I removed the patch that
explicitly enabled the always-on clock everything ran fine. Just
reporting that this happened just in case it's relevant.

[0] https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git/log/?h=topic/rcar-x5h-ironhide-scmi-cpg-mdlc-remapping-v3
[1] https://git.ideasonboard.com/epaul/linux/src/branch/epaul/v7.3-rc1/x5h/vsp/fcp
[2] https://git.ideasonboard.com/renesas/vsp-tests/commit/900168f58c9d96be0592c2593f4d8f34edc9c69e

Signed-off-by: Paul Elder <paul.elder+renesas@ideasonboard.com>
---
Paul Elder (10):
      dt-bindings: clock: renesas,r8a78000-cpg: Add CPG_SGD4_VIO_DP_{TX,OTHER}
      clk: renesas: r8a78000: Add clock for FCPV and VSP for SCP FW SDKv4.36
      pmdomain: renesas: r8a78000: Add maps for VIO for SCP FW SDKv4.36
      arm64: renesas: r8a78000: Add FCPV[BI] nodes
      arm64: renesas: r8a78000: Add VSP[BI] nodes
      media: rcar-fcp: Check device revision at probe time
      media: rcar-fcp: Handle resets
      media: vsp1: Support full VSPB on R-Car M3-W, M3-N and E3
      media: vsp1: Document X5H SoC ID
      media: rcar-fcp: Add R-Car X5H support

 arch/arm64/boot/dts/renesas/r8a78000.dtsi        | 171 +++++++++++++++++++++++
 drivers/clk/renesas/r8a78000-cpg.c               |   2 +
 drivers/media/platform/renesas/rcar-fcp.c        | 162 +++++++++++++++++++--
 drivers/media/platform/renesas/vsp1/vsp1_drv.c   |  13 +-
 drivers/media/platform/renesas/vsp1/vsp1_regs.h  |   3 +-
 drivers/pmdomain/renesas/r8a78000-mdlc.c         |  34 ++++-
 include/dt-bindings/clock/renesas,r8a78000-cpg.h |   2 +
 7 files changed, 372 insertions(+), 15 deletions(-)
---
base-commit: 02c5d61866607bce0b3271e7c1b838c53dbedc55
change-id: 20260917-epaul-v7-3-rc1-x5h-vsp-fcp-8afdeb2740f7

Best regards,
-- 
Paul Elder <paul.elder+renesas@ideasonboard.com>

[PATCH 01/10] dt-bindings: clock: renesas,r8a78000-cpg: Add CPG_SGD4_VIO_DP_{TX,OTHER}

[Paul Elder]

Add preliminary clocks for testing:
- CPG_SGD4_VIO_DP_TX is used by FCP
- CPG_SGD4_VIO_DP_OTHER is used by VSP

Signed-off-by: Paul Elder <paul.elder+renesas@ideasonboard.com>
---
 include/dt-bindings/clock/renesas,r8a78000-cpg.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/dt-bindings/clock/renesas,r8a78000-cpg.h b/include/dt-bindings/clock/renesas,r8a78000-cpg.h
index 5851a29847f961b9b4ec270f263eb3aa19e45308..8c1a01e28ddbb26c583d7c9b387400ef6626c06c 100644
--- a/include/dt-bindings/clock/renesas,r8a78000-cpg.h
+++ b/include/dt-bindings/clock/renesas,r8a78000-cpg.h
@@ -12,5 +12,7 @@
 #define R8A78000_CPG_SGASYNCD16_PERW_BUS	2
 #define R8A78000_CPG_S0D4_PERE_MAIN		3	// FIXME Preliminary
 #define R8A78000_CPG_MSOCK_PERW_BUS		4	// FIXME Preliminary
+#define R8A78000_CPG_SGD4_VIO_DP_TX		5	// FIXME Preliminary
+#define R8A78000_CPG_SGD4_VIO_DP_OTHER		6	// FIXME Preliminary
 
 #endif /* __DT_BINDINGS_CLOCK_RENESAS_R8A78000_CPG_H__ */

-- 
2.47.3

[PATCH 02/10] clk: renesas: r8a78000: Add clock for FCPV and VSP for SCP FW SDKv4.36

[Paul Elder]

Add clocks for the FCPV{B,I,D} and VSP{B,I}. They each have one clock
from an option of two: a 1066MHz and a quarter-divided 266MHz. As we
already have support for the 266MHz one, add just those for now.

Signed-off-by: Paul Elder <paul.elder+renesas@ideasonboard.com>
---
 drivers/clk/renesas/r8a78000-cpg.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/clk/renesas/r8a78000-cpg.c b/drivers/clk/renesas/r8a78000-cpg.c
index b820d09e1a195068debe8a6eea7a01c534a97b23..17792ff6ab8ae2f7eb5c8f7e3d581b43177e195d 100644
--- a/drivers/clk/renesas/r8a78000-cpg.c
+++ b/drivers/clk/renesas/r8a78000-cpg.c
@@ -326,6 +326,8 @@ static const struct clk_map_in r8a78000_cpg_fw_4_31_0[] = {
 	{ R8A78000_CPG_SGASYNCD16_PERW_BUS,	FIXED_CLK(66M) },
 	{ R8A78000_CPG_S0D4_PERE_MAIN,		FIXED_CLK(200M) },
 	{ R8A78000_CPG_MSOCK_PERW_BUS,		1667 },
+	{ R8A78000_CPG_SGD4_VIO_DP_TX,		FIXED_CLK(266M)},
+	{ R8A78000_CPG_SGD4_VIO_DP_OTHER,	FIXED_CLK(266M)},
 	{ -1 }
 };
 

-- 
2.47.3

[PATCH 03/10] pmdomain: renesas: r8a78000: Add maps for VIO for SCP FW SDKv4.36

[Paul Elder]

Add maps for VIO for the VSP and FCP power domains and reset domains.

Signed-off-by: Paul Elder <paul.elder+renesas@ideasonboard.com>
---
 drivers/pmdomain/renesas/r8a78000-mdlc.c | 34 ++++++++++++++++++++++++++++++--
 1 file changed, 32 insertions(+), 2 deletions(-)

diff --git a/drivers/pmdomain/renesas/r8a78000-mdlc.c b/drivers/pmdomain/renesas/r8a78000-mdlc.c
index a0d83f27735e7deacb060e4102e510726b34e62e..c8d34376800982000cfa1b1ae6c279edd749ec9c 100644
--- a/drivers/pmdomain/renesas/r8a78000-mdlc.c
+++ b/drivers/pmdomain/renesas/r8a78000-mdlc.c
@@ -861,6 +861,36 @@ static const struct mdlc_info r8a78000_mdlc_fw_4_28_0[] = {
 	{ /* sentinel */ }
 };
 
+static const struct power_map_in r8a78000_mdlc_vio_power_fw_4_31_0[] = {
+	{ 0, 4 },	/* PD_VIO0 */
+	{ 1, 5 },	/* PD_VIO1 */
+	{ 2, 6 },	/* PD_VIO2 */
+	{ 3, 7 },	/* PD_VIO3 */
+	{ 7, 11 },	/* PD_VIO4 */
+	{ -1 }
+};
+static const struct mod_map_in r8a78000_mdlc_vio_mod_fw_4_31_0[] = {
+	{ 0xf9, 163 },	/* VSPB0 */
+	{ 0xfa, 164 },	/* VSPB1 */
+	{ 0xfb, 165 },	/* VSPB2 */
+	{ 0xfc, 166 },	/* VSPB3 */
+	{ 0xfd, 167 },	/* VSPB4 */
+	{ 0xfe, 168 },	/* VSPI0 */
+	{ 0xff, 169 },	/* VSPI1 */
+	{ 0x100, 170 },	/* VSPI2 */
+	{ 0x101, 171 },	/* VSPI3 */
+	{ 0x102, 172 },	/* FCPVB0 */
+	{ 0x103, 173 },	/* FCPVB1 */
+	{ 0x104, 174 },	/* FCPVB2 */
+	{ 0x105, 175 },	/* FCPVB3 */
+	{ 0x106, 176 },	/* FCPVB4 */
+	{ 0x107, 177 },	/* FCPVI0 */
+	{ 0x108, 178 },	/* FCPVI1 */
+	{ 0x109, 179 },	/* FCPVI2 */
+	{ 0x10a, 180 },	/* FCPVI3 */
+	{ -1 }
+};
+
 static const struct mod_map_in r8a78000_mdlc_pere_mod_fw_4_31_0[] = {
 	{ 0x30, 193 },	/* PERE_GPIODM0 */
 	// No CLOCK_ATTRIBUTES { 0x31, 194 },	/* PERE_GPIODM1 */
@@ -997,8 +1027,8 @@ static const struct mdlc_info r8a78000_mdlc_fw_4_31_0[] = {
 		/* FIXME .mod_map = r8a78000_mdlc_vips_mod_fw_4_31_0, */
 	}, {
 		.base = 0xc5000000 /* mdlc_vio */,
-		/* FIXME .power_map = r8a78000_mdlc_vio_power_fw_4_28_0, */
-		/* FIXME .mod_map = r8a78000_mdlc_vio_mod_fw_4_31_0, */
+		.power_map = r8a78000_mdlc_vio_power_fw_4_31_0,
+		.mod_map = r8a78000_mdlc_vio_mod_fw_4_31_0,
 	}, {
 		.base = 0xc08f0000 /* mdlc_pere */,
 		.power_map = r8a78000_mdlc_pere_power_fw_4_28_0,

-- 
2.47.3

[PATCH 04/10] arm64: renesas: r8a78000: Add FCPV[BI] nodes

[Paul Elder]

Add DT nodes for the FCPVB and FCPVI IP cores in the R-Car X5H Soc.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Paul Elder <paul.elder+renesas@ideasonboard.com>
---
 arch/arm64/boot/dts/renesas/r8a78000.dtsi | 72 +++++++++++++++++++++++++++++++
 1 file changed, 72 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a78000.dtsi b/arch/arm64/boot/dts/renesas/r8a78000.dtsi
index 9a07753b221541ed49a975e0c95f2f5d1fdc6ac2..2f8886f8b6545026397fd83969882f8c62afa9d3 100644
--- a/arch/arm64/boot/dts/renesas/r8a78000.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a78000.dtsi
@@ -1000,6 +1000,78 @@ mdlc_aon: system-controller@c1338000 {
 			bootph-all;
 		};
 
+		fcpvi0: fcp@c5030000 {
+			compatible = "renesas,fcpv";
+			reg = <0 0xc5030000 0 0x1000>;
+			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
+			power-domains = <&mdlc_vio 0x07 0x107>;
+			resets = <&mdlc_vio 0x107>;
+		};
+
+		fcpvi1: fcp@c5031000 {
+			compatible = "renesas,fcpv";
+			reg = <0 0xc5031000 0 0x1000>;
+			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
+			power-domains = <&mdlc_vio 0x07 0x108>;
+			resets = <&mdlc_vio 0x108>;
+		};
+
+		fcpvi2: fcp@c5032000 {
+			compatible = "renesas,fcpv";
+			reg = <0 0xc5032000 0 0x1000>;
+			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
+			power-domains = <&mdlc_vio 0x07 0x109>;
+			resets = <&mdlc_vio 0x109>;
+		};
+
+		fcpvi3: fcp@c5033000 {
+			compatible = "renesas,fcpv";
+			reg = <0 0xc5033000 0 0x1000>;
+			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
+			power-domains = <&mdlc_vio 0x07 0x10a>;
+			resets = <&mdlc_vio 0x10a>;
+		};
+
+		fcpvb0: fcp@c5038000 {
+			compatible = "renesas,fcpv";
+			reg = <0 0xc5038000 0 0x1000>;
+			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
+			power-domains = <&mdlc_vio 0x07 0x102>;
+			resets = <&mdlc_vio 0x102>;
+		};
+
+		fcpvb1: fcp@c5039000 {
+			compatible = "renesas,fcpv";
+			reg = <0 0xc5039000 0 0x1000>;
+			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
+			power-domains = <&mdlc_vio 0x07 0x103>;
+			resets = <&mdlc_vio 0x103>;
+		};
+
+		fcpvb2: fcp@c503a000 {
+			compatible = "renesas,fcpv";
+			reg = <0 0xc503a000 0 0x1000>;
+			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
+			power-domains = <&mdlc_vio 0x07 0x104>;
+			resets = <&mdlc_vio 0x104>;
+		};
+
+		fcpvb3: fcp@c503b000 {
+			compatible = "renesas,fcpv";
+			reg = <0 0xc503b000 0 0x1000>;
+			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
+			power-domains = <&mdlc_vio 0x07 0x105>;
+			resets = <&mdlc_vio 0x105>;
+		};
+
+		fcpvb4: fcp@c503c000 {
+			compatible = "renesas,fcpv";
+			reg = <0 0xc503c000 0 0x1000>;
+			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
+			power-domains = <&mdlc_vio 0x07 0x106>;
+			resets = <&mdlc_vio 0x106>;
+		};
+
 		mdlc_cmnn: system-controller@ca410000 {
 			compatible = "renesas,r8a78000-mdlc";
 			reg = <0 0xca410000 0 0x1000>;

-- 
2.47.3

[PATCH 05/10] arm64: renesas: r8a78000: Add VSP[BI] nodes

[Paul Elder]

Add DT nodes for the VSPB and VSPI IP cores in the R-Car X5H Soc.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Paul Elder <paul.elder+renesas@ideasonboard.com>
---
 arch/arm64/boot/dts/renesas/r8a78000.dtsi | 99 +++++++++++++++++++++++++++++++
 1 file changed, 99 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a78000.dtsi b/arch/arm64/boot/dts/renesas/r8a78000.dtsi
index 2f8886f8b6545026397fd83969882f8c62afa9d3..f90b869579d384e3fc13d0a13625b7cddaac2868 100644
--- a/arch/arm64/boot/dts/renesas/r8a78000.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a78000.dtsi
@@ -1072,6 +1072,105 @@ fcpvb4: fcp@c503c000 {
 			resets = <&mdlc_vio 0x106>;
 		};
 
+		vspi0: vsp@c5080000 {
+			compatible = "renesas,vsp2";
+			reg = <0 0xc5080000 0 0x8000>;
+			interrupts = <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_OTHER>;
+			power-domains = <&mdlc_vio 0x07 0xfe>;
+			resets = <&mdlc_vio 0xfe>;
+
+			renesas,fcp = <&fcpvi0>;
+		};
+
+		vspi1: vsp@c5088000 {
+			compatible = "renesas,vsp2";
+			reg = <0 0xc5088000 0 0x8000>;
+			interrupts = <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_OTHER>;
+			power-domains = <&mdlc_vio 0x07 0xff>;
+			resets = <&mdlc_vio 0xff>;
+
+			renesas,fcp = <&fcpvi1>;
+		};
+
+		vspi2: vsp@c5090000 {
+			compatible = "renesas,vsp2";
+			reg = <0 0xc5090000 0 0x8000>;
+			interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_OTHER>;
+			power-domains = <&mdlc_vio 0x07 0x100>;
+			resets = <&mdlc_vio 0x100>;
+
+			renesas,fcp = <&fcpvi2>;
+		};
+
+		vspi3: vsp@c5098000 {
+			compatible = "renesas,vsp2";
+			reg = <0 0xc5098000 0 0x8000>;
+			interrupts = <GIC_SPI 646 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_OTHER>;
+			power-domains = <&mdlc_vio 0x07 0x101>;
+			resets = <&mdlc_vio 0x101>;
+
+			renesas,fcp = <&fcpvi3>;
+		};
+
+		vspb0: vsp@c50c0000 {
+			compatible = "renesas,vsp2";
+			reg = <0 0xc50c0000 0 0x8000>;
+			interrupts = <GIC_SPI 618 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_OTHER>;
+			power-domains = <&mdlc_vio 0x07 0xf9>;
+			resets = <&mdlc_vio 0xf9>;
+
+			renesas,fcp = <&fcpvb0>;
+		};
+
+		vspb1: vsp@c50c8000 {
+			compatible = "renesas,vsp2";
+			reg = <0 0xc50c8000 0 0x8000>;
+			interrupts = <GIC_SPI 619 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_OTHER>;
+			power-domains = <&mdlc_vio 0x07 0xfa>;
+			resets = <&mdlc_vio 0xfa>;
+
+			renesas,fcp = <&fcpvb1>;
+		};
+
+		vspb2: vsp@c50d0000 {
+			compatible = "renesas,vsp2";
+			reg = <0 0xc50d0000 0 0x8000>;
+			interrupts = <GIC_SPI 620 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_OTHER>;
+			power-domains = <&mdlc_vio 0x07 0xfb>;
+			resets = <&mdlc_vio 0xfb>;
+
+			renesas,fcp = <&fcpvb2>;
+		};
+
+		vspb3: vsp@c50d8000 {
+			compatible = "renesas,vsp2";
+			reg = <0 0xc50d8000 0 0x8000>;
+			interrupts = <GIC_SPI 621 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_OTHER>;
+			power-domains = <&mdlc_vio 0x07 0xfc>;
+			resets = <&mdlc_vio 0xfc>;
+
+			renesas,fcp = <&fcpvb3>;
+		};
+
+		vspb4: vsp@c50e0000 {
+			compatible = "renesas,vsp2";
+			reg = <0 0xc50e0000 0 0x8000>;
+			interrupts = <GIC_SPI 622 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_OTHER>;
+			power-domains = <&mdlc_vio 0x07 0xfd>;
+			resets = <&mdlc_vio 0xfd>;
+
+			renesas,fcp = <&fcpvb4>;
+		};
+
 		mdlc_cmnn: system-controller@ca410000 {
 			compatible = "renesas,r8a78000-mdlc";
 			reg = <0 0xca410000 0 0x1000>;

-- 
2.47.3

[PATCH 06/10] media: rcar-fcp: Check device revision at probe time

[Paul Elder]

Verify that the device revision register reports a valid value,
otherwise reject the device.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Paul Elder <paul.elder+renesas@ideasonboard.com>
---
Changes since v2:

- Add FCP type information
- Reject devices with an unsupported version

Changes since v1:

- Use devm_platform_ioremap_resource()
---
 drivers/media/platform/renesas/rcar-fcp.c | 130 +++++++++++++++++++++++++++---
 1 file changed, 119 insertions(+), 11 deletions(-)

diff --git a/drivers/media/platform/renesas/rcar-fcp.c b/drivers/media/platform/renesas/rcar-fcp.c
index dfb0ca93e854dd0bb8aedfb757fd786ef6e45542..d99b3ff976e80f275af19e5dc02c6e1de98c38a3 100644
--- a/drivers/media/platform/renesas/rcar-fcp.c
+++ b/drivers/media/platform/renesas/rcar-fcp.c
@@ -14,26 +14,75 @@
 #include <linux/list.h>
 #include <linux/module.h>
 #include <linux/mutex.h>
+#include <linux/of_device.h>
 #include <linux/platform_device.h>
 #include <linux/pm_runtime.h>
+#include <linux/property.h>
 #include <linux/slab.h>
 
 #include <media/rcar-fcp.h>
 
-#define RCAR_FCP_REG_RST		0x0010
-#define RCAR_FCP_REG_RST_SOFTRST	BIT(0)
-#define RCAR_FCP_REG_STA		0x0018
-#define RCAR_FCP_REG_STA_ACT		BIT(0)
+#define RCAR_FCP_REG_VCR			0x0000
+#define RCAR_FCP_REG_VCR_CATEGORY		(1 << 8)
+#define RCAR_FCP_REG_VCR_REVISION_H3_ES1	(1 << 0)
+#define RCAR_FCP_REG_VCR_REVISION_M3W		(2 << 0)
+#define RCAR_FCP_REG_VCR_REVISION_V3M		(3 << 0)
+#define RCAR_FCP_REG_VCR_REVISION_H3		(4 << 0)
+#define RCAR_FCP_REG_VCR_REVISION_D3		(5 << 0)
+#define RCAR_FCP_REG_VCR_REVISION_M3N		(6 << 0)
+#define RCAR_FCP_REG_VCR_REVISION_V3H		(7 << 0)
+#define RCAR_FCP_REG_VCR_REVISION_E3		(8 << 0)
+
+#define RCAR_FCP_REG_CFG0			0x0004
+#define RCAR_FCP_REG_CFG0_FCPVSEL		BIT(1)
+
+#define RCAR_FCP_REG_RST			0x0010
+#define RCAR_FCP_REG_RST_RIIFRST		BIT(22)
+#define RCAR_FCP_REG_RST_RSIFRST		BIT(21)
+#define RCAR_FCP_REG_RST_DCMPRST		BIT(20)
+#define RCAR_FCP_REG_RST_MODRST			BIT(4)
+#define RCAR_FCP_REG_RST_SOFTRST		BIT(0)
+
+#define RCAR_FCP_REG_STA			0x0018
+#define RCAR_FCP_REG_STA_ACT			BIT(0)
+
+#define RCAR_FCP_REG_TL_CTRL			0x0070
+#define RCAR_FCP_REG_TL_CTRL_TLEN		BIT(31)
+#define RCAR_FCP_REG_TL_CTRL_VPOS_C(n)		((n) << 16)
+#define RCAR_FCP_REG_TL_CTRL_VPOS_Y(n)		((n) << 0)
+
+#define RCAR_FCP_REG_PICINFO1			0x00c4
+#define RCAR_FCP_REG_PICINFO1_STRIDE_DIV16	((n) << 0)
+
+#define RCAR_FCP_REG_BA_ANC_Y0			0x0100
+#define RCAR_FCP_REG_BA_ANC_Y1			0x0104
+#define RCAR_FCP_REG_BA_ANC_Y2			0x0108
+#define RCAR_FCP_REG_BA_ANC_C			0x010c
+#define RCAR_FCP_REG_BA_REF_Y0			0x0110
+#define RCAR_FCP_REG_BA_REF_Y1			0x0114
+#define RCAR_FCP_REG_BA_REF_Y2			0x0118
+#define RCAR_FCP_REG_BA_REF_C			0x011c
+
+enum rcar_fcp_type {
+	RCAR_FCPF,
+	RCAR_FCPV,
+};
 
 struct rcar_fcp_device {
 	struct list_head list;
 	struct device *dev;
 	void __iomem *base;
+	enum rcar_fcp_type type;
 };
 
 static LIST_HEAD(fcp_devices);
 static DEFINE_MUTEX(fcp_lock);
 
+static inline u32 rcar_fcp_read(struct rcar_fcp_device *fcp, u32 reg)
+{
+	return ioread32(fcp->base + reg);
+}
+
 static inline void rcar_fcp_write(struct rcar_fcp_device *fcp, u32 reg, u32 val)
 {
 	iowrite32(val, fcp->base + reg);
@@ -152,15 +201,66 @@ EXPORT_SYMBOL_GPL(rcar_fcp_soft_reset);
  * Platform Driver
  */
 
+static int rcar_fcp_setup(struct rcar_fcp_device *fcp)
+{
+	static const char * const models[] = {
+		[RCAR_FCPF] = "FCPF",
+		[RCAR_FCPV] = "FCPV",
+	};
+	static struct {
+		u32 version;
+		const char *name;
+	} versions[] = {
+		{ RCAR_FCP_REG_VCR_CATEGORY | RCAR_FCP_REG_VCR_REVISION_H3_ES1, "H3 ES1.x" },
+		{ RCAR_FCP_REG_VCR_CATEGORY | RCAR_FCP_REG_VCR_REVISION_M3W, "M3W" },
+		{ RCAR_FCP_REG_VCR_CATEGORY | RCAR_FCP_REG_VCR_REVISION_V3M, "V3M" },
+		{ RCAR_FCP_REG_VCR_CATEGORY | RCAR_FCP_REG_VCR_REVISION_H3, "H3" },
+		{ RCAR_FCP_REG_VCR_CATEGORY | RCAR_FCP_REG_VCR_REVISION_D3, "D3" },
+		{ RCAR_FCP_REG_VCR_CATEGORY | RCAR_FCP_REG_VCR_REVISION_M3N, "M3N" },
+		{ RCAR_FCP_REG_VCR_CATEGORY | RCAR_FCP_REG_VCR_REVISION_V3H, "V3H" },
+		{ RCAR_FCP_REG_VCR_CATEGORY | RCAR_FCP_REG_VCR_REVISION_E3, "E3" },
+	};
+
+	unsigned int i;
+	u32 version;
+
+	/* Check the device version register. */
+	version = rcar_fcp_read(fcp, RCAR_FCP_REG_VCR);
+
+	for (i = 0; i < ARRAY_SIZE(versions); ++i) {
+		if (versions[i].version == version)
+			break;
+	}
+
+	if (i >= ARRAY_SIZE(versions)) {
+		dev_err(fcp->dev, "Invalid FCP version 0x%08x\n", version);
+		return -ENODEV;
+	}
+
+	dev_dbg(fcp->dev, "%s %s device found\n", models[fcp->type],
+		versions[i].name);
+
+	return 0;
+}
+
+static const struct of_device_id rcar_fcp_of_match[] = {
+	{ .compatible = "renesas,fcpf", .data = (void *)RCAR_FCPF },
+	{ .compatible = "renesas,fcpv", .data = (void *)RCAR_FCPV },
+	{ },
+};
+MODULE_DEVICE_TABLE(of, rcar_fcp_of_match);
+
 static int rcar_fcp_probe(struct platform_device *pdev)
 {
 	struct rcar_fcp_device *fcp;
+	int ret;
 
 	fcp = devm_kzalloc(&pdev->dev, sizeof(*fcp), GFP_KERNEL);
 	if (fcp == NULL)
 		return -ENOMEM;
 
 	fcp->dev = &pdev->dev;
+	fcp->type = (enum rcar_fcp_type)device_get_match_data(&pdev->dev);
 
 	fcp->base = devm_platform_ioremap_resource(pdev, 0);
 	if (IS_ERR(fcp->base))
@@ -169,6 +269,15 @@ static int rcar_fcp_probe(struct platform_device *pdev)
 	dma_set_max_seg_size(fcp->dev, UINT_MAX);
 
 	pm_runtime_enable(&pdev->dev);
+	ret = pm_runtime_resume_and_get(&pdev->dev);
+	if (ret < 0)
+		goto error_pm_disable;
+
+	ret = rcar_fcp_setup(fcp);
+	if (ret < 0)
+		goto error_pm_put;
+
+	pm_runtime_put(&pdev->dev);
 
 	mutex_lock(&fcp_lock);
 	list_add_tail(&fcp->list, &fcp_devices);
@@ -177,6 +286,12 @@ static int rcar_fcp_probe(struct platform_device *pdev)
 	platform_set_drvdata(pdev, fcp);
 
 	return 0;
+
+error_pm_put:
+	pm_runtime_put(&pdev->dev);
+error_pm_disable:
+	pm_runtime_disable(&pdev->dev);
+	return ret;
 }
 
 static void rcar_fcp_remove(struct platform_device *pdev)
@@ -190,13 +305,6 @@ static void rcar_fcp_remove(struct platform_device *pdev)
 	pm_runtime_disable(&pdev->dev);
 }
 
-static const struct of_device_id rcar_fcp_of_match[] = {
-	{ .compatible = "renesas,fcpf" },
-	{ .compatible = "renesas,fcpv" },
-	{ },
-};
-MODULE_DEVICE_TABLE(of, rcar_fcp_of_match);
-
 static struct platform_driver rcar_fcp_platform_driver = {
 	.probe		= rcar_fcp_probe,
 	.remove		= rcar_fcp_remove,

-- 
2.47.3

[PATCH 07/10] media: rcar-fcp: Handle resets

[Paul Elder]

On some versions of the FCP, such as the one on the X5H, reset control
is required to operate the FCP. Add support for handling resets
optionally, to continue supporting versions that do not require it.

Signed-off-by: Paul Elder <paul.elder+renesas@ideasonboard.com>
---
 drivers/media/platform/renesas/rcar-fcp.c | 34 +++++++++++++++++++++++++++++--
 1 file changed, 32 insertions(+), 2 deletions(-)

diff --git a/drivers/media/platform/renesas/rcar-fcp.c b/drivers/media/platform/renesas/rcar-fcp.c
index d99b3ff976e80f275af19e5dc02c6e1de98c38a3..15bcbbda3b853f71780aae876f6440b33addf193 100644
--- a/drivers/media/platform/renesas/rcar-fcp.c
+++ b/drivers/media/platform/renesas/rcar-fcp.c
@@ -18,6 +18,7 @@
 #include <linux/platform_device.h>
 #include <linux/pm_runtime.h>
 #include <linux/property.h>
+#include <linux/reset.h>
 #include <linux/slab.h>
 
 #include <media/rcar-fcp.h>
@@ -63,6 +64,8 @@
 #define RCAR_FCP_REG_BA_REF_Y2			0x0118
 #define RCAR_FCP_REG_BA_REF_C			0x011c
 
+struct reset_control;
+
 enum rcar_fcp_type {
 	RCAR_FCPF,
 	RCAR_FCPV,
@@ -73,6 +76,7 @@ struct rcar_fcp_device {
 	struct device *dev;
 	void __iomem *base;
 	enum rcar_fcp_type type;
+	struct reset_control *rstc;
 };
 
 static LIST_HEAD(fcp_devices);
@@ -262,12 +266,19 @@ static int rcar_fcp_probe(struct platform_device *pdev)
 	fcp->dev = &pdev->dev;
 	fcp->type = (enum rcar_fcp_type)device_get_match_data(&pdev->dev);
 
+	platform_set_drvdata(pdev, fcp);
+
 	fcp->base = devm_platform_ioremap_resource(pdev, 0);
 	if (IS_ERR(fcp->base))
 		return PTR_ERR(fcp->base);
 
 	dma_set_max_seg_size(fcp->dev, UINT_MAX);
 
+	fcp->rstc = devm_reset_control_get_optional(&pdev->dev, NULL);
+	if (IS_ERR(fcp->rstc))
+		return dev_err_probe(&pdev->dev, PTR_ERR(fcp->rstc),
+				     "failed to get reset control\n");
+
 	pm_runtime_enable(&pdev->dev);
 	ret = pm_runtime_resume_and_get(&pdev->dev);
 	if (ret < 0)
@@ -283,8 +294,6 @@ static int rcar_fcp_probe(struct platform_device *pdev)
 	list_add_tail(&fcp->list, &fcp_devices);
 	mutex_unlock(&fcp_lock);
 
-	platform_set_drvdata(pdev, fcp);
-
 	return 0;
 
 error_pm_put:
@@ -305,11 +314,32 @@ static void rcar_fcp_remove(struct platform_device *pdev)
 	pm_runtime_disable(&pdev->dev);
 }
 
+static int fcp_pm_runtime_suspend(struct device *dev)
+{
+	struct rcar_fcp_device *fcp = dev_get_drvdata(dev);
+
+	reset_control_assert(fcp->rstc);
+	return 0;
+}
+
+static int fcp_pm_runtime_resume(struct device *dev)
+{
+	struct rcar_fcp_device *fcp = dev_get_drvdata(dev);
+
+	reset_control_deassert(fcp->rstc);
+	return 0;
+}
+
+static const struct dev_pm_ops fcp_pm_ops = {
+	RUNTIME_PM_OPS(fcp_pm_runtime_suspend, fcp_pm_runtime_resume, NULL)
+};
+
 static struct platform_driver rcar_fcp_platform_driver = {
 	.probe		= rcar_fcp_probe,
 	.remove		= rcar_fcp_remove,
 	.driver		= {
 		.name	= "rcar-fcp",
+		.pm = pm_ptr(&fcp_pm_ops),
 		.of_match_table = rcar_fcp_of_match,
 		.suppress_bind_attrs = true,
 	},

-- 
2.47.3

[PATCH 08/10] media: vsp1: Support full VSPB on R-Car M3-W, M3-N and E3

[Paul Elder]

The M3-W, M3-N and E3 SoCs integrate a VSPB that reports the same
version ID as the VSPBD in the H3 and H3-N, but includes additional
entities compared to the VSPBD. The VSPBD device entry in the driver
matches on the version ID only, which results in the VSPB being handled
as a VSPBD. The driver therefore doesn't support the CLU, LUT and HGO
entities in the M3-W, M3-N and E3 SoCs.

To fix it, split the device entry in two, one for the VSPBD with an
additional SoC ID match, and one for the VSPB. The VSPBD entry needs to
be listed first, otherwise the VSPB entry will match on H3 and H3-N as
well.

The VI6_IP_VERSION_MODEL_VSPBD_GEN3 macro is renamed to
VI6_IP_VERSION_MODEL_VSPB_GEN3 to indicate that the VSPBD is the special
case.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Paul Elder <paul.elder+renesas@ideasonboard.com>
---
 drivers/media/platform/renesas/vsp1/vsp1_drv.c  | 13 ++++++++++++-
 drivers/media/platform/renesas/vsp1/vsp1_regs.h |  2 +-
 2 files changed, 13 insertions(+), 2 deletions(-)

diff --git a/drivers/media/platform/renesas/vsp1/vsp1_drv.c b/drivers/media/platform/renesas/vsp1/vsp1_drv.c
index 762a9e776a94d50accad070068f92f6dabb81035..5597595414fe787413c7daa5a3142faa9ced8408 100644
--- a/drivers/media/platform/renesas/vsp1/vsp1_drv.c
+++ b/drivers/media/platform/renesas/vsp1/vsp1_drv.c
@@ -781,14 +781,25 @@ static const struct vsp1_device_info vsp1_device_infos[] = {
 		.wpf_count = 1,
 		.uapi = true,
 	}, {
-		.version = VI6_IP_VERSION_MODEL_VSPBD_GEN3,
+		.version = VI6_IP_VERSION_MODEL_VSPB_GEN3,
 		.model = "VSP2-BD",
+		.soc = VI6_IP_VERSION_SOC_H3,
 		.gen = 3,
 		.features = VSP1_HAS_BRU | VSP1_HAS_WPF_VFLIP,
 		.rpf_count = 5,
 		.wpf_count = 1,
 		.num_bru_inputs = 5,
 		.uapi = true,
+	}, {
+		.version = VI6_IP_VERSION_MODEL_VSPB_GEN3,
+		.model = "VSP2-B",
+		.gen = 3,
+		.features = VSP1_HAS_BRU | VSP1_HAS_CLU | VSP1_HAS_HGO
+			  | VSP1_HAS_LUT | VSP1_HAS_WPF_VFLIP,
+		.rpf_count = 5,
+		.wpf_count = 1,
+		.num_bru_inputs = 5,
+		.uapi = true,
 	}, {
 		.version = VI6_IP_VERSION_MODEL_VSPBC_GEN3,
 		.model = "VSP2-BC",
diff --git a/drivers/media/platform/renesas/vsp1/vsp1_regs.h b/drivers/media/platform/renesas/vsp1/vsp1_regs.h
index 10cfbcd1b6e0b3a9c0a8daaa990babfaeb8dde0c..4c0315656e9f81a9656b58fb6f0233f8a22ac0e1 100644
--- a/drivers/media/platform/renesas/vsp1/vsp1_regs.h
+++ b/drivers/media/platform/renesas/vsp1/vsp1_regs.h
@@ -792,7 +792,7 @@
 #define VI6_IP_VERSION_MODEL_VSPS_V2H	(0x12 << 8)
 #define VI6_IP_VERSION_MODEL_VSPD_V2H	(0x13 << 8)
 #define VI6_IP_VERSION_MODEL_VSPI_GEN3	(0x14 << 8)
-#define VI6_IP_VERSION_MODEL_VSPBD_GEN3	(0x15 << 8)
+#define VI6_IP_VERSION_MODEL_VSPB_GEN3	(0x15 << 8)
 #define VI6_IP_VERSION_MODEL_VSPBC_GEN3	(0x16 << 8)
 #define VI6_IP_VERSION_MODEL_VSPD_GEN3	(0x17 << 8)
 #define VI6_IP_VERSION_MODEL_VSPD_V3	(0x18 << 8)

-- 
2.47.3

[PATCH 09/10] media: vsp1: Document X5H SoC ID

[Paul Elder]

The R-Car X5H uses 0x04 as the SoC ID in the version register. Document
is with a macro, as done for other R-Car SoCs.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Paul Elder <paul.elder+renesas@ideasonboard.com>
---
 drivers/media/platform/renesas/vsp1/vsp1_regs.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/media/platform/renesas/vsp1/vsp1_regs.h b/drivers/media/platform/renesas/vsp1/vsp1_regs.h
index 4c0315656e9f81a9656b58fb6f0233f8a22ac0e1..c5066aa17f0139fe7072687325beaa0e04ba260a 100644
--- a/drivers/media/platform/renesas/vsp1/vsp1_regs.h
+++ b/drivers/media/platform/renesas/vsp1/vsp1_regs.h
@@ -814,6 +814,7 @@
 #define VI6_IP_VERSION_SOC_D3		(0x04 << 0)
 #define VI6_IP_VERSION_SOC_M3N		(0x04 << 0)
 #define VI6_IP_VERSION_SOC_E3		(0x04 << 0)
+#define VI6_IP_VERSION_SOC_X5H		(0x04 << 0)
 #define VI6_IP_VERSION_SOC_V3U		(0x05 << 0)
 #define VI6_IP_VERSION_SOC_V4H		(0x06 << 0)
 /* RZ/G2L SoCs have no version register, So use 0x80 for SoC Identification */

-- 
2.47.3

[PATCH 10/10] media: rcar-fcp: Add R-Car X5H support

[Paul Elder]

The FCP instances found in the R-Car X5H v1.0 have a different device
ID. Add it to the devices list.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Paul Elder <paul.elder+renesas@ideasonboard.com>
---
 drivers/media/platform/renesas/rcar-fcp.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/media/platform/renesas/rcar-fcp.c b/drivers/media/platform/renesas/rcar-fcp.c
index 15bcbbda3b853f71780aae876f6440b33addf193..8d62f07d38b7881270e94331b0564e4665664646 100644
--- a/drivers/media/platform/renesas/rcar-fcp.c
+++ b/drivers/media/platform/renesas/rcar-fcp.c
@@ -33,6 +33,7 @@
 #define RCAR_FCP_REG_VCR_REVISION_M3N		(6 << 0)
 #define RCAR_FCP_REG_VCR_REVISION_V3H		(7 << 0)
 #define RCAR_FCP_REG_VCR_REVISION_E3		(8 << 0)
+#define RCAR_FCP_REG_VCR_REVISION_X5H_V1	(12 << 0)
 
 #define RCAR_FCP_REG_CFG0			0x0004
 #define RCAR_FCP_REG_CFG0_FCPVSEL		BIT(1)
@@ -223,6 +224,7 @@ static int rcar_fcp_setup(struct rcar_fcp_device *fcp)
 		{ RCAR_FCP_REG_VCR_CATEGORY | RCAR_FCP_REG_VCR_REVISION_M3N, "M3N" },
 		{ RCAR_FCP_REG_VCR_CATEGORY | RCAR_FCP_REG_VCR_REVISION_V3H, "V3H" },
 		{ RCAR_FCP_REG_VCR_CATEGORY | RCAR_FCP_REG_VCR_REVISION_E3, "E3" },
+		{ RCAR_FCP_REG_VCR_CATEGORY | RCAR_FCP_REG_VCR_REVISION_X5H_V1, "X5H v1.0" },
 	};
 
 	unsigned int i;

-- 
2.47.3

Re: [PATCH 00/10] media: rcar-fcp, vsp1: Enable on R-Car X5H

[Laurent Pinchart]

On Thu, Sep 17, 2026 at 09:04:39PM +0900, Paul Elder wrote:
> This series is based on Geert's
> "topic/rcar-x5h-ironhide-scmi-cpg-mdlc-remapping-v3" branch [0]. A
> branch including this series is available here [1].
> 
> This series enables the FCPV[BI] and the VSP[BI] blocks on the Renesas
> R-Car X5H SoC.
> 
> This has been tested on an Ironhide with the vsp-tests test suite [2]:
> 148 tests: 142 passed, 0 failed, 6 skipped
> 
> There was some odd behavior with the clocks, where from what I
> understood was that the clocks for the FCPV[BI] and VSP[BI] are
> always-on, but the tests would hang unless I explicitly enabled...  the
> always-on clock (or fsleep). Then after I removed the patch that
> explicitly enabled the always-on clock everything ran fine. Just
> reporting that this happened just in case it's relevant.

Well, it's always worrying, but as you can't reproduce it now it's hard
to debug it. Let's keep an eye on that during further VSP work.

> [0] https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git/log/?h=topic/rcar-x5h-ironhide-scmi-cpg-mdlc-remapping-v3
> [1] https://git.ideasonboard.com/epaul/linux/src/branch/epaul/v7.3-rc1/x5h/vsp/fcp
> [2] https://git.ideasonboard.com/renesas/vsp-tests/commit/900168f58c9d96be0592c2593f4d8f34edc9c69e
> 
> Signed-off-by: Paul Elder <paul.elder+renesas@ideasonboard.com>
> ---
> Paul Elder (10):
>       dt-bindings: clock: renesas,r8a78000-cpg: Add CPG_SGD4_VIO_DP_{TX,OTHER}
>       clk: renesas: r8a78000: Add clock for FCPV and VSP for SCP FW SDKv4.36
>       pmdomain: renesas: r8a78000: Add maps for VIO for SCP FW SDKv4.36
>       arm64: renesas: r8a78000: Add FCPV[BI] nodes
>       arm64: renesas: r8a78000: Add VSP[BI] nodes
>       media: rcar-fcp: Check device revision at probe time
>       media: rcar-fcp: Handle resets
>       media: vsp1: Support full VSPB on R-Car M3-W, M3-N and E3
>       media: vsp1: Document X5H SoC ID
>       media: rcar-fcp: Add R-Car X5H support
> 
>  arch/arm64/boot/dts/renesas/r8a78000.dtsi        | 171 +++++++++++++++++++++++
>  drivers/clk/renesas/r8a78000-cpg.c               |   2 +
>  drivers/media/platform/renesas/rcar-fcp.c        | 162 +++++++++++++++++++--
>  drivers/media/platform/renesas/vsp1/vsp1_drv.c   |  13 +-
>  drivers/media/platform/renesas/vsp1/vsp1_regs.h  |   3 +-
>  drivers/pmdomain/renesas/r8a78000-mdlc.c         |  34 ++++-
>  include/dt-bindings/clock/renesas,r8a78000-cpg.h |   2 +
>  7 files changed, 372 insertions(+), 15 deletions(-)
> ---
> base-commit: 02c5d61866607bce0b3271e7c1b838c53dbedc55
> change-id: 20260917-epaul-v7-3-rc1-x5h-vsp-fcp-8afdeb2740f7

-- 
Regards,

Laurent Pinchart

Re: [PATCH 01/10] dt-bindings: clock: renesas,r8a78000-cpg: Add CPG_SGD4_VIO_DP_{TX,OTHER}

[Laurent Pinchart]

Hi Paul,

Thank you for the patch.

On Thu, Sep 17, 2026 at 09:04:40PM +0900, Paul Elder wrote:
> Add preliminary clocks for testing:
> - CPG_SGD4_VIO_DP_TX is used by FCP
> - CPG_SGD4_VIO_DP_OTHER is used by VSP
> 
> Signed-off-by: Paul Elder <paul.elder+renesas@ideasonboard.com>
> ---
>  include/dt-bindings/clock/renesas,r8a78000-cpg.h | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/include/dt-bindings/clock/renesas,r8a78000-cpg.h b/include/dt-bindings/clock/renesas,r8a78000-cpg.h
> index 5851a29847f961b9b4ec270f263eb3aa19e45308..8c1a01e28ddbb26c583d7c9b387400ef6626c06c 100644
> --- a/include/dt-bindings/clock/renesas,r8a78000-cpg.h
> +++ b/include/dt-bindings/clock/renesas,r8a78000-cpg.h
> @@ -12,5 +12,7 @@
>  #define R8A78000_CPG_SGASYNCD16_PERW_BUS	2
>  #define R8A78000_CPG_S0D4_PERE_MAIN		3	// FIXME Preliminary
>  #define R8A78000_CPG_MSOCK_PERW_BUS		4	// FIXME Preliminary
> +#define R8A78000_CPG_SGD4_VIO_DP_TX		5	// FIXME Preliminary
> +#define R8A78000_CPG_SGD4_VIO_DP_OTHER		6	// FIXME Preliminary

While those two clocks are not directly controllable, we need to ensure
that the parents are enabled. That will require taking a closer look at
the SCP firmware. As the X5H CPG driver in upstream is alone a barebone
version at the moment, that doesn't have to be fixed now. This patch is
not an immediate candidate for upstream.

>  
>  #endif /* __DT_BINDINGS_CLOCK_RENESAS_R8A78000_CPG_H__ */
> 

-- 
Regards,

Laurent Pinchart

Re: [PATCH 02/10] clk: renesas: r8a78000: Add clock for FCPV and VSP for SCP FW SDKv4.36

[Laurent Pinchart]

On Thu, Sep 17, 2026 at 09:04:41PM +0900, Paul Elder wrote:
> Add clocks for the FCPV{B,I,D} and VSP{B,I}. They each have one clock
> from an option of two: a 1066MHz and a quarter-divided 266MHz. As we
> already have support for the 266MHz one, add just those for now.
> 
> Signed-off-by: Paul Elder <paul.elder+renesas@ideasonboard.com>
> ---
>  drivers/clk/renesas/r8a78000-cpg.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/drivers/clk/renesas/r8a78000-cpg.c b/drivers/clk/renesas/r8a78000-cpg.c
> index b820d09e1a195068debe8a6eea7a01c534a97b23..17792ff6ab8ae2f7eb5c8f7e3d581b43177e195d 100644
> --- a/drivers/clk/renesas/r8a78000-cpg.c
> +++ b/drivers/clk/renesas/r8a78000-cpg.c
> @@ -326,6 +326,8 @@ static const struct clk_map_in r8a78000_cpg_fw_4_31_0[] = {
>  	{ R8A78000_CPG_SGASYNCD16_PERW_BUS,	FIXED_CLK(66M) },
>  	{ R8A78000_CPG_S0D4_PERE_MAIN,		FIXED_CLK(200M) },
>  	{ R8A78000_CPG_MSOCK_PERW_BUS,		1667 },
> +	{ R8A78000_CPG_SGD4_VIO_DP_TX,		FIXED_CLK(266M)},
> +	{ R8A78000_CPG_SGD4_VIO_DP_OTHER,	FIXED_CLK(266M)},

Same comment as for 01/10. I think the two patches can be squashed
together actually (unless Geert disagrees).

>  	{ -1 }
>  };
>  
> 

-- 
Regards,

Laurent Pinchart

Re: [PATCH 03/10] pmdomain: renesas: r8a78000: Add maps for VIO for SCP FW SDKv4.36

[Laurent Pinchart]

On Thu, Sep 17, 2026 at 09:04:42PM +0900, Paul Elder wrote:
> Add maps for VIO for the VSP and FCP power domains and reset domains.
> 
> Signed-off-by: Paul Elder <paul.elder+renesas@ideasonboard.com>

The driver in upstream is currently a barebone version so this patch can
be merged yet, but it looks good to me. I've successfully tested it on
X5H. We can carry it downstream for the time being.

> ---
>  drivers/pmdomain/renesas/r8a78000-mdlc.c | 34 ++++++++++++++++++++++++++++++--
>  1 file changed, 32 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/pmdomain/renesas/r8a78000-mdlc.c b/drivers/pmdomain/renesas/r8a78000-mdlc.c
> index a0d83f27735e7deacb060e4102e510726b34e62e..c8d34376800982000cfa1b1ae6c279edd749ec9c 100644
> --- a/drivers/pmdomain/renesas/r8a78000-mdlc.c
> +++ b/drivers/pmdomain/renesas/r8a78000-mdlc.c
> @@ -861,6 +861,36 @@ static const struct mdlc_info r8a78000_mdlc_fw_4_28_0[] = {
>  	{ /* sentinel */ }
>  };
>  
> +static const struct power_map_in r8a78000_mdlc_vio_power_fw_4_31_0[] = {
> +	{ 0, 4 },	/* PD_VIO0 */
> +	{ 1, 5 },	/* PD_VIO1 */
> +	{ 2, 6 },	/* PD_VIO2 */
> +	{ 3, 7 },	/* PD_VIO3 */
> +	{ 7, 11 },	/* PD_VIO4 */
> +	{ -1 }
> +};
> +static const struct mod_map_in r8a78000_mdlc_vio_mod_fw_4_31_0[] = {
> +	{ 0xf9, 163 },	/* VSPB0 */
> +	{ 0xfa, 164 },	/* VSPB1 */
> +	{ 0xfb, 165 },	/* VSPB2 */
> +	{ 0xfc, 166 },	/* VSPB3 */
> +	{ 0xfd, 167 },	/* VSPB4 */
> +	{ 0xfe, 168 },	/* VSPI0 */
> +	{ 0xff, 169 },	/* VSPI1 */
> +	{ 0x100, 170 },	/* VSPI2 */
> +	{ 0x101, 171 },	/* VSPI3 */
> +	{ 0x102, 172 },	/* FCPVB0 */
> +	{ 0x103, 173 },	/* FCPVB1 */
> +	{ 0x104, 174 },	/* FCPVB2 */
> +	{ 0x105, 175 },	/* FCPVB3 */
> +	{ 0x106, 176 },	/* FCPVB4 */
> +	{ 0x107, 177 },	/* FCPVI0 */
> +	{ 0x108, 178 },	/* FCPVI1 */
> +	{ 0x109, 179 },	/* FCPVI2 */
> +	{ 0x10a, 180 },	/* FCPVI3 */
> +	{ -1 }
> +};
> +
>  static const struct mod_map_in r8a78000_mdlc_pere_mod_fw_4_31_0[] = {
>  	{ 0x30, 193 },	/* PERE_GPIODM0 */
>  	// No CLOCK_ATTRIBUTES { 0x31, 194 },	/* PERE_GPIODM1 */
> @@ -997,8 +1027,8 @@ static const struct mdlc_info r8a78000_mdlc_fw_4_31_0[] = {
>  		/* FIXME .mod_map = r8a78000_mdlc_vips_mod_fw_4_31_0, */
>  	}, {
>  		.base = 0xc5000000 /* mdlc_vio */,
> -		/* FIXME .power_map = r8a78000_mdlc_vio_power_fw_4_28_0, */
> -		/* FIXME .mod_map = r8a78000_mdlc_vio_mod_fw_4_31_0, */
> +		.power_map = r8a78000_mdlc_vio_power_fw_4_31_0,
> +		.mod_map = r8a78000_mdlc_vio_mod_fw_4_31_0,
>  	}, {
>  		.base = 0xc08f0000 /* mdlc_pere */,
>  		.power_map = r8a78000_mdlc_pere_power_fw_4_28_0,
> 

-- 
Regards,

Laurent Pinchart

Re: [PATCH 04/10] arm64: renesas: r8a78000: Add FCPV[BI] nodes

[Laurent Pinchart]

On Thu, Sep 17, 2026 at 09:04:43PM +0900, Paul Elder wrote:
> Add DT nodes for the FCPVB and FCPVI IP cores in the R-Car X5H Soc.
> 
> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> Signed-off-by: Paul Elder <paul.elder+renesas@ideasonboard.com>
> ---
>  arch/arm64/boot/dts/renesas/r8a78000.dtsi | 72 +++++++++++++++++++++++++++++++
>  1 file changed, 72 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/renesas/r8a78000.dtsi b/arch/arm64/boot/dts/renesas/r8a78000.dtsi
> index 9a07753b221541ed49a975e0c95f2f5d1fdc6ac2..2f8886f8b6545026397fd83969882f8c62afa9d3 100644
> --- a/arch/arm64/boot/dts/renesas/r8a78000.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a78000.dtsi
> @@ -1000,6 +1000,78 @@ mdlc_aon: system-controller@c1338000 {
>  			bootph-all;
>  		};
>  
> +		fcpvi0: fcp@c5030000 {
> +			compatible = "renesas,fcpv";
> +			reg = <0 0xc5030000 0 0x1000>;
> +			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;

Hmmm... Merging this in mainline requires patch 01/10, but we can't
upstream it yet in its current form. Geert, does that mean we can't
upstream DT integration yet at all ?

The patch otherwise looks good to me.

Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Tested-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

> +			power-domains = <&mdlc_vio 0x07 0x107>;
> +			resets = <&mdlc_vio 0x107>;
> +		};
> +
> +		fcpvi1: fcp@c5031000 {
> +			compatible = "renesas,fcpv";
> +			reg = <0 0xc5031000 0 0x1000>;
> +			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
> +			power-domains = <&mdlc_vio 0x07 0x108>;
> +			resets = <&mdlc_vio 0x108>;
> +		};
> +
> +		fcpvi2: fcp@c5032000 {
> +			compatible = "renesas,fcpv";
> +			reg = <0 0xc5032000 0 0x1000>;
> +			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
> +			power-domains = <&mdlc_vio 0x07 0x109>;
> +			resets = <&mdlc_vio 0x109>;
> +		};
> +
> +		fcpvi3: fcp@c5033000 {
> +			compatible = "renesas,fcpv";
> +			reg = <0 0xc5033000 0 0x1000>;
> +			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
> +			power-domains = <&mdlc_vio 0x07 0x10a>;
> +			resets = <&mdlc_vio 0x10a>;
> +		};
> +
> +		fcpvb0: fcp@c5038000 {
> +			compatible = "renesas,fcpv";
> +			reg = <0 0xc5038000 0 0x1000>;
> +			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
> +			power-domains = <&mdlc_vio 0x07 0x102>;
> +			resets = <&mdlc_vio 0x102>;
> +		};
> +
> +		fcpvb1: fcp@c5039000 {
> +			compatible = "renesas,fcpv";
> +			reg = <0 0xc5039000 0 0x1000>;
> +			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
> +			power-domains = <&mdlc_vio 0x07 0x103>;
> +			resets = <&mdlc_vio 0x103>;
> +		};
> +
> +		fcpvb2: fcp@c503a000 {
> +			compatible = "renesas,fcpv";
> +			reg = <0 0xc503a000 0 0x1000>;
> +			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
> +			power-domains = <&mdlc_vio 0x07 0x104>;
> +			resets = <&mdlc_vio 0x104>;
> +		};
> +
> +		fcpvb3: fcp@c503b000 {
> +			compatible = "renesas,fcpv";
> +			reg = <0 0xc503b000 0 0x1000>;
> +			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
> +			power-domains = <&mdlc_vio 0x07 0x105>;
> +			resets = <&mdlc_vio 0x105>;
> +		};
> +
> +		fcpvb4: fcp@c503c000 {
> +			compatible = "renesas,fcpv";
> +			reg = <0 0xc503c000 0 0x1000>;
> +			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_TX>;
> +			power-domains = <&mdlc_vio 0x07 0x106>;
> +			resets = <&mdlc_vio 0x106>;
> +		};
> +
>  		mdlc_cmnn: system-controller@ca410000 {
>  			compatible = "renesas,r8a78000-mdlc";
>  			reg = <0 0xca410000 0 0x1000>;

-- 
Regards,

Laurent Pinchart

Re: [PATCH 05/10] arm64: renesas: r8a78000: Add VSP[BI] nodes

[Laurent Pinchart]

On Thu, Sep 17, 2026 at 09:04:44PM +0900, Paul Elder wrote:
> Add DT nodes for the VSPB and VSPI IP cores in the R-Car X5H Soc.
> 
> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> Signed-off-by: Paul Elder <paul.elder+renesas@ideasonboard.com>
> ---
>  arch/arm64/boot/dts/renesas/r8a78000.dtsi | 99 +++++++++++++++++++++++++++++++
>  1 file changed, 99 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/renesas/r8a78000.dtsi b/arch/arm64/boot/dts/renesas/r8a78000.dtsi
> index 2f8886f8b6545026397fd83969882f8c62afa9d3..f90b869579d384e3fc13d0a13625b7cddaac2868 100644
> --- a/arch/arm64/boot/dts/renesas/r8a78000.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a78000.dtsi
> @@ -1072,6 +1072,105 @@ fcpvb4: fcp@c503c000 {
>  			resets = <&mdlc_vio 0x106>;
>  		};
>  
> +		vspi0: vsp@c5080000 {
> +			compatible = "renesas,vsp2";
> +			reg = <0 0xc5080000 0 0x8000>;
> +			interrupts = <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_OTHER>;

Same comment as for 04/10.

Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Tested-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>

> +			power-domains = <&mdlc_vio 0x07 0xfe>;
> +			resets = <&mdlc_vio 0xfe>;
> +
> +			renesas,fcp = <&fcpvi0>;
> +		};
> +
> +		vspi1: vsp@c5088000 {
> +			compatible = "renesas,vsp2";
> +			reg = <0 0xc5088000 0 0x8000>;
> +			interrupts = <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_OTHER>;
> +			power-domains = <&mdlc_vio 0x07 0xff>;
> +			resets = <&mdlc_vio 0xff>;
> +
> +			renesas,fcp = <&fcpvi1>;
> +		};
> +
> +		vspi2: vsp@c5090000 {
> +			compatible = "renesas,vsp2";
> +			reg = <0 0xc5090000 0 0x8000>;
> +			interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_OTHER>;
> +			power-domains = <&mdlc_vio 0x07 0x100>;
> +			resets = <&mdlc_vio 0x100>;
> +
> +			renesas,fcp = <&fcpvi2>;
> +		};
> +
> +		vspi3: vsp@c5098000 {
> +			compatible = "renesas,vsp2";
> +			reg = <0 0xc5098000 0 0x8000>;
> +			interrupts = <GIC_SPI 646 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_OTHER>;
> +			power-domains = <&mdlc_vio 0x07 0x101>;
> +			resets = <&mdlc_vio 0x101>;
> +
> +			renesas,fcp = <&fcpvi3>;
> +		};
> +
> +		vspb0: vsp@c50c0000 {
> +			compatible = "renesas,vsp2";
> +			reg = <0 0xc50c0000 0 0x8000>;
> +			interrupts = <GIC_SPI 618 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_OTHER>;
> +			power-domains = <&mdlc_vio 0x07 0xf9>;
> +			resets = <&mdlc_vio 0xf9>;
> +
> +			renesas,fcp = <&fcpvb0>;
> +		};
> +
> +		vspb1: vsp@c50c8000 {
> +			compatible = "renesas,vsp2";
> +			reg = <0 0xc50c8000 0 0x8000>;
> +			interrupts = <GIC_SPI 619 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_OTHER>;
> +			power-domains = <&mdlc_vio 0x07 0xfa>;
> +			resets = <&mdlc_vio 0xfa>;
> +
> +			renesas,fcp = <&fcpvb1>;
> +		};
> +
> +		vspb2: vsp@c50d0000 {
> +			compatible = "renesas,vsp2";
> +			reg = <0 0xc50d0000 0 0x8000>;
> +			interrupts = <GIC_SPI 620 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_OTHER>;
> +			power-domains = <&mdlc_vio 0x07 0xfb>;
> +			resets = <&mdlc_vio 0xfb>;
> +
> +			renesas,fcp = <&fcpvb2>;
> +		};
> +
> +		vspb3: vsp@c50d8000 {
> +			compatible = "renesas,vsp2";
> +			reg = <0 0xc50d8000 0 0x8000>;
> +			interrupts = <GIC_SPI 621 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_OTHER>;
> +			power-domains = <&mdlc_vio 0x07 0xfc>;
> +			resets = <&mdlc_vio 0xfc>;
> +
> +			renesas,fcp = <&fcpvb3>;
> +		};
> +
> +		vspb4: vsp@c50e0000 {
> +			compatible = "renesas,vsp2";
> +			reg = <0 0xc50e0000 0 0x8000>;
> +			interrupts = <GIC_SPI 622 IRQ_TYPE_LEVEL_HIGH>;
> +			clocks = <&cpg R8A78000_CPG_SGD4_VIO_DP_OTHER>;
> +			power-domains = <&mdlc_vio 0x07 0xfd>;
> +			resets = <&mdlc_vio 0xfd>;
> +
> +			renesas,fcp = <&fcpvb4>;
> +		};
> +
>  		mdlc_cmnn: system-controller@ca410000 {
>  			compatible = "renesas,r8a78000-mdlc";
>  			reg = <0 0xca410000 0 0x1000>;

-- 
Regards,

Laurent Pinchart

Re: [PATCH 06/10] media: rcar-fcp: Check device revision at probe time

[Laurent Pinchart]

On Thu, Sep 17, 2026 at 09:04:45PM +0900, Paul Elder wrote:

I'm the original author of this patch, please preserve authorship.

> Verify that the device revision register reports a valid value,
> otherwise reject the device.

The code is fine, but I don't think we should merge this now. It will
slow down probe for little value.

> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> Signed-off-by: Paul Elder <paul.elder+renesas@ideasonboard.com>
> ---
> Changes since v2:
> 
> - Add FCP type information
> - Reject devices with an unsupported version
> 
> Changes since v1:
> 
> - Use devm_platform_ioremap_resource()
> ---
>  drivers/media/platform/renesas/rcar-fcp.c | 130 +++++++++++++++++++++++++++---
>  1 file changed, 119 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/media/platform/renesas/rcar-fcp.c b/drivers/media/platform/renesas/rcar-fcp.c
> index dfb0ca93e854dd0bb8aedfb757fd786ef6e45542..d99b3ff976e80f275af19e5dc02c6e1de98c38a3 100644
> --- a/drivers/media/platform/renesas/rcar-fcp.c
> +++ b/drivers/media/platform/renesas/rcar-fcp.c
> @@ -14,26 +14,75 @@
>  #include <linux/list.h>
>  #include <linux/module.h>
>  #include <linux/mutex.h>
> +#include <linux/of_device.h>
>  #include <linux/platform_device.h>
>  #include <linux/pm_runtime.h>
> +#include <linux/property.h>
>  #include <linux/slab.h>
>  
>  #include <media/rcar-fcp.h>
>  
> -#define RCAR_FCP_REG_RST		0x0010
> -#define RCAR_FCP_REG_RST_SOFTRST	BIT(0)
> -#define RCAR_FCP_REG_STA		0x0018
> -#define RCAR_FCP_REG_STA_ACT		BIT(0)
> +#define RCAR_FCP_REG_VCR			0x0000
> +#define RCAR_FCP_REG_VCR_CATEGORY		(1 << 8)
> +#define RCAR_FCP_REG_VCR_REVISION_H3_ES1	(1 << 0)
> +#define RCAR_FCP_REG_VCR_REVISION_M3W		(2 << 0)
> +#define RCAR_FCP_REG_VCR_REVISION_V3M		(3 << 0)
> +#define RCAR_FCP_REG_VCR_REVISION_H3		(4 << 0)
> +#define RCAR_FCP_REG_VCR_REVISION_D3		(5 << 0)
> +#define RCAR_FCP_REG_VCR_REVISION_M3N		(6 << 0)
> +#define RCAR_FCP_REG_VCR_REVISION_V3H		(7 << 0)
> +#define RCAR_FCP_REG_VCR_REVISION_E3		(8 << 0)
> +
> +#define RCAR_FCP_REG_CFG0			0x0004
> +#define RCAR_FCP_REG_CFG0_FCPVSEL		BIT(1)
> +
> +#define RCAR_FCP_REG_RST			0x0010
> +#define RCAR_FCP_REG_RST_RIIFRST		BIT(22)
> +#define RCAR_FCP_REG_RST_RSIFRST		BIT(21)
> +#define RCAR_FCP_REG_RST_DCMPRST		BIT(20)
> +#define RCAR_FCP_REG_RST_MODRST			BIT(4)
> +#define RCAR_FCP_REG_RST_SOFTRST		BIT(0)
> +
> +#define RCAR_FCP_REG_STA			0x0018
> +#define RCAR_FCP_REG_STA_ACT			BIT(0)
> +
> +#define RCAR_FCP_REG_TL_CTRL			0x0070
> +#define RCAR_FCP_REG_TL_CTRL_TLEN		BIT(31)
> +#define RCAR_FCP_REG_TL_CTRL_VPOS_C(n)		((n) << 16)
> +#define RCAR_FCP_REG_TL_CTRL_VPOS_Y(n)		((n) << 0)
> +
> +#define RCAR_FCP_REG_PICINFO1			0x00c4
> +#define RCAR_FCP_REG_PICINFO1_STRIDE_DIV16	((n) << 0)
> +
> +#define RCAR_FCP_REG_BA_ANC_Y0			0x0100
> +#define RCAR_FCP_REG_BA_ANC_Y1			0x0104
> +#define RCAR_FCP_REG_BA_ANC_Y2			0x0108
> +#define RCAR_FCP_REG_BA_ANC_C			0x010c
> +#define RCAR_FCP_REG_BA_REF_Y0			0x0110
> +#define RCAR_FCP_REG_BA_REF_Y1			0x0114
> +#define RCAR_FCP_REG_BA_REF_Y2			0x0118
> +#define RCAR_FCP_REG_BA_REF_C			0x011c
> +
> +enum rcar_fcp_type {
> +	RCAR_FCPF,
> +	RCAR_FCPV,
> +};
>  
>  struct rcar_fcp_device {
>  	struct list_head list;
>  	struct device *dev;
>  	void __iomem *base;
> +	enum rcar_fcp_type type;
>  };
>  
>  static LIST_HEAD(fcp_devices);
>  static DEFINE_MUTEX(fcp_lock);
>  
> +static inline u32 rcar_fcp_read(struct rcar_fcp_device *fcp, u32 reg)
> +{
> +	return ioread32(fcp->base + reg);
> +}
> +
>  static inline void rcar_fcp_write(struct rcar_fcp_device *fcp, u32 reg, u32 val)
>  {
>  	iowrite32(val, fcp->base + reg);
> @@ -152,15 +201,66 @@ EXPORT_SYMBOL_GPL(rcar_fcp_soft_reset);
>   * Platform Driver
>   */
>  
> +static int rcar_fcp_setup(struct rcar_fcp_device *fcp)
> +{
> +	static const char * const models[] = {
> +		[RCAR_FCPF] = "FCPF",
> +		[RCAR_FCPV] = "FCPV",
> +	};
> +	static struct {
> +		u32 version;
> +		const char *name;
> +	} versions[] = {
> +		{ RCAR_FCP_REG_VCR_CATEGORY | RCAR_FCP_REG_VCR_REVISION_H3_ES1, "H3 ES1.x" },
> +		{ RCAR_FCP_REG_VCR_CATEGORY | RCAR_FCP_REG_VCR_REVISION_M3W, "M3W" },
> +		{ RCAR_FCP_REG_VCR_CATEGORY | RCAR_FCP_REG_VCR_REVISION_V3M, "V3M" },
> +		{ RCAR_FCP_REG_VCR_CATEGORY | RCAR_FCP_REG_VCR_REVISION_H3, "H3" },
> +		{ RCAR_FCP_REG_VCR_CATEGORY | RCAR_FCP_REG_VCR_REVISION_D3, "D3" },
> +		{ RCAR_FCP_REG_VCR_CATEGORY | RCAR_FCP_REG_VCR_REVISION_M3N, "M3N" },
> +		{ RCAR_FCP_REG_VCR_CATEGORY | RCAR_FCP_REG_VCR_REVISION_V3H, "V3H" },
> +		{ RCAR_FCP_REG_VCR_CATEGORY | RCAR_FCP_REG_VCR_REVISION_E3, "E3" },
> +	};
> +
> +	unsigned int i;
> +	u32 version;
> +
> +	/* Check the device version register. */
> +	version = rcar_fcp_read(fcp, RCAR_FCP_REG_VCR);
> +
> +	for (i = 0; i < ARRAY_SIZE(versions); ++i) {
> +		if (versions[i].version == version)
> +			break;
> +	}
> +
> +	if (i >= ARRAY_SIZE(versions)) {
> +		dev_err(fcp->dev, "Invalid FCP version 0x%08x\n", version);
> +		return -ENODEV;
> +	}
> +
> +	dev_dbg(fcp->dev, "%s %s device found\n", models[fcp->type],
> +		versions[i].name);
> +
> +	return 0;
> +}
> +
> +static const struct of_device_id rcar_fcp_of_match[] = {
> +	{ .compatible = "renesas,fcpf", .data = (void *)RCAR_FCPF },
> +	{ .compatible = "renesas,fcpv", .data = (void *)RCAR_FCPV },
> +	{ },
> +};
> +MODULE_DEVICE_TABLE(of, rcar_fcp_of_match);
> +
>  static int rcar_fcp_probe(struct platform_device *pdev)
>  {
>  	struct rcar_fcp_device *fcp;
> +	int ret;
>  
>  	fcp = devm_kzalloc(&pdev->dev, sizeof(*fcp), GFP_KERNEL);
>  	if (fcp == NULL)
>  		return -ENOMEM;
>  
>  	fcp->dev = &pdev->dev;
> +	fcp->type = (enum rcar_fcp_type)device_get_match_data(&pdev->dev);
>  
>  	fcp->base = devm_platform_ioremap_resource(pdev, 0);
>  	if (IS_ERR(fcp->base))
> @@ -169,6 +269,15 @@ static int rcar_fcp_probe(struct platform_device *pdev)
>  	dma_set_max_seg_size(fcp->dev, UINT_MAX);
>  
>  	pm_runtime_enable(&pdev->dev);
> +	ret = pm_runtime_resume_and_get(&pdev->dev);
> +	if (ret < 0)
> +		goto error_pm_disable;
> +
> +	ret = rcar_fcp_setup(fcp);
> +	if (ret < 0)
> +		goto error_pm_put;
> +
> +	pm_runtime_put(&pdev->dev);
>  
>  	mutex_lock(&fcp_lock);
>  	list_add_tail(&fcp->list, &fcp_devices);
> @@ -177,6 +286,12 @@ static int rcar_fcp_probe(struct platform_device *pdev)
>  	platform_set_drvdata(pdev, fcp);
>  
>  	return 0;
> +
> +error_pm_put:
> +	pm_runtime_put(&pdev->dev);
> +error_pm_disable:
> +	pm_runtime_disable(&pdev->dev);
> +	return ret;
>  }
>  
>  static void rcar_fcp_remove(struct platform_device *pdev)
> @@ -190,13 +305,6 @@ static void rcar_fcp_remove(struct platform_device *pdev)
>  	pm_runtime_disable(&pdev->dev);
>  }
>  
> -static const struct of_device_id rcar_fcp_of_match[] = {
> -	{ .compatible = "renesas,fcpf" },
> -	{ .compatible = "renesas,fcpv" },
> -	{ },
> -};
> -MODULE_DEVICE_TABLE(of, rcar_fcp_of_match);
> -
>  static struct platform_driver rcar_fcp_platform_driver = {
>  	.probe		= rcar_fcp_probe,
>  	.remove		= rcar_fcp_remove,
> 

-- 
Regards,

Laurent Pinchart

Re: [PATCH 07/10] media: rcar-fcp: Handle resets

[Laurent Pinchart]

On Thu, Sep 17, 2026 at 09:04:46PM +0900, Paul Elder wrote:
> On some versions of the FCP, such as the one on the X5H, reset control
> is required to operate the FCP. Add support for handling resets
> optionally, to continue supporting versions that do not require it.
> 
> Signed-off-by: Paul Elder <paul.elder+renesas@ideasonboard.com>
> ---
>  drivers/media/platform/renesas/rcar-fcp.c | 34 +++++++++++++++++++++++++++++--
>  1 file changed, 32 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/media/platform/renesas/rcar-fcp.c b/drivers/media/platform/renesas/rcar-fcp.c
> index d99b3ff976e80f275af19e5dc02c6e1de98c38a3..15bcbbda3b853f71780aae876f6440b33addf193 100644
> --- a/drivers/media/platform/renesas/rcar-fcp.c
> +++ b/drivers/media/platform/renesas/rcar-fcp.c
> @@ -18,6 +18,7 @@
>  #include <linux/platform_device.h>
>  #include <linux/pm_runtime.h>
>  #include <linux/property.h>
> +#include <linux/reset.h>
>  #include <linux/slab.h>
>  
>  #include <media/rcar-fcp.h>
> @@ -63,6 +64,8 @@
>  #define RCAR_FCP_REG_BA_REF_Y2			0x0118
>  #define RCAR_FCP_REG_BA_REF_C			0x011c
>  
> +struct reset_control;
> +

Not needed, you include linux/reset.h.

>  enum rcar_fcp_type {
>  	RCAR_FCPF,
>  	RCAR_FCPV,
> @@ -73,6 +76,7 @@ struct rcar_fcp_device {
>  	struct device *dev;
>  	void __iomem *base;
>  	enum rcar_fcp_type type;
> +	struct reset_control *rstc;
>  };
>  
>  static LIST_HEAD(fcp_devices);
> @@ -262,12 +266,19 @@ static int rcar_fcp_probe(struct platform_device *pdev)
>  	fcp->dev = &pdev->dev;
>  	fcp->type = (enum rcar_fcp_type)device_get_match_data(&pdev->dev);
>  
> +	platform_set_drvdata(pdev, fcp);
> +
>  	fcp->base = devm_platform_ioremap_resource(pdev, 0);
>  	if (IS_ERR(fcp->base))
>  		return PTR_ERR(fcp->base);
>  
>  	dma_set_max_seg_size(fcp->dev, UINT_MAX);
>  
> +	fcp->rstc = devm_reset_control_get_optional(&pdev->dev, NULL);
> +	if (IS_ERR(fcp->rstc))
> +		return dev_err_probe(&pdev->dev, PTR_ERR(fcp->rstc),
> +				     "failed to get reset control\n");
> +
>  	pm_runtime_enable(&pdev->dev);
>  	ret = pm_runtime_resume_and_get(&pdev->dev);
>  	if (ret < 0)
> @@ -283,8 +294,6 @@ static int rcar_fcp_probe(struct platform_device *pdev)
>  	list_add_tail(&fcp->list, &fcp_devices);
>  	mutex_unlock(&fcp_lock);
>  
> -	platform_set_drvdata(pdev, fcp);
> -
>  	return 0;
>  
>  error_pm_put:
> @@ -305,11 +314,32 @@ static void rcar_fcp_remove(struct platform_device *pdev)
>  	pm_runtime_disable(&pdev->dev);
>  }
>  
> +static int fcp_pm_runtime_suspend(struct device *dev)
> +{
> +	struct rcar_fcp_device *fcp = dev_get_drvdata(dev);
> +
> +	reset_control_assert(fcp->rstc);

No need for error checking ?

> +	return 0;
> +}
> +
> +static int fcp_pm_runtime_resume(struct device *dev)
> +{
> +	struct rcar_fcp_device *fcp = dev_get_drvdata(dev);
> +
> +	reset_control_deassert(fcp->rstc);

Same here.

Otherwise this looks good, but please move it before patch 06/10 as I
would like to upstream this without 06/10.

> +	return 0;
> +}
> +
> +static const struct dev_pm_ops fcp_pm_ops = {
> +	RUNTIME_PM_OPS(fcp_pm_runtime_suspend, fcp_pm_runtime_resume, NULL)
> +};
> +
>  static struct platform_driver rcar_fcp_platform_driver = {
>  	.probe		= rcar_fcp_probe,
>  	.remove		= rcar_fcp_remove,
>  	.driver		= {
>  		.name	= "rcar-fcp",
> +		.pm = pm_ptr(&fcp_pm_ops),
>  		.of_match_table = rcar_fcp_of_match,
>  		.suppress_bind_attrs = true,
>  	},
> 

-- 
Regards,

Laurent Pinchart

Re: [PATCH 08/10] media: vsp1: Support full VSPB on R-Car M3-W, M3-N and E3

[Laurent Pinchart]

Hi Paul,

Thank you for the patch.

On Thu, Sep 17, 2026 at 09:04:47PM +0900, Paul Elder wrote:

Please preserve authorship of patches.

> The M3-W, M3-N and E3 SoCs integrate a VSPB that reports the same
> version ID as the VSPBD in the H3 and H3-N, but includes additional
> entities compared to the VSPBD. The VSPBD device entry in the driver
> matches on the version ID only, which results in the VSPB being handled
> as a VSPBD. The driver therefore doesn't support the CLU, LUT and HGO
> entities in the M3-W, M3-N and E3 SoCs.
> 
> To fix it, split the device entry in two, one for the VSPBD with an
> additional SoC ID match, and one for the VSPB. The VSPBD entry needs to
> be listed first, otherwise the VSPB entry will match on H3 and H3-N as
> well.
> 
> The VI6_IP_VERSION_MODEL_VSPBD_GEN3 macro is renamed to
> VI6_IP_VERSION_MODEL_VSPB_GEN3 to indicate that the VSPBD is the special
> case.
> 
> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> Signed-off-by: Paul Elder <paul.elder+renesas@ideasonboard.com>
> ---
>  drivers/media/platform/renesas/vsp1/vsp1_drv.c  | 13 ++++++++++++-
>  drivers/media/platform/renesas/vsp1/vsp1_regs.h |  2 +-
>  2 files changed, 13 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/media/platform/renesas/vsp1/vsp1_drv.c b/drivers/media/platform/renesas/vsp1/vsp1_drv.c
> index 762a9e776a94d50accad070068f92f6dabb81035..5597595414fe787413c7daa5a3142faa9ced8408 100644
> --- a/drivers/media/platform/renesas/vsp1/vsp1_drv.c
> +++ b/drivers/media/platform/renesas/vsp1/vsp1_drv.c
> @@ -781,14 +781,25 @@ static const struct vsp1_device_info vsp1_device_infos[] = {
>  		.wpf_count = 1,
>  		.uapi = true,
>  	}, {
> -		.version = VI6_IP_VERSION_MODEL_VSPBD_GEN3,
> +		.version = VI6_IP_VERSION_MODEL_VSPB_GEN3,
>  		.model = "VSP2-BD",
> +		.soc = VI6_IP_VERSION_SOC_H3,
>  		.gen = 3,
>  		.features = VSP1_HAS_BRU | VSP1_HAS_WPF_VFLIP,
>  		.rpf_count = 5,
>  		.wpf_count = 1,
>  		.num_bru_inputs = 5,
>  		.uapi = true,
> +	}, {
> +		.version = VI6_IP_VERSION_MODEL_VSPB_GEN3,
> +		.model = "VSP2-B",
> +		.gen = 3,
> +		.features = VSP1_HAS_BRU | VSP1_HAS_CLU | VSP1_HAS_HGO
> +			  | VSP1_HAS_LUT | VSP1_HAS_WPF_VFLIP,
> +		.rpf_count = 5,
> +		.wpf_count = 1,
> +		.num_bru_inputs = 5,
> +		.uapi = true,
>  	}, {
>  		.version = VI6_IP_VERSION_MODEL_VSPBC_GEN3,
>  		.model = "VSP2-BC",
> diff --git a/drivers/media/platform/renesas/vsp1/vsp1_regs.h b/drivers/media/platform/renesas/vsp1/vsp1_regs.h
> index 10cfbcd1b6e0b3a9c0a8daaa990babfaeb8dde0c..4c0315656e9f81a9656b58fb6f0233f8a22ac0e1 100644
> --- a/drivers/media/platform/renesas/vsp1/vsp1_regs.h
> +++ b/drivers/media/platform/renesas/vsp1/vsp1_regs.h
> @@ -792,7 +792,7 @@
>  #define VI6_IP_VERSION_MODEL_VSPS_V2H	(0x12 << 8)
>  #define VI6_IP_VERSION_MODEL_VSPD_V2H	(0x13 << 8)
>  #define VI6_IP_VERSION_MODEL_VSPI_GEN3	(0x14 << 8)
> -#define VI6_IP_VERSION_MODEL_VSPBD_GEN3	(0x15 << 8)
> +#define VI6_IP_VERSION_MODEL_VSPB_GEN3	(0x15 << 8)
>  #define VI6_IP_VERSION_MODEL_VSPBC_GEN3	(0x16 << 8)
>  #define VI6_IP_VERSION_MODEL_VSPD_GEN3	(0x17 << 8)
>  #define VI6_IP_VERSION_MODEL_VSPD_V3	(0x18 << 8)

-- 
Regards,

Laurent Pinchart

Re: [PATCH 09/10] media: vsp1: Document X5H SoC ID

[Laurent Pinchart]

On Thu, Sep 17, 2026 at 09:04:48PM +0900, Paul Elder wrote:
> The R-Car X5H uses 0x04 as the SoC ID in the version register. Document
> is with a macro, as done for other R-Car SoCs.
> 
> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> Signed-off-by: Paul Elder <paul.elder+renesas@ideasonboard.com>
> ---
>  drivers/media/platform/renesas/vsp1/vsp1_regs.h | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/media/platform/renesas/vsp1/vsp1_regs.h b/drivers/media/platform/renesas/vsp1/vsp1_regs.h
> index 4c0315656e9f81a9656b58fb6f0233f8a22ac0e1..c5066aa17f0139fe7072687325beaa0e04ba260a 100644
> --- a/drivers/media/platform/renesas/vsp1/vsp1_regs.h
> +++ b/drivers/media/platform/renesas/vsp1/vsp1_regs.h
> @@ -814,6 +814,7 @@
>  #define VI6_IP_VERSION_SOC_D3		(0x04 << 0)
>  #define VI6_IP_VERSION_SOC_M3N		(0x04 << 0)
>  #define VI6_IP_VERSION_SOC_E3		(0x04 << 0)
> +#define VI6_IP_VERSION_SOC_X5H		(0x04 << 0)

I don't think this is correct. You will find the right value when
enabling the VSPD.

>  #define VI6_IP_VERSION_SOC_V3U		(0x05 << 0)
>  #define VI6_IP_VERSION_SOC_V4H		(0x06 << 0)
>  /* RZ/G2L SoCs have no version register, So use 0x80 for SoC Identification */

-- 
Regards,

Laurent Pinchart

Re: [PATCH 10/10] media: rcar-fcp: Add R-Car X5H support

[Laurent Pinchart]

On Thu, Sep 17, 2026 at 09:04:49PM +0900, Paul Elder wrote:

Same comment about authorship.

> The FCP instances found in the R-Car X5H v1.0 have a different device
> ID. Add it to the devices list.
> 
> Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
> Signed-off-by: Paul Elder <paul.elder+renesas@ideasonboard.com>
> ---
>  drivers/media/platform/renesas/rcar-fcp.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/drivers/media/platform/renesas/rcar-fcp.c b/drivers/media/platform/renesas/rcar-fcp.c
> index 15bcbbda3b853f71780aae876f6440b33addf193..8d62f07d38b7881270e94331b0564e4665664646 100644
> --- a/drivers/media/platform/renesas/rcar-fcp.c
> +++ b/drivers/media/platform/renesas/rcar-fcp.c
> @@ -33,6 +33,7 @@
>  #define RCAR_FCP_REG_VCR_REVISION_M3N		(6 << 0)
>  #define RCAR_FCP_REG_VCR_REVISION_V3H		(7 << 0)
>  #define RCAR_FCP_REG_VCR_REVISION_E3		(8 << 0)
> +#define RCAR_FCP_REG_VCR_REVISION_X5H_V1	(12 << 0)
>  
>  #define RCAR_FCP_REG_CFG0			0x0004
>  #define RCAR_FCP_REG_CFG0_FCPVSEL		BIT(1)
> @@ -223,6 +224,7 @@ static int rcar_fcp_setup(struct rcar_fcp_device *fcp)
>  		{ RCAR_FCP_REG_VCR_CATEGORY | RCAR_FCP_REG_VCR_REVISION_M3N, "M3N" },
>  		{ RCAR_FCP_REG_VCR_CATEGORY | RCAR_FCP_REG_VCR_REVISION_V3H, "V3H" },
>  		{ RCAR_FCP_REG_VCR_CATEGORY | RCAR_FCP_REG_VCR_REVISION_E3, "E3" },
> +		{ RCAR_FCP_REG_VCR_CATEGORY | RCAR_FCP_REG_VCR_REVISION_X5H_V1, "X5H v1.0" },
>  	};
>  
>  	unsigned int i;

-- 
Regards,

Laurent Pinchart

Re: [PATCH 00/10] media: rcar-fcp, vsp1: Enable on R-Car X5H

[Laurent Pinchart]

On Thu, Sep 17, 2026 at 09:04:39PM +0900, Paul Elder wrote:
> This series is based on Geert's
> "topic/rcar-x5h-ironhide-scmi-cpg-mdlc-remapping-v3" branch [0]. A
> branch including this series is available here [1].

The series contains a mix of patches ready for upstream and patches that
are not. The cover letter should explain this better to avoid wasting
reviewers' time. Please organize the patches better in v2, mark the ones
not ready for uptreaming with '[DNI]' or a similar prefix, and explain
the rationale in the cover letter.

> This series enables the FCPV[BI] and the VSP[BI] blocks on the Renesas
> R-Car X5H SoC.
> 
> This has been tested on an Ironhide with the vsp-tests test suite [2]:
> 148 tests: 142 passed, 0 failed, 6 skipped
> 
> There was some odd behavior with the clocks, where from what I
> understood was that the clocks for the FCPV[BI] and VSP[BI] are
> always-on, but the tests would hang unless I explicitly enabled...  the
> always-on clock (or fsleep). Then after I removed the patch that
> explicitly enabled the always-on clock everything ran fine. Just
> reporting that this happened just in case it's relevant.
> 
> [0] https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git/log/?h=topic/rcar-x5h-ironhide-scmi-cpg-mdlc-remapping-v3
> [1] https://git.ideasonboard.com/epaul/linux/src/branch/epaul/v7.3-rc1/x5h/vsp/fcp
> [2] https://git.ideasonboard.com/renesas/vsp-tests/commit/900168f58c9d96be0592c2593f4d8f34edc9c69e
> 
> Signed-off-by: Paul Elder <paul.elder+renesas@ideasonboard.com>
> ---
> Paul Elder (10):
>       dt-bindings: clock: renesas,r8a78000-cpg: Add CPG_SGD4_VIO_DP_{TX,OTHER}
>       clk: renesas: r8a78000: Add clock for FCPV and VSP for SCP FW SDKv4.36
>       pmdomain: renesas: r8a78000: Add maps for VIO for SCP FW SDKv4.36
>       arm64: renesas: r8a78000: Add FCPV[BI] nodes
>       arm64: renesas: r8a78000: Add VSP[BI] nodes
>       media: rcar-fcp: Check device revision at probe time
>       media: rcar-fcp: Handle resets
>       media: vsp1: Support full VSPB on R-Car M3-W, M3-N and E3
>       media: vsp1: Document X5H SoC ID
>       media: rcar-fcp: Add R-Car X5H support
> 
>  arch/arm64/boot/dts/renesas/r8a78000.dtsi        | 171 +++++++++++++++++++++++
>  drivers/clk/renesas/r8a78000-cpg.c               |   2 +
>  drivers/media/platform/renesas/rcar-fcp.c        | 162 +++++++++++++++++++--
>  drivers/media/platform/renesas/vsp1/vsp1_drv.c   |  13 +-
>  drivers/media/platform/renesas/vsp1/vsp1_regs.h  |   3 +-
>  drivers/pmdomain/renesas/r8a78000-mdlc.c         |  34 ++++-
>  include/dt-bindings/clock/renesas,r8a78000-cpg.h |   2 +
>  7 files changed, 372 insertions(+), 15 deletions(-)
> ---
> base-commit: 02c5d61866607bce0b3271e7c1b838c53dbedc55
> change-id: 20260917-epaul-v7-3-rc1-x5h-vsp-fcp-8afdeb2740f7

-- 
Regards,

Laurent Pinchart