[PATCH Intenal 0/2] EDAC/amd64: Add Family 1Ah Model 80h-8Fh support and fix csrow decode

[PATCH Intenal 0/2] EDAC/amd64: Add Family 1Ah Model 80h-8Fh support and fix csrow decode

[Vishal Badole]

This series adds AMD Family 1Ah Model 80h-8Fh support to the amd64_edac
driver and fixes a UMC csrow decode issue seen on that part.

Patch 1 adds support for Family 1Ah Model 80h-8Fh.

Patch 2 fixes the chip select decode for DRAM ECC errors. The syndrome
field was masked assuming eight chip selects while the controller
implements four, producing an out-of-range csrow and an error reported
against "unknown memory". Mask with the number of chip selects the
controller actually implements.

Tested on a Family 1Ah Model 88h board with injected ECC errors.

Vishal Badole (2):
  EDAC/amd64: Add support for AMD family 1Ah models 80h-8Fh
  EDAC/amd64: Limit UMC csrow decode to the implemented chip selects

 drivers/edac/amd64_edac.c | 17 +++++++++++------
 drivers/edac/amd64_edac.h |  2 +-
 2 files changed, 12 insertions(+), 7 deletions(-)

-- 
2.34.1

[PATCH Intenal 1/2] EDAC/amd64: Add support for AMD family 1Ah models 80h-8Fh

[Vishal Badole]

Add support for family 1Ah-based models 80h-8Fh.

Signed-off-by: Vishal Badole <Vishal.Badole@amd.com>
---
 drivers/edac/amd64_edac.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
index c6aa69dbd9fb..ff0ebc8e15f6 100644
--- a/drivers/edac/amd64_edac.c
+++ b/drivers/edac/amd64_edac.c
@@ -3900,6 +3900,10 @@ static int per_family_init(struct amd64_pvt *pvt)
 			pvt->max_mcs            = 16;
 			pvt->flags.zn_regs_v2   = 1;
 			break;
+		case 0x80 ... 0x8f:
+			pvt->max_mcs            = 2;
+			pvt->flags.zn_regs_v2   = 1;
+			break;
 		case 0x90 ... 0x9f:
 		case 0xa0 ... 0xaf:
 			pvt->max_mcs            = 8;
-- 
2.34.1

Re: [PATCH Intenal 1/2] EDAC/amd64: Add support for AMD family 1Ah models 80h-8Fh

[Yazen Ghannam]

On Wed, Sep 23, 2026 at 04:50:02PM +0530, Vishal Badole wrote:
> Add support for family 1Ah-based models 80h-8Fh.
> 
> Signed-off-by: Vishal Badole <Vishal.Badole@amd.com>
> ---
>  drivers/edac/amd64_edac.c | 4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
> index c6aa69dbd9fb..ff0ebc8e15f6 100644
> --- a/drivers/edac/amd64_edac.c
> +++ b/drivers/edac/amd64_edac.c
> @@ -3900,6 +3900,10 @@ static int per_family_init(struct amd64_pvt *pvt)
>  			pvt->max_mcs            = 16;
>  			pvt->flags.zn_regs_v2   = 1;
>  			break;
> +		case 0x80 ... 0x8f:
> +			pvt->max_mcs            = 2;

Should this be '4'?

In documentation, I see 4 UMC MCA banks, and the UMC register
definitions list UMC0-UMC3 instances.

Thanks,
Yazen

[PATCH Intenal 2/2] EDAC/amd64: Limit UMC csrow decode to the implemented chip selects

[Vishal Badole]

For DRAM ECC errors on SMCA systems, the Chip Select which reported the
error is encoded in the MCA_SYND[ErrorInformation] field. The EDAC core
uses that value to index into the csrow array which was sized during
probe from pvt->csels[].b_cnt.

On Family 1Ah Model 88h a corrected DRAM error results in:

  EDAC MC0: INTERNAL ERROR: csrow value is out of range (5 >= 4)
  WARNING: drivers/edac/edac_mc.c:919 at edac_raw_mc_handle_error

and the error is subsequently reported against "unknown memory", so the
DIMM which actually reported the error cannot be identified.

This happens because the syndrome field is masked with a hardcoded 0x7,
i.e. eight possible chip selects, while umc_prep_chip_selects() sizes
every UMC channel for four. Bit 2 of that field is therefore not a valid
Chip Select bit, and whenever hardware leaves it set the decoded value
exceeds the number of csrows the EDAC core knows about.

Mask with the number of chip selects the controller actually implements
so the decoded value can never exceed what was allocated, instead of
relying on an assumption about the field width that no longer holds.

Signed-off-by: Vishal Badole <Vishal.Badole@amd.com>
---
 drivers/edac/amd64_edac.c | 13 +++++++------
 drivers/edac/amd64_edac.h |  2 +-
 2 files changed, 8 insertions(+), 7 deletions(-)

diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
index ff0ebc8e15f6..f6f9b8e63234 100644
--- a/drivers/edac/amd64_edac.c
+++ b/drivers/edac/amd64_edac.c
@@ -2796,13 +2796,14 @@ static inline void decode_bus_error(int node_id, struct mce *m)
  * the instance_id. For example, instance_id=0xYXXXXX where Y is the channel
  * number.
  *
- * For DRAM ECC errors, the Chip Select number is given in bits [2:0] of
- * the MCA_SYND[ErrorInformation] field.
+ * For DRAM ECC errors, the Chip Select number is given in the low bits of
+ * the MCA_SYND[ErrorInformation] field. Only as many bits as the UMC has
+ * implemented chip selects are valid there.
  */
-static void umc_get_err_info(struct mce *m, struct err_info *err)
+static void umc_get_err_info(struct amd64_pvt *pvt, struct mce *m, struct err_info *err)
 {
 	err->channel = (m->ipid & GENMASK(31, 0)) >> 20;
-	err->csrow = m->synd & 0x7;
+	err->csrow = m->synd & (pvt->csels[0].b_cnt - 1);
 }
 
 static void decode_umc_error(int node_id, struct mce *m)
@@ -2841,7 +2842,7 @@ static void decode_umc_error(int node_id, struct mce *m)
 			err.err_code = ERR_CHANNEL;
 	}
 
-	pvt->ops->get_err_info(m, &err);
+	pvt->ops->get_err_info(pvt, m, &err);
 
 	a_err.addr = m->addr;
 	a_err.ipid = m->ipid;
@@ -3514,7 +3515,7 @@ static int umc_hw_info_get(struct amd64_pvt *pvt)
  * UMC1 CH[3:0] = 0x0025[3:0]000
  * UMC1 CH[7:4] = 0x0035[3:0]000
  */
-static void gpu_get_err_info(struct mce *m, struct err_info *err)
+static void gpu_get_err_info(struct amd64_pvt *pvt, struct mce *m, struct err_info *err)
 {
 	u8 ch = (m->ipid & GENMASK(31, 0)) >> 20;
 	u8 phy = ((m->ipid >> 12) & 0xf);
diff --git a/drivers/edac/amd64_edac.h b/drivers/edac/amd64_edac.h
index 1757c1b99fc8..9a8b7e296087 100644
--- a/drivers/edac/amd64_edac.h
+++ b/drivers/edac/amd64_edac.h
@@ -467,7 +467,7 @@ struct low_ops {
 	bool (*ecc_enabled)(struct amd64_pvt *pvt);
 	void (*setup_mci_misc_attrs)(struct mem_ctl_info *mci);
 	void (*dump_misc_regs)(struct amd64_pvt *pvt);
-	void (*get_err_info)(struct mce *m, struct err_info *err);
+	void (*get_err_info)(struct amd64_pvt *pvt, struct mce *m, struct err_info *err);
 };
 
 int __amd64_read_pci_cfg_dword(struct pci_dev *pdev, int offset,
-- 
2.34.1

Re: [PATCH Intenal 2/2] EDAC/amd64: Limit UMC csrow decode to the implemented chip selects

[Yazen Ghannam]

On Wed, Sep 23, 2026 at 04:50:03PM +0530, Vishal Badole wrote:
> For DRAM ECC errors on SMCA systems, the Chip Select which reported the
> error is encoded in the MCA_SYND[ErrorInformation] field. The EDAC core
> uses that value to index into the csrow array which was sized during
> probe from pvt->csels[].b_cnt.
> 
> On Family 1Ah Model 88h a corrected DRAM error results in:
> 
>   EDAC MC0: INTERNAL ERROR: csrow value is out of range (5 >= 4)
>   WARNING: drivers/edac/edac_mc.c:919 at edac_raw_mc_handle_error
> 
> and the error is subsequently reported against "unknown memory", so the
> DIMM which actually reported the error cannot be identified.
> 
> This happens because the syndrome field is masked with a hardcoded 0x7,
> i.e. eight possible chip selects, while umc_prep_chip_selects() sizes
> every UMC channel for four. Bit 2 of that field is therefore not a valid
> Chip Select bit, and whenever hardware leaves it set the decoded value
> exceeds the number of csrows the EDAC core knows about.

This isn't an accurate description of the issue.

For this model, the hardcoded 0x7 mask is correct. The register
definition shows "MCA_SYND_UMC[2:0] = Chip Select" for this error code.

The issue is that some forms of error 'injection' populate the registers
with hardcoded values that don't necessarily reflect the hardware.

> 
> Mask with the number of chip selects the controller actually implements
> so the decoded value can never exceed what was allocated, instead of
> relying on an assumption about the field width that no longer holds.
> 

In practice, the simpler solution is to change the mask to 0x3.
Documentation for newer products show "MCA_SYND_UMC[1:0] = Chip Select".
And older products only ever had 4 chip selects as you point out.

Thanks,
Yazen