[PATCH v2 0/6] Add StarFive JHB100 PECI support

[PATCH v2 0/6] Add StarFive JHB100 PECI support

[Changhuang Liang]

Add PECI controller driver for StarFive JHB100 SoC. The driver
supports PECI protocol communication for CPU thermal management.

This series has been tested on the JHB100 EVB1 board.

Changes since v1:

PATCH 1:
- Add Conor's "Reviewed-by" tag.

PATCH 2:
- Remove PECI write command support.

PATCH 3:
- Update the 0x83 completion code definition to PECI_CC_RESP_IN_PROGRESS

PATCH 5:
- Update commit message
- Set GNR's minimum PECI revision to 0x42

PATCH6:
- Update commit message
- Set GNR's minimum PECI revision to 0x42
- Remove the redundant !priv->gen_info->read_thresholds check in update_thresholds()

v1: https://lore.kernel.org/all/20260903133408.110847-1-changhuang.liang@starfivetech.com/

Changhuang Liang (6):
  dt-bindings: peci: Add StarFive JHB100 PECI controller
  peci: controller: Add StarFive JHB100 PECI driver
  peci: Add support for PECI CC 0x83 retry condition
  peci: cpu: Add Intel Granite Rapids support
  hwmon: (peci/cputemp) Add support for Granite Rapids (GNR)
  hwmon: (peci/dimmtemp) Add support for Granite Rapids (GNR)

 .../bindings/peci/starfive,jhb100-peci.yaml   |  57 +++
 MAINTAINERS                                   |   8 +
 drivers/hwmon/peci/cputemp.c                  |  21 +
 drivers/hwmon/peci/dimmtemp.c                 |  33 +-
 drivers/peci/controller/Kconfig               |  17 +
 drivers/peci/controller/Makefile              |   1 +
 drivers/peci/controller/peci-starfive.c       | 376 ++++++++++++++++++
 drivers/peci/cpu.c                            |   4 +
 drivers/peci/request.c                        |   2 +
 9 files changed, 515 insertions(+), 4 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/peci/starfive,jhb100-peci.yaml
 create mode 100644 drivers/peci/controller/peci-starfive.c

--
2.25.1

[PATCH v2 1/6] dt-bindings: peci: Add StarFive JHB100 PECI controller

[Changhuang Liang]

Add device tree bindings for the Platform Environment Control Interface
(PECI) controller found on StarFive JHB100 SoC.

Co-developed-by: Mason Huo <mason.huo@starfivetech.com>
Signed-off-by: Mason Huo <mason.huo@starfivetech.com>
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
---
 .../bindings/peci/starfive,jhb100-peci.yaml   | 57 +++++++++++++++++++
 1 file changed, 57 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/peci/starfive,jhb100-peci.yaml

diff --git a/Documentation/devicetree/bindings/peci/starfive,jhb100-peci.yaml b/Documentation/devicetree/bindings/peci/starfive,jhb100-peci.yaml
new file mode 100644
index 000000000000..761eb9aa4adf
--- /dev/null
+++ b/Documentation/devicetree/bindings/peci/starfive,jhb100-peci.yaml
@@ -0,0 +1,57 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/peci/starfive,jhb100-peci.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive JHB100 PECI Controller
+
+maintainers:
+  - Changhuang Liang <changhuang.liang@starfivetech.com>
+  - Mason Huo <mason.huo@starfivetech.com>
+
+allOf:
+  - $ref: peci-controller.yaml#
+
+properties:
+  compatible:
+    enum:
+      - starfive,jhb100-peci
+
+  reg:
+    maxItems: 1
+
+  interrupts:
+    maxItems: 1
+
+  clocks:
+    maxItems: 1
+
+  resets:
+    maxItems: 1
+
+  cmd-timeout-ms:
+    minimum: 1
+    maximum: 1000
+    default: 1000
+
+required:
+  - compatible
+  - reg
+  - interrupts
+  - clocks
+  - resets
+
+additionalProperties: false
+
+examples:
+  - |
+    peci-controller@11c60000 {
+      compatible = "starfive,jhb100-peci";
+      reg = <0x11c60000 0x400>;
+      interrupts = <222>;
+      clocks = <&per3crg 34>;
+      resets = <&per3crg 3>;
+      cmd-timeout-ms = <1000>;
+    };
+...
-- 
2.25.1

[PATCH v2 2/6] peci: controller: Add StarFive JHB100 PECI driver

[Changhuang Liang]

Add PECI controller driver for StarFive JHB100 SoC. The driver supports
PECI protocol communication for CPU thermal management.

For this controller, the special clock and reset operation sequence is:
  probe: clk_prepare_enable() then reset_control_deassert()
  remove: clk_disable_unprepare() then reset_control_assert()

Co-developed-by: Mason Huo <mason.huo@starfivetech.com>
Signed-off-by: Mason Huo <mason.huo@starfivetech.com>
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
 MAINTAINERS                             |   8 +
 drivers/peci/controller/Kconfig         |  17 ++
 drivers/peci/controller/Makefile        |   1 +
 drivers/peci/controller/peci-starfive.c | 376 ++++++++++++++++++++++++
 4 files changed, 402 insertions(+)
 create mode 100644 drivers/peci/controller/peci-starfive.c

diff --git a/MAINTAINERS b/MAINTAINERS
index 834f88b7a41b..a8d7ece2d199 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -26224,6 +26224,14 @@ S:	Supported
 F:	Documentation/devicetree/bindings/interrupt-controller/starfive,jhb100-intc.yaml
 F:	drivers/irqchip/irq-starfive-jhb100-intc.c
 
+STARFIVE JHB100 PECI DRIVER
+M:	Changhuang Liang <changhuang.liang@starfivetech.com>
+M:	Mason Huo <mason.huo@starfivetech.com>
+L:	openbmc@lists.ozlabs.org (moderated for non-subscribers)
+S:	Maintained
+F:	Documentation/devicetree/bindings/peci/starfive,jhb100-peci.yaml
+F:	drivers/peci/controller/peci-starfive.c
+
 STARFIVE JHB100 PINCTRL DRIVERS
 M:	Changhuang Liang <changhuang.liang@starfivetech.com>
 M:	Lianfeng Ouyang <lianfeng.ouyang@starfivetech.com>
diff --git a/drivers/peci/controller/Kconfig b/drivers/peci/controller/Kconfig
index 4f9c245ad042..c0c35bc179ef 100644
--- a/drivers/peci/controller/Kconfig
+++ b/drivers/peci/controller/Kconfig
@@ -32,3 +32,20 @@ config PECI_NPCM
 
 	  This support is also available as a module. If so, the module
 	  will be called peci-npcm.
+
+config PECI_STARFIVE
+	tristate "STARFIVE PECI support"
+	depends on ARCH_STARFIVE || COMPILE_TEST
+	depends on OF
+	depends on HAS_IOMEM
+	select REGMAP_MMIO
+	help
+	  This option enables PECI controller driver for StarFive JHB100
+	  SoC. It allows BMC to discover devices connected to it, and
+	  communicate with them using PECI protocol.
+
+	  Say Y here if your system runs on StarFive JHB100 SoC and you are
+	  using it as BMC for Intel platform.
+
+	  This driver can also be built as a module. If so, the module will
+	  be called peci-starfive.
diff --git a/drivers/peci/controller/Makefile b/drivers/peci/controller/Makefile
index e247449bb423..935e356b058c 100644
--- a/drivers/peci/controller/Makefile
+++ b/drivers/peci/controller/Makefile
@@ -2,3 +2,4 @@
 
 obj-$(CONFIG_PECI_ASPEED)	+= peci-aspeed.o
 obj-$(CONFIG_PECI_NPCM)		+= peci-npcm.o
+obj-$(CONFIG_PECI_STARFIVE)	+= peci-starfive.o
diff --git a/drivers/peci/controller/peci-starfive.c b/drivers/peci/controller/peci-starfive.c
new file mode 100644
index 000000000000..6004cb27a774
--- /dev/null
+++ b/drivers/peci/controller/peci-starfive.c
@@ -0,0 +1,376 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2024 StarFive Technology Co., Ltd.
+ */
+
+#include <linux/unaligned.h>
+#include <linux/bitfield.h>
+#include <linux/clk.h>
+#include <linux/completion.h>
+#include <linux/interrupt.h>
+#include <linux/jiffies.h>
+#include <linux/minmax.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/peci.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <linux/reset.h>
+
+/* Control register */
+#define STARFIVE_PECI_CTRL			0x00
+/* automatically clears after transfer started */
+#define   STARFIVE_PECI_CTRL_START		BIT(0)
+#define   STARFIVE_PECI_CTRL_FCS_MODE		BIT(2)
+#define   STARFIVE_PECI_CTRL_AW_FCS_EN		BIT(3)
+#define   STARFIVE_PECI_CTRL_RDY		BIT(4)
+
+/* Read/Write length register */
+#define STARFIVE_PECI_HDR			0x04
+#define   STARFIVE_PECI_HDR_RD_LEN_MASK		GENMASK(23, 16)
+#define   STARFIVE_PECI_HDR_WR_LEN_MASK		GENMASK(15, 8)
+#define   STARFIVE_PECI_HDR_TARGET_ADDR_MASK	GENMASK(7, 0)
+
+/* Feature control register */
+#define STARFIVE_PECI_F_CTRL			0x0c
+#define   STARFIVE_PECI_F_CTRL_EN		BIT(0)
+
+/* Interrupt enable register */
+#define STARFIVE_PECI_INT_EN			0x10
+#define   STARFIVE_PECI_INT_XFER_DONE		BIT(0)
+#define   STARFIVE_PECI_INT_CFG_ERR		BIT(1)
+#define   STARFIVE_PECI_INT_TBIT_ERR		BIT(2)
+#define   STARFIVE_PECI_INT_BAD_WR_FCS		BIT(3)
+#define   STARFIVE_PECI_INT_ABORT_WR_FCS	BIT(4)
+#define   STARFIVE_PECI_INT_BAD_RD_FCS		BIT(5)
+#define   STARFIVE_PECI_INT_BUS_CONTENTION	BIT(6)
+#define   STARFIVE_PECI_INT_TBIT_OVER_LIMIT	BIT(7)
+#define   STARFIVE_PECI_INT_ALL			GENMASK(7, 0)
+
+/* Interrupt status register */
+#define STARFIVE_PECI_INT_STS			0x14
+#define   STARFIVE_PECI_STS_XFER_DONE		BIT(0)
+#define   STARFIVE_PECI_STS_CFG_ERR		BIT(1)
+#define   STARFIVE_PECI_STS_TBIT_ERR		BIT(2)
+#define   STARFIVE_PECI_STS_BAD_WR_FCS		BIT(3)
+#define   STARFIVE_PECI_STS_ABORT_WR_FCS	BIT(4)
+#define   STARFIVE_PECI_STS_BAD_RD_FCS		BIT(5)
+#define   STARFIVE_PECI_STS_BUS_CONTENTION	BIT(6)
+#define   STARFIVE_PECI_STS_TBIT_OVER_LIMIT	BIT(7)
+#define   STARFIVE_PECI_STS_MASK		GENMASK(7, 0)
+
+/* Received FCS data register */
+#define STARFIVE_PECI_FCS_RCVD			0x1C
+#define   STARFIVE_PECI_RCVD_WR_FCS_MASK	GENMASK(7, 0)
+#define   STARFIVE_PECI_RCVD_RD_FCS_MASK	GENMASK(15, 8)
+
+/* Rx/Tx Data Buffer Registers */
+#define STARFIVE_PECI_WR_DATA(n)		(0x70 + ((n) * 4))
+#define STARFIVE_PECI_RD_DATA(n)		(0xB0 + ((n) * 4))
+
+/* Hardware TX/RX data FIFOs are 64 bytes, but PECI core caps requests lower */
+#define STARFIVE_PECI_DATA_BUF_SIZE_MAX		min(64, PECI_REQUEST_MAX_BUF_SIZE)
+#define STARFIVE_PECI_MAX_REG			0x100
+
+/* Timeout */
+#define STARFIVE_PECI_IDLE_CHECK_TIMEOUT_US	(50 * USEC_PER_MSEC)
+#define STARFIVE_PECI_IDLE_CHECK_INTERVAL_US	(10 * USEC_PER_MSEC)
+#define STARFIVE_PECI_CMD_TIMEOUT_MS_DEFAULT	1000
+#define STARFIVE_PECI_CMD_TIMEOUT_MS_MAX	1000
+
+struct starfive_peci {
+	u32			cmd_timeout_ms;
+	struct completion	xfer_complete;
+	struct regmap		*regmap;
+	u32			status;
+	spinlock_t		lock;	/* sync completion status */
+	struct peci_controller	*controller;
+	struct device		*dev;
+	struct clk		*clk;
+	struct reset_control	*rst;
+	int			irq;
+};
+
+static int starfive_peci_xfer(struct peci_controller *controller,
+			      u8 addr, struct peci_request *req)
+{
+	struct starfive_peci *priv = dev_get_drvdata(controller->dev.parent);
+	unsigned long timeout = msecs_to_jiffies(priv->cmd_timeout_ms);
+	u32 msg_rd;
+	u32 cmd_sts;
+	u32 peci_hdr;
+	int i, ret, j;
+
+	if (req->tx.len > STARFIVE_PECI_DATA_BUF_SIZE_MAX ||
+	    req->rx.len > STARFIVE_PECI_DATA_BUF_SIZE_MAX)
+		return -EINVAL;
+
+	/* Check command sts and bus idle state */
+	ret = regmap_read_poll_timeout(priv->regmap,
+				       STARFIVE_PECI_CTRL, cmd_sts,
+				       cmd_sts & STARFIVE_PECI_CTRL_RDY,
+				       STARFIVE_PECI_IDLE_CHECK_INTERVAL_US,
+				       STARFIVE_PECI_IDLE_CHECK_TIMEOUT_US);
+	if (ret)
+		return ret;
+
+	spin_lock_irq(&priv->lock);
+	reinit_completion(&priv->xfer_complete);
+
+	peci_hdr = FIELD_PREP(STARFIVE_PECI_HDR_TARGET_ADDR_MASK, addr) |
+		   FIELD_PREP(STARFIVE_PECI_HDR_WR_LEN_MASK, req->tx.len) |
+		   FIELD_PREP(STARFIVE_PECI_HDR_RD_LEN_MASK, req->rx.len);
+	regmap_write(priv->regmap, STARFIVE_PECI_HDR, peci_hdr);
+
+	/* Currently, we do not support write commands, force this bit to 0. */
+	regmap_write_bits(priv->regmap, STARFIVE_PECI_CTRL,
+			  STARFIVE_PECI_CTRL_AW_FCS_EN, 0);
+
+	for (i = 0; i < ALIGN(req->tx.len, 4) / 4; i++)
+		regmap_write(priv->regmap, STARFIVE_PECI_WR_DATA(i),
+			     get_unaligned_le32(&req->tx.buf[4 * i]));
+
+	dev_dbg(priv->dev, "addr : %#02x, tx.len : %#02x, rx.len : %#02x\n",
+		addr, req->tx.len, req->rx.len);
+	print_hex_dump_bytes("TX : ", DUMP_PREFIX_NONE, req->tx.buf,
+			     req->tx.len);
+
+	priv->status = 0;
+
+	regmap_write_bits(priv->regmap, STARFIVE_PECI_CTRL,
+			  STARFIVE_PECI_CTRL_START, STARFIVE_PECI_CTRL_START);
+
+	spin_unlock_irq(&priv->lock);
+
+	ret = wait_for_completion_interruptible_timeout(&priv->xfer_complete,
+							timeout);
+	if (ret < 0)
+		return ret;
+
+	if (ret == 0) {
+		dev_dbg(priv->dev, "Timeout waiting for a response\n");
+		return -ETIMEDOUT;
+	}
+
+	spin_lock_irq(&priv->lock);
+
+	if (priv->status != STARFIVE_PECI_STS_XFER_DONE) {
+		spin_unlock_irq(&priv->lock);
+		dev_dbg(priv->dev, "No valid response, status: %#02x\n",
+			priv->status);
+		return -EIO;
+	}
+
+	regmap_read(priv->regmap, STARFIVE_PECI_FCS_RCVD, &msg_rd);
+	dev_dbg(priv->dev, "write & read command FCS : %#02lx & %#02lx\n",
+		FIELD_GET(STARFIVE_PECI_RCVD_WR_FCS_MASK, msg_rd),
+		FIELD_GET(STARFIVE_PECI_RCVD_RD_FCS_MASK, msg_rd));
+
+	for (i = 0; i < ALIGN(req->rx.len, 4) / 4; i++) {
+		regmap_read(priv->regmap, STARFIVE_PECI_RD_DATA(i), &msg_rd);
+
+		if (req->rx.len - 4 * (i + 1) >= 0) {
+			put_unaligned_be32(msg_rd, &req->rx.buf[req->rx.len - 4 * (i + 1)]);
+		} else {
+			for (j = req->rx.len % 4 - 1; j >= 0; j--) {
+				req->rx.buf[j] = (u8)msg_rd;
+				msg_rd >>= 8;
+			}
+		}
+	}
+
+	spin_unlock_irq(&priv->lock);
+
+	print_hex_dump_bytes("RX : ",
+			     DUMP_PREFIX_NONE, req->rx.buf, req->rx.len);
+
+	return 0;
+}
+
+static irqreturn_t starfive_peci_irq_handler(int irq, void *arg)
+{
+	struct starfive_peci *priv = arg;
+	u32 status;
+
+	spin_lock(&priv->lock);
+	regmap_read(priv->regmap, STARFIVE_PECI_INT_STS, &status);
+	priv->status |= (status & STARFIVE_PECI_STS_MASK);
+	regmap_write(priv->regmap, STARFIVE_PECI_INT_STS,
+		     status & STARFIVE_PECI_STS_MASK);
+
+	/*
+	 * All commands are terminated with the XFER_DONE bit set, even when
+	 * an error condition is reported alongside it.
+	 */
+	if (status & STARFIVE_PECI_STS_XFER_DONE)
+		complete(&priv->xfer_complete);
+
+	spin_unlock(&priv->lock);
+
+	return IRQ_HANDLED;
+}
+
+static void starfive_peci_clk_reset_release(void *data)
+{
+	struct starfive_peci *priv = data;
+
+	clk_disable_unprepare(priv->clk);
+	reset_control_assert(priv->rst);
+}
+
+static int starfive_peci_init_clk_rst(struct starfive_peci *priv)
+{
+	int ret;
+
+	priv->clk = devm_clk_get(priv->dev, NULL);
+	if (IS_ERR(priv->clk))
+		return dev_err_probe(priv->dev, PTR_ERR(priv->clk),
+				     "Failed to get peci clock\n");
+
+	priv->rst = devm_reset_control_get(priv->dev, NULL);
+	if (IS_ERR(priv->rst))
+		return dev_err_probe(priv->dev, PTR_ERR(priv->rst),
+				     "Failed to get reset control\n");
+
+	ret = clk_prepare_enable(priv->clk);
+	if (ret)
+		return dev_err_probe(priv->dev, ret,
+				     "Failed to enable peci clock\n");
+
+	ret = reset_control_deassert(priv->rst);
+	if (ret) {
+		clk_disable_unprepare(priv->clk);
+		return dev_err_probe(priv->dev, ret,
+				     "Failed to deassert reset control\n");
+	}
+
+	return devm_add_action_or_reset(priv->dev, starfive_peci_clk_reset_release,
+					priv);
+}
+
+static int starfive_peci_init_ctrl(struct starfive_peci *priv)
+{
+	u32 cmd_sts;
+	int ret;
+
+	ret = device_property_read_u32(priv->dev, "cmd-timeout-ms",
+				       &priv->cmd_timeout_ms);
+	if (ret) {
+		priv->cmd_timeout_ms = STARFIVE_PECI_CMD_TIMEOUT_MS_DEFAULT;
+	} else if (priv->cmd_timeout_ms > STARFIVE_PECI_CMD_TIMEOUT_MS_MAX ||
+		   priv->cmd_timeout_ms == 0) {
+		dev_warn(priv->dev,
+			 "Invalid cmd-timeout-ms: %u, falling back to: %u\n",
+			 priv->cmd_timeout_ms,
+			 STARFIVE_PECI_CMD_TIMEOUT_MS_DEFAULT);
+
+		priv->cmd_timeout_ms = STARFIVE_PECI_CMD_TIMEOUT_MS_DEFAULT;
+	}
+
+	regmap_write_bits(priv->regmap, STARFIVE_PECI_F_CTRL,
+			  STARFIVE_PECI_F_CTRL_EN, STARFIVE_PECI_F_CTRL_EN);
+	regmap_write_bits(priv->regmap, STARFIVE_PECI_CTRL,
+			  STARFIVE_PECI_CTRL_FCS_MODE, STARFIVE_PECI_CTRL_FCS_MODE);
+
+	ret = regmap_read_poll_timeout(priv->regmap,
+				       STARFIVE_PECI_CTRL, cmd_sts,
+				       cmd_sts & STARFIVE_PECI_CTRL_RDY,
+				       STARFIVE_PECI_IDLE_CHECK_INTERVAL_US,
+				       STARFIVE_PECI_IDLE_CHECK_TIMEOUT_US);
+	if (ret)
+		return ret;
+
+	regmap_write(priv->regmap, STARFIVE_PECI_INT_STS, STARFIVE_PECI_STS_MASK);
+
+	/* PECI interrupt enable */
+	regmap_write(priv->regmap, STARFIVE_PECI_INT_EN, STARFIVE_PECI_INT_ALL);
+
+	return 0;
+}
+
+static const struct regmap_config starfive_peci_regmap_config = {
+	.reg_bits = 32,
+	.val_bits = 32,
+	.max_register = STARFIVE_PECI_MAX_REG,
+	.fast_io = true,
+};
+
+static const struct peci_controller_ops starfive_ops = {
+	.xfer = starfive_peci_xfer,
+};
+
+static int starfive_peci_probe(struct platform_device *pdev)
+{
+	struct peci_controller *controller;
+	struct starfive_peci *priv;
+	void __iomem *base;
+	int ret;
+
+	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	priv->dev = &pdev->dev;
+	dev_set_drvdata(&pdev->dev, priv);
+
+	base = devm_platform_ioremap_resource(pdev, 0);
+	if (IS_ERR(base))
+		return PTR_ERR(base);
+
+	priv->regmap = devm_regmap_init_mmio(&pdev->dev, base,
+					     &starfive_peci_regmap_config);
+	if (IS_ERR(priv->regmap))
+		return dev_err_probe(priv->dev, PTR_ERR(priv->regmap),
+				     "Failed to initialize regmap\n");
+
+	priv->irq = platform_get_irq(pdev, 0);
+	if (priv->irq < 0)
+		return dev_err_probe(priv->dev, priv->irq, "Failed to get IRQ\n");
+
+	init_completion(&priv->xfer_complete);
+	spin_lock_init(&priv->lock);
+
+	ret = starfive_peci_init_clk_rst(priv);
+	if (ret)
+		return dev_err_probe(priv->dev, ret, "Failed to initialize clock and reset\n");
+
+	ret = devm_request_irq(&pdev->dev,
+			       priv->irq, starfive_peci_irq_handler,
+			       0, "peci-starfive", priv);
+	if (ret)
+		return dev_err_probe(priv->dev, ret, "Failed to request IRQ\n");
+
+	ret = starfive_peci_init_ctrl(priv);
+	if (ret)
+		return dev_err_probe(priv->dev, ret, "Failed to initialize control\n");
+
+	controller = devm_peci_controller_add(priv->dev, &starfive_ops);
+	if (IS_ERR(controller))
+		return dev_err_probe(priv->dev, PTR_ERR(controller),
+				     "Failed to add peci controller\n");
+
+	priv->controller = controller;
+
+	return 0;
+}
+
+static const struct of_device_id starfive_peci_of_table[] = {
+	{ .compatible = "starfive,jhb100-peci", },
+	{ }
+};
+MODULE_DEVICE_TABLE(of, starfive_peci_of_table);
+
+static struct platform_driver starfive_peci_driver = {
+	.probe	= starfive_peci_probe,
+	.driver = {
+		.name		= KBUILD_MODNAME,
+		.of_match_table = starfive_peci_of_table,
+	},
+};
+module_platform_driver(starfive_peci_driver);
+
+MODULE_AUTHOR("Changhuang Liang <changhuang.liang@starfivetech.com>");
+MODULE_AUTHOR("Mason Huo <mason.huo@starfivetech.com>");
+MODULE_DESCRIPTION("StarFive PECI driver");
+MODULE_LICENSE("GPL");
+MODULE_IMPORT_NS("PECI");
-- 
2.25.1

[PATCH v2 3/6] peci: Add support for PECI CC 0x83 retry condition

[Changhuang Liang]

Some PECI client devices may return completion code 0x83, this
completion code means that a command response is in progress, which
is not currently handled by the driver.

Add PECI_CC_RESP_IN_PROGRESS definition and map it to -EAGAIN so that
the request will be retried appropriately, similar to other retryable
completion codes (0x80, 0x81, 0x82).

Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
 drivers/peci/request.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/peci/request.c b/drivers/peci/request.c
index db2cc30a42a4..bf80bd205e60 100644
--- a/drivers/peci/request.c
+++ b/drivers/peci/request.c
@@ -71,6 +71,7 @@
 #define PECI_CC_NEED_RETRY			0x80
 #define PECI_CC_OUT_OF_RESOURCE			0x81
 #define PECI_CC_UNAVAIL_RESOURCE		0x82
+#define PECI_CC_RESP_IN_PROGRESS		0x83
 #define PECI_CC_INVALID_REQ			0x90
 #define PECI_CC_MCA_ERROR			0x91
 #define PECI_CC_CATASTROPHIC_MCA_ERROR		0x93
@@ -112,6 +113,7 @@ int peci_request_status(struct peci_request *req)
 	case PECI_CC_NEED_RETRY:
 	case PECI_CC_OUT_OF_RESOURCE:
 	case PECI_CC_UNAVAIL_RESOURCE:
+	case PECI_CC_RESP_IN_PROGRESS:
 		return -EAGAIN;
 	case PECI_CC_INVALID_REQ:
 		return -EINVAL;
-- 
2.25.1

[PATCH v2 4/6] peci: cpu: Add Intel Granite Rapids support

[Changhuang Liang]

Add support for detection of Intel Granite Rapids processor based on
CPU model.

Granite Rapids processors with the model set to INTEL_GRANITERAPIDS_X.
The data field for this entry is "gnr".

Tested on JHB100 BMC with Intel Granite Rapids processors.

Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
 drivers/peci/cpu.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/peci/cpu.c b/drivers/peci/cpu.c
index c9fc06c9ff53..abf004637949 100644
--- a/drivers/peci/cpu.c
+++ b/drivers/peci/cpu.c
@@ -325,6 +325,10 @@ static const struct peci_device_id peci_cpu_device_ids[] = {
 		.x86_vfm  = INTEL_EMERALDRAPIDS_X,
 		.data  = "emr",
 	},
+	{ /* Granite Rapids */
+		.x86_vfm = INTEL_GRANITERAPIDS_X,
+		.data	= "gnr",
+	},
 	{ }
 };
 MODULE_DEVICE_TABLE(peci, peci_cpu_device_ids);
-- 
2.25.1

[PATCH v2 5/6] hwmon: (peci/cputemp) Add support for Granite Rapids (GNR)

[Changhuang Liang]

Add Granite Rapids (GNR) CPU support to the PECI cputemp driver.

For Granite Rapids, the resolved cores mask must be collected from each
compute core. This implementation is relatively complex. Since we do not
use the resolved cores information for these CPUs, we can explicitly
state in the driver that the core mask is not supported for this model.

Define new cpu_info structure for GNR with minimum PECI revision 0x42 and
the thermal margin conversion function dts_ten_dot_six_to_millidegree().

Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
 drivers/hwmon/peci/cputemp.c | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/drivers/hwmon/peci/cputemp.c b/drivers/hwmon/peci/cputemp.c
index 457089c561b4..69c4a07b99f7 100644
--- a/drivers/hwmon/peci/cputemp.c
+++ b/drivers/hwmon/peci/cputemp.c
@@ -339,6 +339,18 @@ static int init_core_mask(struct peci_cputemp *priv)
 	u32 data;
 	int ret;
 
+	/*
+	 * For Granite Rapids, the resolved cores mask is relatively complex to implement.
+	 * Since we do not use the resolved cores information for this CPU, the driver
+	 * explicitly does not support the core mask for this model.
+	 */
+	if (!reg) {
+		dev_dbg(priv->dev,
+			"resolved cores scan is not supported on vendor-family-model 0x%x\n",
+			peci_dev->info.x86_vfm);
+		return -EOPNOTSUPP;
+	}
+
 	/* Get the RESOLVED_CORES register value */
 	switch (peci_dev->info.x86_vfm) {
 	case INTEL_ICELAKE_X:
@@ -543,6 +555,11 @@ static const struct cpu_info cpu_emr = {
 	.thermal_margin_to_millidegree = &dts_ten_dot_six_to_millidegree,
 };
 
+static const struct cpu_info cpu_gnr = {
+	.min_peci_revision = 0x42,
+	.thermal_margin_to_millidegree = &dts_ten_dot_six_to_millidegree,
+};
+
 static const struct auxiliary_device_id peci_cputemp_ids[] = {
 	{
 		.name = "peci_cpu.cputemp.hsx",
@@ -576,6 +593,10 @@ static const struct auxiliary_device_id peci_cputemp_ids[] = {
 		.name = "peci_cpu.cputemp.emr",
 		.driver_data = (kernel_ulong_t)&cpu_emr,
 	},
+	{
+		.name = "peci_cpu.cputemp.gnr",
+		.driver_data = (kernel_ulong_t)&cpu_gnr,
+	},
 	{ }
 };
 MODULE_DEVICE_TABLE(auxiliary, peci_cputemp_ids);
-- 
2.25.1

[PATCH v2 6/6] hwmon: (peci/dimmtemp) Add support for Granite Rapids (GNR)

[Changhuang Liang]

Add support for Granite Rapids (GNR) platform in PECI DIMM temperature
monitoring driver.

The GNR platform has different DIMM topology from previous generations,
with 12 channel ranks (CHAN_RANK_MAX_ON_GNR) and 2 DIMM indexes per
channel. Define these new constants and update CHAN_RANK_MAX to use
the GNR value since it represents the maximum across all supported
platforms.

Since the current peci core does not support domains, accessing GNR's
DIMM_TEMP_MAX and DIMM_TEMP_CRIT via PECI commands will be rejected
and return completion code 0x90 (invalid request). To handle this, the
read_thresholds callback is not defined for GNR, and the visibility
logic is updated to skip exposing the max and crit temperature
attributes.

The minimum PECI revision required for GNR is 0x42.

Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
 drivers/hwmon/peci/dimmtemp.c | 33 +++++++++++++++++++++++++++++----
 1 file changed, 29 insertions(+), 4 deletions(-)

diff --git a/drivers/hwmon/peci/dimmtemp.c b/drivers/hwmon/peci/dimmtemp.c
index bd3e8715dfec..791a8e866081 100644
--- a/drivers/hwmon/peci/dimmtemp.c
+++ b/drivers/hwmon/peci/dimmtemp.c
@@ -34,8 +34,10 @@
 #define DIMM_IDX_MAX_ON_SPR	2
 #define CHAN_RANK_MAX_ON_EMR	8
 #define DIMM_IDX_MAX_ON_EMR	2
+#define CHAN_RANK_MAX_ON_GNR	12
+#define DIMM_IDX_MAX_ON_GNR	2
 
-#define CHAN_RANK_MAX		CHAN_RANK_MAX_ON_HSX
+#define CHAN_RANK_MAX		CHAN_RANK_MAX_ON_GNR
 #define DIMM_IDX_MAX		DIMM_IDX_MAX_ON_HSX
 #define DIMM_NUMS_MAX		(CHAN_RANK_MAX * DIMM_IDX_MAX)
 
@@ -198,10 +200,18 @@ static umode_t dimmtemp_is_visible(const void *data, enum hwmon_sensor_types typ
 {
 	const struct peci_dimmtemp *priv = data;
 
-	if (test_bit(channel, priv->dimm_mask))
-		return 0444;
+	if (!test_bit(channel, priv->dimm_mask))
+		return 0;
 
-	return 0;
+	/*
+	 * Some platforms do not provide the DIMM temperature thresholds over
+	 * PECI - do not expose the corresponding attributes there.
+	 */
+	if ((attr == hwmon_temp_max || attr == hwmon_temp_crit) &&
+	    !priv->gen_info->read_thresholds)
+		return 0;
+
+	return 0444;
 }
 
 static const struct hwmon_ops peci_dimmtemp_ops = {
@@ -626,6 +636,17 @@ static const struct dimm_info dimm_emr = {
 	.read_thresholds = &read_thresholds_emr,
 };
 
+static const struct dimm_info dimm_gnr = {
+	.chan_rank_max	= CHAN_RANK_MAX_ON_GNR,
+	.dimm_idx_max	= DIMM_IDX_MAX_ON_GNR,
+	.min_peci_revision = 0x42,
+	/*
+	 * Reading DIMM_TEMP_MAX/DIMM_TEMP_CRIT over PECI is answered with
+	 * completion code 0x90 (invalid request) on Granite Rapids, so the
+	 * threshold attributes are not exposed on this platform.
+	 */
+};
+
 static const struct auxiliary_device_id peci_dimmtemp_ids[] = {
 	{
 		.name = "peci_cpu.dimmtemp.hsx",
@@ -659,6 +680,10 @@ static const struct auxiliary_device_id peci_dimmtemp_ids[] = {
 		.name = "peci_cpu.dimmtemp.emr",
 		.driver_data = (kernel_ulong_t)&dimm_emr,
 	},
+	{
+		.name = "peci_cpu.dimmtemp.gnr",
+		.driver_data = (kernel_ulong_t)&dimm_gnr,
+	},
 	{ }
 };
 MODULE_DEVICE_TABLE(auxiliary, peci_dimmtemp_ids);
-- 
2.25.1

Re: [PATCH v2 2/6] peci: controller: Add StarFive JHB100 PECI driver

[Philipp Zabel]

On Mo, 2026-09-28 at 00:59 -0700, Changhuang Liang wrote:
> Add PECI controller driver for StarFive JHB100 SoC. The driver supports
> PECI protocol communication for CPU thermal management.
> 
> For this controller, the special clock and reset operation sequence is:
>   probe: clk_prepare_enable() then reset_control_deassert()
>   remove: clk_disable_unprepare() then reset_control_assert()
> 
> Co-developed-by: Mason Huo <mason.huo@starfivetech.com>
> Signed-off-by: Mason Huo <mason.huo@starfivetech.com>
> Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
> ---
>  MAINTAINERS                             |   8 +
>  drivers/peci/controller/Kconfig         |  17 ++
>  drivers/peci/controller/Makefile        |   1 +
>  drivers/peci/controller/peci-starfive.c | 376 ++++++++++++++++++++++++
>  4 files changed, 402 insertions(+)
>  create mode 100644 drivers/peci/controller/peci-starfive.c
> 
[...]
> diff --git a/drivers/peci/controller/peci-starfive.c b/drivers/peci/controller/peci-starfive.c
> new file mode 100644
> index 000000000000..6004cb27a774
> --- /dev/null
> +++ b/drivers/peci/controller/peci-starfive.c
> @@ -0,0 +1,376 @@
[...]
> +static int starfive_peci_init_clk_rst(struct starfive_peci *priv)
> +{
> +	int ret;
> +
> +	priv->clk = devm_clk_get(priv->dev, NULL);
> +	if (IS_ERR(priv->clk))
> +		return dev_err_probe(priv->dev, PTR_ERR(priv->clk),
> +				     "Failed to get peci clock\n");
> +
> +	priv->rst = devm_reset_control_get(priv->dev, NULL);

Please use devm_reset_control_get_exclusive() directly.

> +	if (IS_ERR(priv->rst))
> +		return dev_err_probe(priv->dev, PTR_ERR(priv->rst),
> +				     "Failed to get reset control\n");
> +
> +	ret = clk_prepare_enable(priv->clk);
> +	if (ret)
> +		return dev_err_probe(priv->dev, ret,
> +				     "Failed to enable peci clock\n");
> +
> +	ret = reset_control_deassert(priv->rst);
> +	if (ret) {
> +		clk_disable_unprepare(priv->clk);
> +		return dev_err_probe(priv->dev, ret,
> +				     "Failed to deassert reset control\n");
> +	}
> +
> +	return devm_add_action_or_reset(priv->dev, starfive_peci_clk_reset_release,
> +					priv);

This could be simplified with devm_clk_get_enabled() and
devm_reset_control_get_exclusive_deasserted().

regards
Philipp

Re: [PATCH v2 2/6] peci: controller: Add StarFive JHB100 PECI driver

[Changhuang Liang]

Hi, Phillipp

Thanks for the review.

> On Mo, 2026-09-28 at 00:59 -0700, Changhuang Liang wrote:
> > Add PECI controller driver for StarFive JHB100 SoC. The driver
> > supports PECI protocol communication for CPU thermal management.
> >
> > For this controller, the special clock and reset operation sequence is:
> >   probe: clk_prepare_enable() then reset_control_deassert()
> >   remove: clk_disable_unprepare() then reset_control_assert()
> >
> > Co-developed-by: Mason Huo <mason.huo@starfivetech.com>
> > Signed-off-by: Mason Huo <mason.huo@starfivetech.com>
> > Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
> > ---
> >  MAINTAINERS                             |   8 +
> >  drivers/peci/controller/Kconfig         |  17 ++
> >  drivers/peci/controller/Makefile        |   1 +
> >  drivers/peci/controller/peci-starfive.c | 376
> > ++++++++++++++++++++++++
> >  4 files changed, 402 insertions(+)
> >  create mode 100644 drivers/peci/controller/peci-starfive.c
> >
> [...]
> > diff --git a/drivers/peci/controller/peci-starfive.c
> > b/drivers/peci/controller/peci-starfive.c
> > new file mode 100644
> > index 000000000000..6004cb27a774
> > --- /dev/null
> > +++ b/drivers/peci/controller/peci-starfive.c
> > @@ -0,0 +1,376 @@
> [...]
> > +static int starfive_peci_init_clk_rst(struct starfive_peci *priv) {
> > +	int ret;
> > +
> > +	priv->clk = devm_clk_get(priv->dev, NULL);
> > +	if (IS_ERR(priv->clk))
> > +		return dev_err_probe(priv->dev, PTR_ERR(priv->clk),
> > +				     "Failed to get peci clock\n");
> > +
> > +	priv->rst = devm_reset_control_get(priv->dev, NULL);
> 
> Please use devm_reset_control_get_exclusive() directly.

Okay, I'll update this.

> > +	if (IS_ERR(priv->rst))
> > +		return dev_err_probe(priv->dev, PTR_ERR(priv->rst),
> > +				     "Failed to get reset control\n");
> > +
> > +	ret = clk_prepare_enable(priv->clk);
> > +	if (ret)
> > +		return dev_err_probe(priv->dev, ret,
> > +				     "Failed to enable peci clock\n");
> > +
> > +	ret = reset_control_deassert(priv->rst);
> > +	if (ret) {
> > +		clk_disable_unprepare(priv->clk);
> > +		return dev_err_probe(priv->dev, ret,
> > +				     "Failed to deassert reset control\n");
> > +	}
> > +
> > +	return devm_add_action_or_reset(priv->dev,
> starfive_peci_clk_reset_release,
> > +					priv);
> 
> This could be simplified with devm_clk_get_enabled() and
> devm_reset_control_get_exclusive_deasserted().

This controller has a special clock reset sequence, and using this 
simplified version doesn't seem to meet the requirements.

probe: clk_prepare_enable() then reset_control_deassert()
remove: clk_disable_unprepare() then reset_control_assert()

Best Regards,
Changhuang