[PATCH v2 0/2] EDAC/amd64: Fix UMC csrow decode and consolidate Family 1Ah setup

[PATCH v2 0/2] EDAC/amd64: Fix UMC csrow decode and consolidate Family 1Ah setup

[Vishal Badole]

Two small amd64_edac fixes/cleanups for AMD Family 1Ah.

Patch 1 is the fix: mask the UMC chip select with 0x3, not 0x7. Only
four chip selects exist, so the old mask could decode an out-of-range
csrow and trip an EDAC warning.

Patch 2 sets zn_regs_v2 once at the Family 1Ah level instead of in each
model case, so future models cannot miss the v2 register layout.

Changes since v1:
 - Patch 1 (fix): Added Fixes: and Cc: stable, and move the fix first.
 - Patch 2 (cleanup): Updated the commit message.

v1: https://lore.kernel.org/all/20260925172639.97063-1-Vishal.Badole@amd.com/

Vishal Badole (2):
  EDAC/amd64: Mask UMC chip select to the four implemented selects
  EDAC/amd64: Set zn_regs_v2 for all Family 1Ah models

 drivers/edac/amd64_edac.c | 10 +++-------
 1 file changed, 3 insertions(+), 7 deletions(-)

-- 
2.34.1

[PATCH v2 1/2] EDAC/amd64: Mask UMC chip select to the four implemented selects

[Vishal Badole]

umc_get_err_info() masks the Chip Select from MCA_SYND with 0x7, a
leftover from Zen 1 where the architecture reserved space for up to
eight chip selects. Only four have ever been implemented, and newer
products document this as MCA_SYND_UMC[1:0] = Chip Select.

Since only four csrows are allocated, a syndrome with bit 2 set decodes
to an out-of-range csrow and trips:

  EDAC MC0: INTERNAL ERROR: csrow value is out of range (5 >= 4)

Mask with 0x3 to match the four implemented chip selects.

Fixes: 713ad54675fd ("EDAC, amd64: Define and register UMC error decode function")
Cc: <stable@vger.kernel.org>
Suggested-by: Yazen Ghannam <yazen.ghannam@amd.com>
Signed-off-by: Vishal Badole <Vishal.Badole@amd.com>
Reviewed-by: Yazen Ghannam <yazen.ghannam@amd.com>
---
 drivers/edac/amd64_edac.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
index 475235c402e8..ec4cc306b726 100644
--- a/drivers/edac/amd64_edac.c
+++ b/drivers/edac/amd64_edac.c
@@ -2802,7 +2802,7 @@ static inline void decode_bus_error(int node_id, struct mce *m)
 static void umc_get_err_info(struct mce *m, struct err_info *err)
 {
 	err->channel = (m->ipid & GENMASK(31, 0)) >> 20;
-	err->csrow = m->synd & 0x7;
+	err->csrow = m->synd & 0x3;
 }
 
 static void decode_umc_error(int node_id, struct mce *m)
-- 
2.34.1

[PATCH v2 2/2] EDAC/amd64: Set zn_regs_v2 for all Family 1Ah models

[Vishal Badole]

All Family 1Ah models use the v2 register layout. Today zn_regs_v2 is
set in each model case. This works, but a new model could forget to set
it and read the UMC registers at the wrong offsets.

Set zn_regs_v2 once at the Family 1Ah level so it applies to all models
uniformly, and drop the per-model assignments.

No functional change intended.

Suggested-by: Yazen Ghannam <yazen.ghannam@amd.com>
Signed-off-by: Vishal Badole <Vishal.Badole@amd.com>
Reviewed-by: Yazen Ghannam <yazen.ghannam@amd.com>
---
 drivers/edac/amd64_edac.c | 8 ++------
 1 file changed, 2 insertions(+), 6 deletions(-)

diff --git a/drivers/edac/amd64_edac.c b/drivers/edac/amd64_edac.c
index ec4cc306b726..b69c3f51dd37 100644
--- a/drivers/edac/amd64_edac.c
+++ b/drivers/edac/amd64_edac.c
@@ -3887,23 +3887,19 @@ static int per_family_init(struct amd64_pvt *pvt)
 		break;
 
 	case 0x1A:
+		pvt->flags.zn_regs_v2   = 1;
+
 		switch (pvt->model) {
 		case 0x00 ... 0x1f:
 			pvt->max_mcs            = 12;
-			pvt->flags.zn_regs_v2   = 1;
-			break;
-		case 0x40 ... 0x4f:
-			pvt->flags.zn_regs_v2   = 1;
 			break;
 		case 0x50 ... 0x57:
 		case 0xc0 ... 0xc7:
 			pvt->max_mcs            = 16;
-			pvt->flags.zn_regs_v2   = 1;
 			break;
 		case 0x90 ... 0x9f:
 		case 0xa0 ... 0xaf:
 			pvt->max_mcs            = 8;
-			pvt->flags.zn_regs_v2   = 1;
 			break;
 		}
 		break;
-- 
2.34.1

Re: [PATCH v2 1/2] EDAC/amd64: Mask UMC chip select to the four implemented selects

[Yazen Ghannam]

On Mon, Sep 28, 2026 at 11:39:34PM +0530, Vishal Badole wrote:
> umc_get_err_info() masks the Chip Select from MCA_SYND with 0x7, a
> leftover from Zen 1 where the architecture reserved space for up to
> eight chip selects. Only four have ever been implemented, and newer
> products document this as MCA_SYND_UMC[1:0] = Chip Select.
> 
> Since only four csrows are allocated, a syndrome with bit 2 set decodes
> to an out-of-range csrow and trips:
> 
>   EDAC MC0: INTERNAL ERROR: csrow value is out of range (5 >= 4)
> 
> Mask with 0x3 to match the four implemented chip selects.
> 

Here's an alternate commit message. Hopefully, this clears up some of
the points from Boris in the other thread.

Thanks,
Yazen

=======================================

For DRAM ECC errors, the chip select value can be found in the
MCA_SYND[ErrorInformation] field.

ErrorInformation[2:0] was first documented in Zen1. The 3 bit field
implied that up to 8 chip selects may be used.

However, all Zen-based systems have only ever had up to 4 chip selects.
So only bits [1:0] would contain a valid chip select value.

Future systems are redefining the field to ErrorInformation[1:0]. This
matches the existing 'up to 4 chip selects' implementations. And it
frees up the extra bit for other decoding.

Change the current chip select mask from 0x7 to 0x3 to prepare for the
decode change.