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From: Radim Krcmar <rkrcmar@qti.qualcomm.com>
To: Guodong Xu <guodong.xu@oss.qualcomm.com>
Cc: Jonathan Corbet <corbet@lwn.net>,
	Shuah Khan <skhan@linuxfoundation.org>,
	Paul Walmsley <pjw@kernel.org>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Alexandre Ghiti <alex@ghiti.fr>, Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>, Yixun Lan <dlan@kernel.org>,
	Chen Wang <chen.wang@linux.dev>,
	Inochi Amaoto <inochiama@gmail.com>,
	Randy Dunlap <rdunlap@infradead.org>,
	"linux-doc@vger.kernel.org" <linux-doc@vger.kernel.org>,
	"linux-riscv@lists.infradead.org"
	<linux-riscv@lists.infradead.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Conor Dooley <conor@kernel.org>,
	"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
	"spacemit@lists.linux.dev" <spacemit@lists.linux.dev>,
	"sophgo@lists.linux.dev" <sophgo@lists.linux.dev>,
	"linux-kselftest@vger.kernel.org"
	<linux-kselftest@vger.kernel.org>,
	Andy Chiu <tchiu@tenstorrent.com>,
	Florian Weimer <fweimer@redhat.com>,
	Peter Bergner <bergner@oss.tenstorrent.com>,
	Zihong Yao <zihong.plct@isrc.iscas.ac.cn>,
	Mark Harris <mark.hsj@gmail.com>,
	Aurelien Jarno <aurelien@aurel32.net>,
	Andrew Jones <andrew.jones@oss.qualcomm.com>,
	linux-riscv <linux-riscv-bounces@lists.infradead.org>
Subject: Re: [PATCH v8 11/11] riscv: hwprobe: Introduce rva23u64 base behavior
Date: Fri, 2 Oct 2026 12:48:59 +0000	[thread overview]
Message-ID: <DLUD4XZN9F16.2LBMTP1H5Q1VC@qti.qualcomm.com> (raw)
In-Reply-To: <7325307a9d029ef3277c343230a46a40.guodong.xu@oss.qualcomm.com>

2026-10-02T04:40:53-04:00, Guodong Xu <guodong.xu@oss.qualcomm.com>:
> On Tue, 29 Sep 2026 16:00:22 +0000, Radim Krcmar wrote:
>> 2026-09-20T03:18:31-04:00, Guodong Xu <guodong.xu@oss.qualcomm.com>:
>>> [ ... ]
>>> +	int cpu;
>>> +
>>> +	for_each_cpu(cpu, cpus) {
>>> +		if (!riscv_isa_base_available(hart_isa[cpu].isa_bases, base))
>>> +			return false;
>>
>> I think that extensions like F or V might be present in the ISA, yet
>> actually disabled in user-mode and this loop would misreport that
>> RVA23U64 is present.
>
> Only V has a way to be disabled by user-mode, through
> prctl(PR_RISCV_V_SET_CONTROL) with PR_RISCV_V_VSTATE_CTRL_OFF. That
> interface is questionable, and obsoleting it was discussed on the
> RISE Platform WG call on 16 Sep. And I plan to take this to LPC26
> next week in Prague to see what the community says.

Sounds like a good plan.  I'll have to figure out how to an invite to
the RISE meetings again...

> Besides, since you mentioned hwprobe_isa_ext0() below: actually, today's
> per hart hwprobe_isa_ext0() doesn't honor that prctl(V OFF), IMA_V stays
> set. Refer to [1].

Yes, that is an acceptable behavior.  User-mode should know what it does
with prctls, so hwprobe doesn't need to report the prctl affected state.

I meant that there are sstatus.FS/VS, senvcfg, sstateen, and possibly
other bits that control the set of extensions that are present in
user-mode based on variables outside of user-mode's control.

> There is no way for a user-mode application to disable F/D.
>
>> Is there a reason to diverge from how hwprobe_isa_ext0() does the
>> extension detection?  (has_fpu() and other global checks)
>
> Anyway, back to the RVA23U64 isa_base bit. In this design, I mean to
> report the per-hart RVA23U64 base, which is derived from hart_isa[cpu].isa.
> That bitmap has passed the validate callbacks in riscv_resolve_isa(), so
> it "matches kernel configuration as well as correct extension
> dependencies".

Whether kernel is compiled without a support for an extension that needs
to be enabled, or decided to not enable such extension at runtime
(command line parameter or weird platform) makes no difference to
user-mode and hwprobe output should be the same.

> There can be a mismatch on a system with heterogeneous harts, where
> has_fpu() is false globally but this particular hart has F/D. On such
> a system Zfa and Zcd are still reported for that hart today, which is
> the same mismatch. Same reason, because Zfa/Zcd passed validate callbacks
> per hart.

That is the bug.  User-mode can never utilize F, Zfa, and Zcd even on
harts that have those extensions, because sstatus.FS is always Off
without has_fpu().

I'll send patches for Zfa and Zcd in hwprobe_isa_ext0, but since this
series doesn't leverage the existing code, we'll need a fix here too.

> So the isa_base bit RVA23U64 behaves like the per-hart keys do today,
> while IMA_FD, IMA_C and IMA_V at the top of hwprobe_isa_ext0() are
> host-wide. My take is that when user space queries over all CPUs, it
> gets the intersection, where RVA23U64 is not reported in such a
> heterogeneous situation. Per hart, I want to keep the kernel config + ISA
> string truth.

Right, when querying across a subset of harts, user-mode should get the
maximal set of extension that are present on each.

Why we would report RVA23U64 on a hart that doesn't run RVA23U64
user-mode, though?

Thanks.

      reply	other threads:[~2026-10-02 12:49 UTC|newest]

Thread overview: 22+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-09-20  7:18 [PATCH v8 00/11] riscv: hwprobe: Expose RVA23U64 " Guodong Xu
2026-09-20  7:18 ` [PATCH v8 01/11] riscv: Add B to hwcap and hwprobe Guodong Xu
2026-09-21 14:24   ` Heinrich Schuchardt
2026-09-24 10:38     ` Guodong Xu
2026-09-29 15:12       ` Radim Krcmar
2026-09-29 16:30         ` Heinrich Schuchardt
2026-09-29 19:24           ` Conor Dooley
2026-10-02  9:22         ` Guodong Xu
2026-10-02 13:00           ` Radim Krcmar
2026-09-20  7:18 ` [PATCH v8 02/11] dt-bindings: riscv: Require block-size for Zicbom, Zicbop, and Zicboz Guodong Xu
2026-09-20  7:18 ` [PATCH v8 03/11] dt-bindings: riscv: Add Zic64b extension description Guodong Xu
2026-09-20  7:18 ` [PATCH v8 04/11] riscv: Add Zic64b to cpufeature and hwprobe Guodong Xu
2026-09-20  7:18 ` [PATCH v8 05/11] riscv: dts: spacemit: k3: Add Zic64b ISA extension Guodong Xu
2026-09-20  7:18 ` [PATCH v8 06/11] riscv: dts: spacemit: k1: " Guodong Xu
2026-09-20  7:18 ` [PATCH v8 07/11] riscv: dts: sophgo: sg2044: " Guodong Xu
2026-09-20  7:18 ` [PATCH v8 08/11] riscv: Add a getter for user PMLEN support Guodong Xu
2026-09-20  7:18 ` [PATCH v8 09/11] riscv: cpufeature: Introduce ISA bases bitmap and rva23u64 detection Guodong Xu
2026-09-20  7:18 ` [PATCH v8 10/11] riscv: cpu: Output isa bases lines in cpuinfo Guodong Xu
2026-09-20  7:18 ` [PATCH v8 11/11] riscv: hwprobe: Introduce rva23u64 base behavior Guodong Xu
2026-09-29 16:00   ` Radim Krcmar
2026-10-02  8:40     ` Guodong Xu
2026-10-02 12:48       ` Radim Krcmar [this message]

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