Re: [PATCH v5 00/23] Add basic clocks and resets for JHB100 SoC

[Conor Dooley <conor@kernel.org>]

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On Fri, Oct 02, 2026 at 02:30:12PM -0400, Brian Masney wrote:
> Hi Conor,
> 
> On Wed, Sep 30, 2026 at 11:43:22PM +0100, Conor Dooley wrote:
> > FYI clock folks,
> > 
> > On Wed, Sep 30, 2026 at 05:42:54AM -0700, Changhuang Liang wrote:
> > > The JHB100 SoC includes CRG (Clock and Reset Generator) for multiple
> > > subsystems:
> > > 
> > > The JHB100 SoC is divided into multiple subsystems, and basically
> > > each subsystem includes a CRG(Clock and Reset Generator):
> > >  - sys0crg/sys1crg/sys2crg/
> > >  - per0crg/per1crg/per2crg/per3crg/
> > >  - voutcrg
> > >  - vcecrg
> > >  - gpu0crg/gpu1crg
> > >  - cpucrg
> > >  - usbcrg
> > >  - host0crg/host1crg
> > >  - pcierpcrg
> > >  - husb0crg/husb1crg
> > >  - husbcmncrg
> > >  - husbd0crg/husbd1crg
> > >  - npucrg
> > > 
> > > In the current series, we will only add the following CRG:
> > >  - sys0crg/sys1crg/sys2crg/
> > >  - per0crg/per1crg/per2crg/per3crg/
> > > 
> > > The remaining CRG will be implemented in future series.
> > > 
> > > This series depends on the series:
> > > https://lore.kernel.org/all/20260806122553.182449-1-changhuang.liang@starfivetech.com/
> > > and it has been tested on the StarFive JHB100 EVB-1.
> > 
> > If this revision of the series is acceptable, I'd (although I'm not a
> > listed driver maintainer) like to send you a PR as I've done in the past
> > for Starfive stuff so that I can get some of these binding patches that
> > contain headers as part of a shared tag to be able to unblock a bunch of
> > the soc tree stuff. With conferences next week I understand that, with it
> > being -rc5, it's probably this doesn't make v7.4 but I figured it was
> > worth getting my intentions out there!
> 
> I am going through this series now, and I have a few minor changes to
> the clk drivers themselves.
> 
> Feel free to send a pull for the bindings and headers though.

Okay, PR below.

I won't put this tag into my linux-next branch until the drivers are in
the clock tree, but it'll let me get my ducks in a row, particularly
beneficial given next week I'll be somewhat AFK! Duck alignment is
currently ongoing in the "jhb100" branch in my repo..

Thanks Brian, Conor.

btw, will you be at LPC or OSSEU?

The following changes since commit cee9395acd8043be0644b25c34bfa86623f2b935:

  Linux 7.3-rc1 (2026-08-30 13:34:40 -0700)

are available in the Git repository at:

  https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/ tags/clk-starfive-jhb100

for you to fetch changes up to 17986e31f3b6142c302c8f9af16540422787daf9:

  dt-bindings: clock: Add StarFive JHB100 Peripheral-3 clock and reset generator (2026-10-02 20:58:09 +0100)

----------------------------------------------------------------
jhb100 clock binding shared tag

This is a shared tag for the Starfive jhb100 clock bindings, between the
riscv soc tree and clock tree.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

----------------------------------------------------------------
Changhuang Liang (7):
      dt-bindings: clock: Add StarFive JHB100 System-0 clock and reset generator
      dt-bindings: clock: Add StarFive JHB100 System-1 clock and reset generator
      dt-bindings: clock: Add StarFive JHB100 System-2 clock and reset generator
      dt-bindings: clock: Add StarFive JHB100 Peripheral-0 clock and reset generator
      dt-bindings: clock: Add StarFive JHB100 Peripheral-1 clock and reset generator
      dt-bindings: clock: Add StarFive JHB100 Peripheral-2 clock and reset generator
      dt-bindings: clock: Add StarFive JHB100 Peripheral-3 clock and reset generator

 Documentation/devicetree/bindings/clock/starfive,jhb100-per0crg.yaml |  70 +++++++++++++++++++++++++++
 Documentation/devicetree/bindings/clock/starfive,jhb100-per1crg.yaml |  70 +++++++++++++++++++++++++++
 Documentation/devicetree/bindings/clock/starfive,jhb100-per2crg.yaml |  76 +++++++++++++++++++++++++++++
 Documentation/devicetree/bindings/clock/starfive,jhb100-per3crg.yaml |  76 +++++++++++++++++++++++++++++
 Documentation/devicetree/bindings/clock/starfive,jhb100-sys0crg.yaml |  63 ++++++++++++++++++++++++
 Documentation/devicetree/bindings/clock/starfive,jhb100-sys1crg.yaml |  71 +++++++++++++++++++++++++++
 Documentation/devicetree/bindings/clock/starfive,jhb100-sys2crg.yaml |  64 +++++++++++++++++++++++++
 include/dt-bindings/clock/starfive,jhb100-crg.h                      | 542 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 include/dt-bindings/reset/starfive,jhb100-crg.h                      | 186 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 9 files changed, 1218 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/starfive,jhb100-per0crg.yaml
 create mode 100644 Documentation/devicetree/bindings/clock/starfive,jhb100-per1crg.yaml
 create mode 100644 Documentation/devicetree/bindings/clock/starfive,jhb100-per2crg.yaml
 create mode 100644 Documentation/devicetree/bindings/clock/starfive,jhb100-per3crg.yaml
 create mode 100644 Documentation/devicetree/bindings/clock/starfive,jhb100-sys0crg.yaml
 create mode 100644 Documentation/devicetree/bindings/clock/starfive,jhb100-sys1crg.yaml
 create mode 100644 Documentation/devicetree/bindings/clock/starfive,jhb100-sys2crg.yaml
 create mode 100644 include/dt-bindings/clock/starfive,jhb100-crg.h
 create mode 100644 include/dt-bindings/reset/starfive,jhb100-crg.h

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