* [PATCH v6 1/6] dt-bindings: iio: imu: icm42600: Add ICM-42670-P
2026-10-09 14:12 [PATCH v6 0/6] Add support for InvenSense ICM-42370-P accelerometer Kanak Shilledar
@ 2026-10-09 14:12 ` Kanak Shilledar
2026-10-09 14:12 ` [PATCH v6 2/6] iio: imu: inv_icm42607: Simplify IIO channel macros Kanak Shilledar
` (4 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: Kanak Shilledar @ 2026-10-09 14:12 UTC (permalink / raw)
To: Henrik Grimler, Jonathan Cameron, David Lechner, Nuno Sá,
Andy Shevchenko, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Jean-Baptiste Maneyrol, Joshua Crofts, Marcelo Schmitt,
Chris Morgan
Cc: Kanak Shilledar, kernel, linux-iio, devicetree, linux-kernel
TDK Invensense, ICM-42370-P is a 3-axis accelerometer. The device can
support I2C, SPI and I3C. This device only has an accelerometer and
lacks gyroscope and it has very similar properties as that of the
icm42607/p the gyroscope feature is controlled via the driver depending
on the device. Add this device to the existing dt-binding and update the
description to match the devices.
Datasheet: https://www.invensense.tdk.com/en-us/products/3-axis/icm-42370-p
Signed-off-by: Kanak Shilledar <kanak.shilledar@axis.com>
---
Documentation/devicetree/bindings/iio/imu/invensense,icm42600.yaml | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/iio/imu/invensense,icm42600.yaml b/Documentation/devicetree/bindings/iio/imu/invensense,icm42600.yaml
index 9e22b603d47fb..7d7ae093fcc96 100644
--- a/Documentation/devicetree/bindings/iio/imu/invensense,icm42600.yaml
+++ b/Documentation/devicetree/bindings/iio/imu/invensense,icm42600.yaml
@@ -11,10 +11,11 @@ maintainers:
description: |
6-axis MotionTracking device that combines a 3-axis gyroscope and a 3-axis
- accelerometer.
+ accelerometer. Some devices such as the Invensense, ICM-42370-P only has a
+ 3-axis accelerometer.
It has a configurable host interface that supports I3C, I2C and SPI serial
- communication, features a 2kB FIFO and 2 programmable interrupts with
+ communication, features up to 2.25kB FIFO and 2 programmable interrupts with
ultra-low-power wake-on-motion support to minimize system power consumption.
Other industry-leading features include InvenSense on-chip APEX Motion
@@ -28,6 +29,7 @@ properties:
compatible:
oneOf:
- enum:
+ - invensense,icm42370p
- invensense,icm42600
- invensense,icm42602
- invensense,icm42605
--
2.43.0
^ permalink raw reply [flat|nested] 7+ messages in thread* [PATCH v6 2/6] iio: imu: inv_icm42607: Simplify IIO channel macros
2026-10-09 14:12 [PATCH v6 0/6] Add support for InvenSense ICM-42370-P accelerometer Kanak Shilledar
2026-10-09 14:12 ` [PATCH v6 1/6] dt-bindings: iio: imu: icm42600: Add ICM-42670-P Kanak Shilledar
@ 2026-10-09 14:12 ` Kanak Shilledar
2026-10-09 14:12 ` [PATCH v6 3/6] iio: imu: inv_icm42607: Initialize gyro based on chip_info Kanak Shilledar
` (3 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: Kanak Shilledar @ 2026-10-09 14:12 UTC (permalink / raw)
To: Henrik Grimler, Jonathan Cameron, David Lechner, Nuno Sá,
Andy Shevchenko, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Jean-Baptiste Maneyrol, Joshua Crofts, Marcelo Schmitt,
Chris Morgan
Cc: Kanak Shilledar, kernel, linux-iio, devicetree, linux-kernel
The INV_ICM42607_ACCEL_CHAN and INV_ICM42607_GYRO_CHAN macro had a third
parameter of _ext_info, drop it and just point the .ext_info field to
the respective inv_icm42607_*_ext_infos. This reduces the repetitive
calling of inv_icm42607_*_ext_infos struct in the IIO channel spec
struct and makes the code more easy to follow.
Reviewed-by: Marcelo Schmitt <marcelo.schmitt1@gmail.com>
Signed-off-by: Kanak Shilledar <kanak.shilledar@axis.com>
---
drivers/iio/imu/inv_icm42607/inv_icm42607_accel.c | 13 +++++--------
drivers/iio/imu/inv_icm42607/inv_icm42607_gyro.c | 13 +++++--------
2 files changed, 10 insertions(+), 16 deletions(-)
diff --git a/drivers/iio/imu/inv_icm42607/inv_icm42607_accel.c b/drivers/iio/imu/inv_icm42607/inv_icm42607_accel.c
index 0b3f035c2da0c..9a3ace3e7fcf9 100644
--- a/drivers/iio/imu/inv_icm42607/inv_icm42607_accel.c
+++ b/drivers/iio/imu/inv_icm42607/inv_icm42607_accel.c
@@ -17,7 +17,7 @@
#include "inv_icm42607.h"
#include "inv_icm42607_temp.h"
-#define INV_ICM42607_ACCEL_CHAN(_modifier, _index, _ext_info) \
+#define INV_ICM42607_ACCEL_CHAN(_modifier, _index) \
{ \
.type = IIO_ACCEL, \
.modified = 1, \
@@ -34,7 +34,7 @@
.storagebits = 16, \
.endianness = IIO_BE, \
}, \
- .ext_info = _ext_info, \
+ .ext_info = inv_icm42607_accel_ext_infos, \
}
enum inv_icm42607_accel_scan {
@@ -50,12 +50,9 @@ static const struct iio_chan_spec_ext_info inv_icm42607_accel_ext_infos[] = {
};
static const struct iio_chan_spec inv_icm42607_accel_channels[] = {
- INV_ICM42607_ACCEL_CHAN(IIO_MOD_X, INV_ICM42607_ACCEL_SCAN_X,
- inv_icm42607_accel_ext_infos),
- INV_ICM42607_ACCEL_CHAN(IIO_MOD_Y, INV_ICM42607_ACCEL_SCAN_Y,
- inv_icm42607_accel_ext_infos),
- INV_ICM42607_ACCEL_CHAN(IIO_MOD_Z, INV_ICM42607_ACCEL_SCAN_Z,
- inv_icm42607_accel_ext_infos),
+ INV_ICM42607_ACCEL_CHAN(IIO_MOD_X, INV_ICM42607_ACCEL_SCAN_X),
+ INV_ICM42607_ACCEL_CHAN(IIO_MOD_Y, INV_ICM42607_ACCEL_SCAN_Y),
+ INV_ICM42607_ACCEL_CHAN(IIO_MOD_Z, INV_ICM42607_ACCEL_SCAN_Z),
INV_ICM42607_TEMP_CHAN(INV_ICM42607_ACCEL_SCAN_TEMP),
};
diff --git a/drivers/iio/imu/inv_icm42607/inv_icm42607_gyro.c b/drivers/iio/imu/inv_icm42607/inv_icm42607_gyro.c
index 5b4683c2dd1e4..a3bad6fbc1981 100644
--- a/drivers/iio/imu/inv_icm42607/inv_icm42607_gyro.c
+++ b/drivers/iio/imu/inv_icm42607/inv_icm42607_gyro.c
@@ -17,7 +17,7 @@
#include "inv_icm42607.h"
#include "inv_icm42607_temp.h"
-#define INV_ICM42607_GYRO_CHAN(_modifier, _index, _ext_info) \
+#define INV_ICM42607_GYRO_CHAN(_modifier, _index) \
{ \
.type = IIO_ANGL_VEL, \
.modified = 1, \
@@ -34,7 +34,7 @@
.storagebits = 16, \
.endianness = IIO_BE, \
}, \
- .ext_info = _ext_info, \
+ .ext_info = inv_icm42607_gyro_ext_infos, \
}
enum inv_icm42607_gyro_scan {
@@ -50,12 +50,9 @@ static const struct iio_chan_spec_ext_info inv_icm42607_gyro_ext_infos[] = {
};
static const struct iio_chan_spec inv_icm42607_gyro_channels[] = {
- INV_ICM42607_GYRO_CHAN(IIO_MOD_X, INV_ICM42607_GYRO_SCAN_X,
- inv_icm42607_gyro_ext_infos),
- INV_ICM42607_GYRO_CHAN(IIO_MOD_Y, INV_ICM42607_GYRO_SCAN_Y,
- inv_icm42607_gyro_ext_infos),
- INV_ICM42607_GYRO_CHAN(IIO_MOD_Z, INV_ICM42607_GYRO_SCAN_Z,
- inv_icm42607_gyro_ext_infos),
+ INV_ICM42607_GYRO_CHAN(IIO_MOD_X, INV_ICM42607_GYRO_SCAN_X),
+ INV_ICM42607_GYRO_CHAN(IIO_MOD_Y, INV_ICM42607_GYRO_SCAN_Y),
+ INV_ICM42607_GYRO_CHAN(IIO_MOD_Z, INV_ICM42607_GYRO_SCAN_Z),
INV_ICM42607_TEMP_CHAN(INV_ICM42607_GYRO_SCAN_TEMP),
};
--
2.43.0
^ permalink raw reply [flat|nested] 7+ messages in thread* [PATCH v6 3/6] iio: imu: inv_icm42607: Initialize gyro based on chip_info
2026-10-09 14:12 [PATCH v6 0/6] Add support for InvenSense ICM-42370-P accelerometer Kanak Shilledar
2026-10-09 14:12 ` [PATCH v6 1/6] dt-bindings: iio: imu: icm42600: Add ICM-42670-P Kanak Shilledar
2026-10-09 14:12 ` [PATCH v6 2/6] iio: imu: inv_icm42607: Simplify IIO channel macros Kanak Shilledar
@ 2026-10-09 14:12 ` Kanak Shilledar
2026-10-09 14:12 ` [PATCH v6 4/6] iio: imu: inv_icm42607: Add support for ICM-42370-P Kanak Shilledar
` (2 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: Kanak Shilledar @ 2026-10-09 14:12 UTC (permalink / raw)
To: Henrik Grimler, Jonathan Cameron, David Lechner, Nuno Sá,
Andy Shevchenko, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Jean-Baptiste Maneyrol, Joshua Crofts, Marcelo Schmitt,
Chris Morgan
Cc: Kanak Shilledar, kernel, linux-iio, devicetree, linux-kernel
Update the chip_info struct with a new `has_gyro` property to support,
devices which do not have gyro functionality. This is a precursor for
adding support for the Invensense, ICM-42370-P. It is similar to the
existing device except it only has accelerometer. Check all operations
related to gyro with the boolean.
Signed-off-by: Kanak Shilledar <kanak.shilledar@axis.com>
---
drivers/iio/imu/inv_icm42607/inv_icm42607.h | 1 +
drivers/iio/imu/inv_icm42607/inv_icm42607_core.c | 57 ++++++++++++++++--------
2 files changed, 39 insertions(+), 19 deletions(-)
diff --git a/drivers/iio/imu/inv_icm42607/inv_icm42607.h b/drivers/iio/imu/inv_icm42607/inv_icm42607.h
index 4d51b0da1aa16..e4075288247b8 100644
--- a/drivers/iio/imu/inv_icm42607/inv_icm42607.h
+++ b/drivers/iio/imu/inv_icm42607/inv_icm42607.h
@@ -130,6 +130,7 @@ struct inv_icm42607_hw {
const char *name;
const struct inv_icm42607_conf *conf;
u8 whoami;
+ bool has_gyro;
};
/**
diff --git a/drivers/iio/imu/inv_icm42607/inv_icm42607_core.c b/drivers/iio/imu/inv_icm42607/inv_icm42607_core.c
index 190e998f7b8ef..46274ecfa7b94 100644
--- a/drivers/iio/imu/inv_icm42607/inv_icm42607_core.c
+++ b/drivers/iio/imu/inv_icm42607/inv_icm42607_core.c
@@ -96,6 +96,7 @@ const struct inv_icm42607_hw inv_icm42607_hw_data = {
.whoami = INV_ICM42607_WHOAMI,
.name = "icm42607",
.conf = &inv_icm42607_default_conf,
+ .has_gyro = true,
};
EXPORT_SYMBOL_NS_GPL(inv_icm42607_hw_data, "IIO_ICM42607");
@@ -103,6 +104,7 @@ const struct inv_icm42607_hw inv_icm42607p_hw_data = {
.whoami = INV_ICM42607P_WHOAMI,
.name = "icm42607p",
.conf = &inv_icm42607_default_conf,
+ .has_gyro = true,
};
EXPORT_SYMBOL_NS_GPL(inv_icm42607p_hw_data, "IIO_ICM42607");
@@ -160,7 +162,11 @@ int inv_icm42607_get_pwr_mgmt0(struct inv_icm42607_state *st,
if (ret)
return ret;
- *gyro = FIELD_GET(INV_ICM42607_PWR_MGMT0_GYRO_MODE_MASK, val);
+ if (st->hw->has_gyro)
+ *gyro = FIELD_GET(INV_ICM42607_PWR_MGMT0_GYRO_MODE_MASK, val);
+ else
+ *gyro = INV_ICM42607_SENSOR_MODE_OFF;
+
*accel = FIELD_GET(INV_ICM42607_PWR_MGMT0_ACCEL_MODE_MASK, val);
return 0;
@@ -176,6 +182,10 @@ static int inv_icm42607_set_pwr_mgmt0(struct inv_icm42607_state *st,
s64 disable_wait;
int ret;
+ /* Disable gyro if has_gyro is not set */
+ if (!st->hw->has_gyro)
+ gyro = INV_ICM42607_SENSOR_MODE_OFF;
+
ret = inv_icm42607_get_pwr_mgmt0(st, &oldgyro, &oldaccel);
if (ret)
return ret;
@@ -417,29 +427,37 @@ static int inv_icm42607_set_init_conf(struct inv_icm42607_state *st,
unsigned int val;
int ret;
- val = FIELD_PREP(INV_ICM42607_PWR_MGMT0_GYRO_MODE_MASK, conf->gyro.mode);
- val |= FIELD_PREP(INV_ICM42607_PWR_MGMT0_ACCEL_MODE_MASK, conf->accel.mode);
+ if (st->hw->has_gyro)
+ val = FIELD_PREP(INV_ICM42607_PWR_MGMT0_ACCEL_MODE_MASK, conf->accel.mode) |
+ FIELD_PREP(INV_ICM42607_PWR_MGMT0_GYRO_MODE_MASK, conf->gyro.mode);
+ else
+ val = FIELD_PREP(INV_ICM42607_PWR_MGMT0_ACCEL_MODE_MASK, conf->accel.mode);
+
ret = regmap_write(st->map, INV_ICM42607_REG_PWR_MGMT0, val);
if (ret)
return ret;
- val = FIELD_PREP(INV_ICM42607_GYRO_CONFIG0_FS_SEL_MASK, conf->gyro.fs);
- val |= FIELD_PREP(INV_ICM42607_GYRO_CONFIG0_ODR_MASK, conf->gyro.odr);
- ret = regmap_write(st->map, INV_ICM42607_REG_GYRO_CONFIG0, val);
- if (ret)
- return ret;
+ if (st->hw->has_gyro) {
+ val = FIELD_PREP(INV_ICM42607_GYRO_CONFIG0_FS_SEL_MASK, conf->gyro.fs) |
+ FIELD_PREP(INV_ICM42607_GYRO_CONFIG0_ODR_MASK, conf->gyro.odr);
+ ret = regmap_write(st->map, INV_ICM42607_REG_GYRO_CONFIG0, val);
+ if (ret)
+ return ret;
+ }
- val = FIELD_PREP(INV_ICM42607_ACCEL_CONFIG0_FS_SEL_MASK, conf->accel.fs);
- val |= FIELD_PREP(INV_ICM42607_ACCEL_CONFIG0_ODR_MASK, conf->accel.odr);
+ val = FIELD_PREP(INV_ICM42607_ACCEL_CONFIG0_FS_SEL_MASK, conf->accel.fs) |
+ FIELD_PREP(INV_ICM42607_ACCEL_CONFIG0_ODR_MASK, conf->accel.odr);
ret = regmap_write(st->map, INV_ICM42607_REG_ACCEL_CONFIG0, val);
if (ret)
return ret;
- val = FIELD_PREP(INV_ICM42607_GYRO_CONFIG1_FILTER_MASK, conf->gyro.filter);
- ret = regmap_update_bits(st->map, INV_ICM42607_REG_GYRO_CONFIG1,
- INV_ICM42607_GYRO_CONFIG1_FILTER_MASK, val);
- if (ret)
- return ret;
+ if (st->hw->has_gyro) {
+ val = FIELD_PREP(INV_ICM42607_GYRO_CONFIG1_FILTER_MASK, conf->gyro.filter);
+ ret = regmap_update_bits(st->map, INV_ICM42607_REG_GYRO_CONFIG1,
+ INV_ICM42607_GYRO_CONFIG1_FILTER_MASK, val);
+ if (ret)
+ return ret;
+ }
val = FIELD_PREP(INV_ICM42607_ACCEL_CONFIG1_FILTER_MASK, conf->accel.filter);
ret = regmap_update_bits(st->map, INV_ICM42607_REG_ACCEL_CONFIG1,
@@ -635,10 +653,11 @@ int inv_icm42607_core_probe(struct regmap *regmap,
if (IS_ERR(st->indio_accel))
return PTR_ERR(st->indio_accel);
- /* Initialize IIO device for Gyro */
- st->indio_gyro = inv_icm42607_gyro_init(st);
- if (IS_ERR(st->indio_gyro))
- return PTR_ERR(st->indio_gyro);
+ if (st->hw->has_gyro) {
+ st->indio_gyro = inv_icm42607_gyro_init(st);
+ if (IS_ERR(st->indio_gyro))
+ return PTR_ERR(st->indio_gyro);
+ }
return 0;
}
--
2.43.0
^ permalink raw reply [flat|nested] 7+ messages in thread* [PATCH v6 4/6] iio: imu: inv_icm42607: Add support for ICM-42370-P
2026-10-09 14:12 [PATCH v6 0/6] Add support for InvenSense ICM-42370-P accelerometer Kanak Shilledar
` (2 preceding siblings ...)
2026-10-09 14:12 ` [PATCH v6 3/6] iio: imu: inv_icm42607: Initialize gyro based on chip_info Kanak Shilledar
@ 2026-10-09 14:12 ` Kanak Shilledar
2026-10-09 14:12 ` [PATCH v6 5/6] iio: imu: inv_icm42607: Implement MREGx register access Kanak Shilledar
2026-10-09 14:12 ` [PATCH v6 6/6] iio: imu: inv_icm42607: Add accelerometer calibbias support Kanak Shilledar
5 siblings, 0 replies; 7+ messages in thread
From: Kanak Shilledar @ 2026-10-09 14:12 UTC (permalink / raw)
To: Henrik Grimler, Jonathan Cameron, David Lechner, Nuno Sá,
Andy Shevchenko, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Jean-Baptiste Maneyrol, Joshua Crofts, Marcelo Schmitt,
Chris Morgan
Cc: Kanak Shilledar, kernel, linux-iio, devicetree, linux-kernel
Add support for the Invensense ICM-42370-P MEMS MotionTracking 3-axis
accelerometer with built-in temperature sensor. This device is almost
identical to the existing Invensense ICM-42607-P IMU, but lacks
gyroscope. The device supports I2C, SPI and I3C. Implement only I2C
support for now, and provide support for raw sensor reads via sysfs.
There is also a built-in temperature sensor but it can not be turned off
similar to the ICM-42607.
While at it, change so dev_err_probe() is returned
when the WHO_AM_I read fails.
Datasheet: https://www.invensense.tdk.com/en-us/products/3-axis/icm-42370-p
Reviewed-by: Marcelo Schmitt <marcelo.schmitt1@gmail.com>
Signed-off-by: Kanak Shilledar <kanak.shilledar@axis.com>
---
drivers/iio/imu/inv_icm42607/inv_icm42607.h | 2 ++
drivers/iio/imu/inv_icm42607/inv_icm42607_core.c | 24 ++++++++++++++++++++++--
drivers/iio/imu/inv_icm42607/inv_icm42607_i2c.c | 6 ++++++
3 files changed, 30 insertions(+), 2 deletions(-)
diff --git a/drivers/iio/imu/inv_icm42607/inv_icm42607.h b/drivers/iio/imu/inv_icm42607/inv_icm42607.h
index e4075288247b8..674a9896fabb3 100644
--- a/drivers/iio/imu/inv_icm42607/inv_icm42607.h
+++ b/drivers/iio/imu/inv_icm42607/inv_icm42607.h
@@ -367,6 +367,7 @@ struct inv_icm42607_sensor_state {
#define INV_ICM42607_REG_FIFO_DATA 0x3F
#define INV_ICM42607_REG_WHOAMI 0x75
+#define INV_ICM42370P_WHOAMI 0x0D
#define INV_ICM42607P_WHOAMI 0x60
#define INV_ICM42607_WHOAMI 0x67
@@ -391,6 +392,7 @@ struct inv_icm42607_sensor_state {
typedef int (*inv_icm42607_bus_setup)(struct inv_icm42607_state *);
extern const struct regmap_config inv_icm42607_regmap_config;
+extern const struct inv_icm42607_hw inv_icm42370p_hw_data;
extern const struct inv_icm42607_hw inv_icm42607_hw_data;
extern const struct inv_icm42607_hw inv_icm42607p_hw_data;
extern const struct dev_pm_ops inv_icm42607_pm_ops;
diff --git a/drivers/iio/imu/inv_icm42607/inv_icm42607_core.c b/drivers/iio/imu/inv_icm42607/inv_icm42607_core.c
index 46274ecfa7b94..75c9617e5d1e7 100644
--- a/drivers/iio/imu/inv_icm42607/inv_icm42607_core.c
+++ b/drivers/iio/imu/inv_icm42607/inv_icm42607_core.c
@@ -77,6 +77,15 @@ const struct regmap_config inv_icm42607_regmap_config = {
EXPORT_SYMBOL_NS_GPL(inv_icm42607_regmap_config, "IIO_ICM42607");
/* chip initial default configuration */
+static const struct inv_icm42607_conf inv_icm42370_default_conf = {
+ .accel = {
+ .mode = INV_ICM42607_SENSOR_MODE_OFF,
+ .fs = INV_ICM42607_ACCEL_FS_4G,
+ .odr = INV_ICM42607_ODR_100HZ,
+ .filter = INV_ICM42607_FILTER_BW_25HZ,
+ },
+};
+
static const struct inv_icm42607_conf inv_icm42607_default_conf = {
.gyro = {
.mode = INV_ICM42607_SENSOR_MODE_OFF,
@@ -92,6 +101,13 @@ static const struct inv_icm42607_conf inv_icm42607_default_conf = {
},
};
+const struct inv_icm42607_hw inv_icm42370p_hw_data = {
+ .whoami = INV_ICM42370P_WHOAMI,
+ .name = "icm42370p",
+ .conf = &inv_icm42370_default_conf,
+};
+EXPORT_SYMBOL_NS_GPL(inv_icm42370p_hw_data, "IIO_ICM42607");
+
const struct inv_icm42607_hw inv_icm42607_hw_data = {
.whoami = INV_ICM42607_WHOAMI,
.name = "icm42607",
@@ -486,7 +502,7 @@ static int inv_icm42607_setup(struct inv_icm42607_state *st,
ret = regmap_read(st->map, INV_ICM42607_REG_WHOAMI, &val);
if (ret)
- return ret;
+ return dev_err_probe(dev, ret, "WHOAMI read failed\n");
/* Warn, but don't fail. */
if (val != st->hw->whoami)
@@ -648,7 +664,11 @@ int inv_icm42607_core_probe(struct regmap *regmap,
pm_runtime_set_autosuspend_delay(dev, INV_ICM42607_SUSPEND_DELAY_MS);
pm_runtime_use_autosuspend(dev);
- /* Initialize IIO device for Accel */
+ /*
+ * Invensense, ICM42607 and ICM42607P both have accelerometer
+ * and gyroscope functionality. Whereas, Invensense, ICM42370P
+ * has only accelerometer.
+ */
st->indio_accel = inv_icm42607_accel_init(st);
if (IS_ERR(st->indio_accel))
return PTR_ERR(st->indio_accel);
diff --git a/drivers/iio/imu/inv_icm42607/inv_icm42607_i2c.c b/drivers/iio/imu/inv_icm42607/inv_icm42607_i2c.c
index e903106af84a8..9f34199ce2949 100644
--- a/drivers/iio/imu/inv_icm42607/inv_icm42607_i2c.c
+++ b/drivers/iio/imu/inv_icm42607/inv_icm42607_i2c.c
@@ -58,6 +58,9 @@ static int inv_icm42607_probe(struct i2c_client *client)
static const struct i2c_device_id inv_icm42607_id[] = {
{
+ .name = "icm42370p",
+ .driver_data = (kernel_ulong_t)&inv_icm42370p_hw_data,
+ }, {
.name = "icm42607",
.driver_data = (kernel_ulong_t)&inv_icm42607_hw_data,
}, {
@@ -70,6 +73,9 @@ MODULE_DEVICE_TABLE(i2c, inv_icm42607_id);
static const struct of_device_id inv_icm42607_of_matches[] = {
{
+ .compatible = "invensense,icm42370p",
+ .data = &inv_icm42370p_hw_data,
+ }, {
.compatible = "invensense,icm42607",
.data = &inv_icm42607_hw_data,
}, {
--
2.43.0
^ permalink raw reply [flat|nested] 7+ messages in thread* [PATCH v6 5/6] iio: imu: inv_icm42607: Implement MREGx register access
2026-10-09 14:12 [PATCH v6 0/6] Add support for InvenSense ICM-42370-P accelerometer Kanak Shilledar
` (3 preceding siblings ...)
2026-10-09 14:12 ` [PATCH v6 4/6] iio: imu: inv_icm42607: Add support for ICM-42370-P Kanak Shilledar
@ 2026-10-09 14:12 ` Kanak Shilledar
2026-10-09 14:12 ` [PATCH v6 6/6] iio: imu: inv_icm42607: Add accelerometer calibbias support Kanak Shilledar
5 siblings, 0 replies; 7+ messages in thread
From: Kanak Shilledar @ 2026-10-09 14:12 UTC (permalink / raw)
To: Henrik Grimler, Jonathan Cameron, David Lechner, Nuno Sá,
Andy Shevchenko, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Jean-Baptiste Maneyrol, Joshua Crofts, Marcelo Schmitt,
Chris Morgan
Cc: Kanak Shilledar, kernel, linux-iio, devicetree, linux-kernel
The device supports indirect register access to different banks. A
specific routine needs to be followed when accessing the registers in
another bank as documented in the datasheet (section 13). This is
required for accessing registers configured via the user and
implementing buffer support. The implementation is inspired from the
icm45600 driver.
The banks are defined based on their initial bank access code which are
written to the BLK_SEL_* regs. However, there is a variation for MREG1
as User Bank 0 and MREG1 both share the same 0x00, so User Bank 1 has
0x00 and MREG1 has 0x01. When MREG1 register is accessed, then BLK_SEL_*
is written with 0x00 instead of 0x01. All the register access goes
through the 16 bit virtual regmap layered on top of the 8bit bus regmap.
Bank id in the upper byte and the register address in the lower byte.
Bank 0 accesses are forwarded to the bus regmap with the bank field
stripped, while MREG accesses are forwarded to bank switching sequence.
Due to the specific bank switching routine, it is not possible to use
regmap-ranges. Only User Bank 0 supports bulk read/writes whereas other
banks can only be accessed serially. Each time some data in the other
bank needs to be accessed, it should go through the complete bank
switching sequence.
Datasheet: https://www.invensense.tdk.com/en-us/products/3-axis/icm-42370-p
Datasheet: https://www.lcsc.com/product-detail/C5129967.html
Assisted-by: LLM
Signed-off-by: Kanak Shilledar <kanak.shilledar@axis.com>
---
LLM was used to implement the mreg back switching support.
---
drivers/iio/imu/inv_icm42607/inv_icm42607.h | 166 ++++++++++------
drivers/iio/imu/inv_icm42607/inv_icm42607_core.c | 241 +++++++++++++++++++++--
drivers/iio/imu/inv_icm42607/inv_icm42607_i2c.c | 6 +
3 files changed, 333 insertions(+), 80 deletions(-)
diff --git a/drivers/iio/imu/inv_icm42607/inv_icm42607.h b/drivers/iio/imu/inv_icm42607/inv_icm42607.h
index 674a9896fabb3..eecf4c46cbdb0 100644
--- a/drivers/iio/imu/inv_icm42607/inv_icm42607.h
+++ b/drivers/iio/imu/inv_icm42607/inv_icm42607.h
@@ -167,31 +167,59 @@ struct inv_icm42607_sensor_state {
int filter;
};
-/* Virtual register addresses: @bank on MSB (4 upper bits), @address on LSB */
+/*
+ * Virtual register addresses: bank id in the upper byte, register address in
+ * the lower byte. Bank 0 is directly addressable on the bus. MREG banks are
+ * reached through the BLK_SEL/MADDR/M indirect access window, one byte per
+ * transaction (datasheet section 13, no burst support).
+ *
+ * MREG1 programs BLK_SEL = 0x00, which collides with the direct bank, so it
+ * gets the distinct virtual id 0x01. MREG2 and MREG3 virtual ids match their
+ * BLK_SEL values.
+ */
+#define INV_ICM42607_REG_BANK_MASK GENMASK(15, 8)
+#define INV_ICM42607_REG_ADDR_MASK GENMASK(7, 0)
+
+#define INV_ICM42607_BANK0 0x00
+#define INV_ICM42607_MREG1 0x01
+#define INV_ICM42607_MREG2 0x28
+#define INV_ICM42607_MREG3 0x50
+
+/* BLK_SEL value written to the device for each virtual bank id. */
+#define INV_ICM42607_MREG1_BLK_SEL 0x00
+#define INV_ICM42607_MREG2_BLK_SEL 0x28
+#define INV_ICM42607_MREG3_BLK_SEL 0x50
+
+/*
+ * Datasheet section 13, Accessing MREGx Registers: no bus access for 10us
+ * after programming the indirect access window.
+ */
+#define INV_ICM42607_MREG_ACCESS_DELAY_US 10
/* Register Map for User Bank 0 */
-#define INV_ICM42607_REG_MCLK_RDY 0x00
+#define INV_ICM42607_REG_MCLK_RDY 0x0000
+#define INV_ICM42607_MCLK_RDY_BIT BIT(3)
-#define INV_ICM42607_REG_DEVICE_CONFIG 0x01
+#define INV_ICM42607_REG_DEVICE_CONFIG 0x0001
#define INV_ICM42607_DEVICE_CONFIG_SPI_AP_4WIRE BIT(2)
#define INV_ICM42607_DEVICE_CONFIG_SPI_MODE BIT(0)
-#define INV_ICM42607_REG_SIGNAL_PATH_RESET 0x02
+#define INV_ICM42607_REG_SIGNAL_PATH_RESET 0x0002
#define INV_ICM42607_SIGNAL_PATH_RESET_SOFT_RESET BIT(4)
#define INV_ICM42607_SIGNAL_PATH_RESET_FIFO_FLUSH BIT(2)
-#define INV_ICM42607_REG_DRIVE_CONFIG1 0x03
+#define INV_ICM42607_REG_DRIVE_CONFIG1 0x0003
#define INV_ICM42607_DRIVE_CONFIG1_I3C_DDR_MASK GENMASK(5, 3)
#define INV_ICM42607_DRIVE_CONFIG1_I3C_SDR_MASK GENMASK(2, 0)
-#define INV_ICM42607_REG_DRIVE_CONFIG2 0x04
+#define INV_ICM42607_REG_DRIVE_CONFIG2 0x0004
#define INV_ICM42607_DRIVE_CONFIG2_I2C_MASK GENMASK(5, 3)
#define INV_ICM42607_DRIVE_CONFIG2_ALL_MASK GENMASK(2, 0)
-#define INV_ICM42607_REG_DRIVE_CONFIG3 0x05
+#define INV_ICM42607_REG_DRIVE_CONFIG3 0x0005
#define INV_ICM42607_DRIVE_CONFIG3_SPI_MASK GENMASK(2, 0)
-#define INV_ICM42607_REG_INT_CONFIG 0x06
+#define INV_ICM42607_REG_INT_CONFIG 0x0006
#define INV_ICM42607_INT_CONFIG_INT2_LATCHED BIT(5)
#define INV_ICM42607_INT_CONFIG_INT2_PUSH_PULL BIT(4)
#define INV_ICM42607_INT_CONFIG_INT2_ACTIVE_HIGH BIT(3)
@@ -202,81 +230,81 @@ struct inv_icm42607_sensor_state {
#define INV_ICM42607_INT_CONFIG_INT1_ACTIVE_LOW 0x00
/* all sensor data are 16 bits (2 registers wide) in big-endian */
-#define INV_ICM42607_REG_TEMP_DATA1 0x09
-#define INV_ICM42607_REG_TEMP_DATA0 0x0A
-#define INV_ICM42607_REG_ACCEL_DATA_X1 0x0B
-#define INV_ICM42607_REG_ACCEL_DATA_X0 0x0C
-#define INV_ICM42607_REG_ACCEL_DATA_Y1 0x0D
-#define INV_ICM42607_REG_ACCEL_DATA_Y0 0x0E
-#define INV_ICM42607_REG_ACCEL_DATA_Z1 0x0F
-#define INV_ICM42607_REG_ACCEL_DATA_Z0 0x10
-#define INV_ICM42607_REG_GYRO_DATA_X1 0x11
-#define INV_ICM42607_REG_GYRO_DATA_X0 0x12
-#define INV_ICM42607_REG_GYRO_DATA_Y1 0x13
-#define INV_ICM42607_REG_GYRO_DATA_Y0 0x14
-#define INV_ICM42607_REG_GYRO_DATA_Z1 0x15
-#define INV_ICM42607_REG_GYRO_DATA_Z0 0x16
+#define INV_ICM42607_REG_TEMP_DATA1 0x0009
+#define INV_ICM42607_REG_TEMP_DATA0 0x000A
+#define INV_ICM42607_REG_ACCEL_DATA_X1 0x000B
+#define INV_ICM42607_REG_ACCEL_DATA_X0 0x000C
+#define INV_ICM42607_REG_ACCEL_DATA_Y1 0x000D
+#define INV_ICM42607_REG_ACCEL_DATA_Y0 0x000E
+#define INV_ICM42607_REG_ACCEL_DATA_Z1 0x000F
+#define INV_ICM42607_REG_ACCEL_DATA_Z0 0x0010
+#define INV_ICM42607_REG_GYRO_DATA_X1 0x0011
+#define INV_ICM42607_REG_GYRO_DATA_X0 0x0012
+#define INV_ICM42607_REG_GYRO_DATA_Y1 0x0013
+#define INV_ICM42607_REG_GYRO_DATA_Y0 0x0014
+#define INV_ICM42607_REG_GYRO_DATA_Z1 0x0015
+#define INV_ICM42607_REG_GYRO_DATA_Z0 0x0016
#define INV_ICM42607_DATA_INVALID -32768
-#define INV_ICM42607_REG_TMST_FSYNCH 0x17
-#define INV_ICM42607_REG_TMST_FSYNCL 0x18
+#define INV_ICM42607_REG_TMST_FSYNCH 0x0017
+#define INV_ICM42607_REG_TMST_FSYNCL 0x0018
/* APEX Data Registers */
-#define INV_ICM42607_REG_APEX_DATA0 0x31
-#define INV_ICM42607_REG_APEX_DATA1 0x32
-#define INV_ICM42607_REG_APEX_DATA2 0x33
-#define INV_ICM42607_REG_APEX_DATA3 0x34
-#define INV_ICM42607_REG_APEX_DATA4 0x1D
-#define INV_ICM42607_REG_APEX_DATA5 0x1E
-
-#define INV_ICM42607_REG_PWR_MGMT0 0x1F
+#define INV_ICM42607_REG_APEX_DATA0 0x0031
+#define INV_ICM42607_REG_APEX_DATA1 0x0032
+#define INV_ICM42607_REG_APEX_DATA2 0x0033
+#define INV_ICM42607_REG_APEX_DATA3 0x0034
+#define INV_ICM42607_REG_APEX_DATA4 0x001D
+#define INV_ICM42607_REG_APEX_DATA5 0x001E
+
+#define INV_ICM42607_REG_PWR_MGMT0 0x001F
#define INV_ICM42607_PWR_MGMT0_ACCEL_LP_CLK_SEL BIT(7)
#define INV_ICM42607_PWR_MGMT0_IDLE BIT(4)
#define INV_ICM42607_PWR_MGMT0_GYRO_MODE_MASK GENMASK(3, 2)
#define INV_ICM42607_PWR_MGMT0_ACCEL_MODE_MASK GENMASK(1, 0)
-#define INV_ICM42607_REG_GYRO_CONFIG0 0x20
+#define INV_ICM42607_REG_GYRO_CONFIG0 0x0020
#define INV_ICM42607_GYRO_CONFIG0_FS_SEL_MASK GENMASK(6, 5)
#define INV_ICM42607_GYRO_CONFIG0_ODR_MASK GENMASK(3, 0)
-#define INV_ICM42607_REG_ACCEL_CONFIG0 0x21
+#define INV_ICM42607_REG_ACCEL_CONFIG0 0x0021
#define INV_ICM42607_ACCEL_CONFIG0_FS_SEL_MASK GENMASK(6, 5)
#define INV_ICM42607_ACCEL_CONFIG0_ODR_MASK GENMASK(3, 0)
-#define INV_ICM42607_REG_TEMP_CONFIG0 0x22
+#define INV_ICM42607_REG_TEMP_CONFIG0 0x0022
#define INV_ICM42607_TEMP_CONFIG0_FILTER_MASK GENMASK(6, 4)
-#define INV_ICM42607_REG_GYRO_CONFIG1 0x23
+#define INV_ICM42607_REG_GYRO_CONFIG1 0x0023
#define INV_ICM42607_GYRO_CONFIG1_FILTER_MASK GENMASK(2, 0)
-#define INV_ICM42607_REG_ACCEL_CONFIG1 0x24
+#define INV_ICM42607_REG_ACCEL_CONFIG1 0x0024
#define INV_ICM42607_ACCEL_CONFIG1_AVG_MASK GENMASK(6, 4)
#define INV_ICM42607_ACCEL_CONFIG1_FILTER_MASK GENMASK(2, 0)
-#define INV_ICM42607_REG_APEX_CONFIG0 0x25
+#define INV_ICM42607_REG_APEX_CONFIG0 0x0025
#define INV_ICM42607_APEX_CONFIG0_DMP_POWER_SAVE_EN BIT(3)
#define INV_ICM42607_APEX_CONFIG0_DMP_INIT_EN BIT(2)
#define INV_ICM42607_APEX_CONFIG0_DMP_MEM_RESET_EN BIT(0)
-#define INV_ICM42607_REG_APEX_CONFIG1 0x26
+#define INV_ICM42607_REG_APEX_CONFIG1 0x0026
#define INV_ICM42607_APEX_CONFIG1_SMD_ENABLE BIT(6)
#define INV_ICM42607_APEX_CONFIG1_FF_ENABLE BIT(5)
#define INV_ICM42607_APEX_CONFIG1_TILT_ENABLE BIT(4)
#define INV_ICM42607_APEX_CONFIG1_PED_ENABLE BIT(3)
#define INV_ICM42607_APEX_CONFIG1_DMP_ODR_MASK GENMASK(1, 0)
-#define INV_ICM42607_REG_WOM_CONFIG 0x27
+#define INV_ICM42607_REG_WOM_CONFIG 0x0027
#define INV_ICM42607_WOM_CONFIG_INT_DUR_MASK GENMASK(4, 3)
#define INV_ICM42607_WOM_CONFIG_INT_MODE BIT(2)
#define INV_ICM42607_WOM_CONFIG_MODE BIT(1)
#define INV_ICM42607_WOM_CONFIG_EN BIT(0)
-#define INV_ICM42607_REG_FIFO_CONFIG1 0x28
+#define INV_ICM42607_REG_FIFO_CONFIG1 0x0028
#define INV_ICM42607_FIFO_CONFIG1_MODE BIT(1)
#define INV_ICM42607_FIFO_CONFIG1_BYPASS BIT(0)
-#define INV_ICM42607_REG_FIFO_CONFIG2 0x29
-#define INV_ICM42607_REG_FIFO_CONFIG3 0x2A
+#define INV_ICM42607_REG_FIFO_CONFIG2 0x0029
+#define INV_ICM42607_REG_FIFO_CONFIG3 0x002A
#define INV_ICM42607_FIFO_WATERMARK_VAL(_wm) \
cpu_to_le16((_wm) & GENMASK(11, 0))
/* FIFO is 2048 bytes, let 12 samples for reading latency */
@@ -284,7 +312,7 @@ struct inv_icm42607_sensor_state {
#define INV_ICM42607_FIFO_1SENSOR_PACKET_SIZE 8
#define INV_ICM42607_FIFO_2SENSORS_PACKET_SIZE 16
-#define INV_ICM42607_REG_INT_SOURCE0 0x2B
+#define INV_ICM42607_REG_INT_SOURCE0 0x002B
#define INV_ICM42607_INT_SOURCE0_ST_INT1_EN BIT(7)
#define INV_ICM42607_INT_SOURCE0_FSYNC_INT1_EN BIT(6)
#define INV_ICM42607_INT_SOURCE0_PLL_RDY_INT1_EN BIT(5)
@@ -294,12 +322,12 @@ struct inv_icm42607_sensor_state {
#define INV_ICM42607_INT_SOURCE0_FIFO_FULL_INT1_EN BIT(1)
#define INV_ICM42607_INT_SOURCE0_AGC_RDY_INT1_EN BIT(0)
-#define INV_ICM42607_REG_INT_SOURCE1 0x2C
+#define INV_ICM42607_REG_INT_SOURCE1 0x002C
#define INV_ICM42607_INT_SOURCE1_I3C_ERROR_INT1_EN BIT(6)
#define INV_ICM42607_INT_SOURCE1_SMD_INT1_EN BIT(3)
#define INV_ICM42607_INT_SOURCE1_WOM_INT1_EN GENMASK(2, 0)
-#define INV_ICM42607_REG_INT_SOURCE3 0x2D
+#define INV_ICM42607_REG_INT_SOURCE3 0x002D
#define INV_ICM42607_INT_SOURCE3_ST_INT2_EN BIT(7)
#define INV_ICM42607_INT_SOURCE3_FSYNC_INT2_EN BIT(6)
#define INV_ICM42607_INT_SOURCE3_PLL_RDY_INT2_EN BIT(5)
@@ -309,17 +337,17 @@ struct inv_icm42607_sensor_state {
#define INV_ICM42607_INT_SOURCE3_FIFO_FULL_INT2_EN BIT(1)
#define INV_ICM42607_INT_SOURCE3_AGC_RDY_INT2_EN BIT(0)
-#define INV_ICM42607_REG_INT_SOURCE4 0x2E
+#define INV_ICM42607_REG_INT_SOURCE4 0x002E
#define INV_ICM42607_INT_SOURCE4_I3C_ERROR_INT2_EN BIT(6)
#define INV_ICM42607_INT_SOURCE4_SMD_INT2_EN BIT(3)
#define INV_ICM42607_INT_SOURCE4_WOM_Z_INT2_EN BIT(2)
#define INV_ICM42607_INT_SOURCE4_WOM_Y_INT2_EN BIT(1)
#define INV_ICM42607_INT_SOURCE4_WOM_X_INT2_EN BIT(0)
-#define INV_ICM42607_REG_FIFO_LOST_PKT0 0x2F
-#define INV_ICM42607_REG_FIFO_LOST_PKT1 0x30
+#define INV_ICM42607_REG_FIFO_LOST_PKT0 0x002F
+#define INV_ICM42607_REG_FIFO_LOST_PKT1 0x0030
-#define INV_ICM42607_REG_INTF_CONFIG0 0x35
+#define INV_ICM42607_REG_INTF_CONFIG0 0x0035
#define INV_ICM42607_INTF_CONFIG0_FIFO_COUNT_FORMAT BIT(6)
#define INV_ICM42607_INTF_CONFIG0_FIFO_COUNT_ENDIAN BIT(5)
#define INV_ICM42607_INTF_CONFIG0_SENSOR_DATA_ENDIAN BIT(4)
@@ -327,7 +355,7 @@ struct inv_icm42607_sensor_state {
#define INV_ICM42607_INTF_CONFIG0_UI_SIFS_CFG_SPI_DIS 2
#define INV_ICM42607_INTF_CONFIG0_UI_SIFS_CFG_I2C_DIS 3
-#define INV_ICM42607_REG_INTF_CONFIG1 0x36
+#define INV_ICM42607_REG_INTF_CONFIG1 0x0036
#define INV_ICM42607_INTF_CONFIG1_I3C_SDR_EN BIT(3)
#define INV_ICM42607_INTF_CONFIG1_I3C_DDR_EN BIT(2)
#define INV_ICM42607_INTF_CONFIG1_CLKSEL_MASK GENMASK(1, 0)
@@ -335,10 +363,10 @@ struct inv_icm42607_sensor_state {
#define INV_ICM42607_INTF_CONFIG1_CLKSEL_PLL 1
#define INV_ICM42607_INTF_CONFIG1_CLKSEL_OFF 2
-#define INV_ICM42607_REG_INT_STATUS_DRDY 0x39
+#define INV_ICM42607_REG_INT_STATUS_DRDY 0x0039
#define INV_ICM42607_INT_STATUS_DRDY_DATA_RDY BIT(0)
-#define INV_ICM42607_REG_INT_STATUS 0x3A
+#define INV_ICM42607_REG_INT_STATUS 0x003A
#define INV_ICM42607_INT_STATUS_ST BIT(7)
#define INV_ICM42607_INT_STATUS_FSYNC BIT(6)
#define INV_ICM42607_INT_STATUS_PLL_RDY BIT(5)
@@ -347,11 +375,11 @@ struct inv_icm42607_sensor_state {
#define INV_ICM42607_INT_STATUS_FIFO_FULL BIT(1)
#define INV_ICM42607_INT_STATUS_AGC_RDY BIT(0)
-#define INV_ICM42607_REG_INT_STATUS2 0x3B
+#define INV_ICM42607_REG_INT_STATUS2 0x003B
#define INV_ICM42607_INT_STATUS2_SMD BIT(3)
#define INV_ICM42607_INT_STATUS2_WOM_INT GENMASK(2, 0)
-#define INV_ICM42607_REG_INT_STATUS3 0x3C
+#define INV_ICM42607_REG_INT_STATUS3 0x003C
#define INV_ICM42607_INT_STATUS3_STEP_DET BIT(5)
#define INV_ICM42607_INT_STATUS3_STEP_CNT_OVF BIT(4)
#define INV_ICM42607_INT_STATUS3_TILT_DET BIT(3)
@@ -362,15 +390,35 @@ struct inv_icm42607_sensor_state {
* FIFO count is 16 bits (2 registers) big-endian
* FIFO data is a continuous read register to read FIFO content
*/
-#define INV_ICM42607_REG_FIFO_COUNTH 0x3D
-#define INV_ICM42607_REG_FIFO_COUNTL 0x3E
-#define INV_ICM42607_REG_FIFO_DATA 0x3F
+#define INV_ICM42607_REG_FIFO_COUNTH 0x003D
+#define INV_ICM42607_REG_FIFO_COUNTL 0x003E
+#define INV_ICM42607_REG_FIFO_DATA 0x003F
-#define INV_ICM42607_REG_WHOAMI 0x75
+#define INV_ICM42607_REG_WHOAMI 0x0075
#define INV_ICM42370P_WHOAMI 0x0D
#define INV_ICM42607P_WHOAMI 0x60
#define INV_ICM42607_WHOAMI 0x67
+#define INV_ICM42607_REG_BLK_SEL_W 0x0079
+#define INV_ICM42607_REG_MADDR_W 0x007A
+#define INV_ICM42607_REG_M_W 0x007B
+#define INV_ICM42607_REG_BLK_SEL_R 0x007C
+#define INV_ICM42607_REG_MADDR_R 0x007D
+#define INV_ICM42607_REG_M_R 0x007E
+
+/* User Bank MREG 1 registers */
+#define INV_ICM42607_REG_OFFSET_USER0 0x014E
+#define INV_ICM42607_REG_OFFSET_USER1 0x014F
+#define INV_ICM42607_REG_OFFSET_USER2 0x0150
+#define INV_ICM42607_REG_OFFSET_USER3 0x0151
+#define INV_ICM42607_REG_OFFSET_USER4 0x0152
+#define INV_ICM42607_REG_OFFSET_USER5 0x0153
+#define INV_ICM42607_REG_OFFSET_USER6 0x0154
+#define INV_ICM42607_REG_OFFSET_USER7 0x0155
+#define INV_ICM42607_REG_OFFSET_USER8 0x0156
+
+/* User Bank MREG 3 registers */
+#define INV_ICM42607_REG_ZG_ST_DATA 0x5005
/*
* Timings as listed in section 3 of datasheet, all values listed in datasheet
* in ms except temp startup time... setting all values in us and using
diff --git a/drivers/iio/imu/inv_icm42607/inv_icm42607_core.c b/drivers/iio/imu/inv_icm42607/inv_icm42607_core.c
index 75c9617e5d1e7..a4393b54cc108 100644
--- a/drivers/iio/imu/inv_icm42607/inv_icm42607_core.c
+++ b/drivers/iio/imu/inv_icm42607/inv_icm42607_core.c
@@ -18,63 +18,255 @@
#include <linux/time.h>
#include <linux/timekeeping.h>
#include <linux/types.h>
+#include <linux/unaligned.h>
#include <asm/byteorder.h>
#include "inv_icm42607.h"
-static bool inv_icm42607_is_readable_reg(struct device *dev, unsigned int reg)
+static int inv_icm42607_mclk_get(struct regmap *map, bool *idle_set)
{
- switch (reg) {
- case INV_ICM42607_REG_MCLK_RDY ... INV_ICM42607_REG_INT_CONFIG:
- case INV_ICM42607_REG_TEMP_DATA1 ... INV_ICM42607_REG_TMST_FSYNCL:
- case INV_ICM42607_REG_APEX_DATA4 ... INV_ICM42607_REG_INTF_CONFIG1:
- case INV_ICM42607_REG_INT_STATUS_DRDY ... INV_ICM42607_REG_FIFO_DATA:
- case INV_ICM42607_REG_WHOAMI:
- return true;
+ unsigned int val;
+ int ret, ret2;
+
+ *idle_set = false;
+
+ ret = regmap_test_bits(map, INV_ICM42607_REG_MCLK_RDY,
+ INV_ICM42607_MCLK_RDY_BIT);
+ if (ret < 0)
+ return ret;
+ if (ret)
+ return 0;
+
+ /*
+ * Clock isn't running: we're either in Sleep mode or in Accel LP mode
+ * running on WUOSC. Force the RC oscillator on via IDLE and wait for
+ * MCLK_RDY. Datasheet gives 10us (accel startup) to 200us (accel
+ * transition from OFF) for this to complete.
+ */
+ ret = regmap_set_bits(map, INV_ICM42607_REG_PWR_MGMT0,
+ INV_ICM42607_PWR_MGMT0_IDLE);
+ if (ret)
+ return ret;
+
+ *idle_set = true;
+
+ ret = regmap_read_poll_timeout(map, INV_ICM42607_REG_MCLK_RDY, val,
+ val & INV_ICM42607_MCLK_RDY_BIT, 10, 200);
+ if (ret) {
+ ret2 = regmap_clear_bits(map, INV_ICM42607_REG_PWR_MGMT0,
+ INV_ICM42607_PWR_MGMT0_IDLE);
+ if (ret2)
+ dev_dbg(regmap_get_device(map),
+ "failed to clear IDLE after MCLK timeout: %d\n", ret2);
+ else
+ *idle_set = false;
}
- return false;
+ return ret;
}
-static bool inv_icm42607_is_writeable_reg(struct device *dev, unsigned int reg)
+static void inv_icm42607_mclk_put(struct regmap *map, bool idle_set)
{
- switch (reg) {
- case INV_ICM42607_REG_DEVICE_CONFIG ... INV_ICM42607_REG_INT_CONFIG:
- case INV_ICM42607_REG_PWR_MGMT0 ... INV_ICM42607_REG_INT_SOURCE4:
- case INV_ICM42607_REG_INTF_CONFIG0 ... INV_ICM42607_REG_INTF_CONFIG1:
- return true;
+ if (!idle_set)
+ return;
+
+ regmap_clear_bits(map, INV_ICM42607_REG_PWR_MGMT0, INV_ICM42607_PWR_MGMT0_IDLE);
+}
+
+static int inv_icm42607_blk_sel(unsigned int reg, u8 *blk_sel)
+{
+ u8 bank = FIELD_GET(INV_ICM42607_REG_BANK_MASK, reg);
+
+ switch (bank) {
+ case INV_ICM42607_MREG1:
+ *blk_sel = INV_ICM42607_MREG1_BLK_SEL;
+ return 0;
+ case INV_ICM42607_MREG2:
+ case INV_ICM42607_MREG3:
+ *blk_sel = bank;
+ return 0;
+ default:
+ return -EINVAL;
}
+}
- return false;
+static int inv_icm42607_mreg_read(struct regmap *map, unsigned int reg,
+ u8 *data, size_t count)
+{
+ unsigned int val;
+ bool idle_set;
+ int ret, ret2;
+ u8 blk_sel;
+
+ /* MREG access is one byte per transaction, no burst support. */
+ if (count != 1)
+ return -EINVAL;
+
+ ret = inv_icm42607_blk_sel(reg, &blk_sel);
+ if (ret)
+ return ret;
+
+ ret = inv_icm42607_mclk_get(map, &idle_set);
+ if (ret)
+ return ret;
+
+ ret = regmap_write(map, INV_ICM42607_REG_BLK_SEL_R, blk_sel);
+ if (ret)
+ goto out;
+
+ ret = regmap_write(map, INV_ICM42607_REG_MADDR_R,
+ FIELD_GET(INV_ICM42607_REG_ADDR_MASK, reg));
+ if (ret)
+ goto out;
+
+ fsleep(INV_ICM42607_MREG_ACCESS_DELAY_US);
+
+ ret = regmap_read(map, INV_ICM42607_REG_M_R, &val);
+ if (ret)
+ goto out;
+
+ fsleep(INV_ICM42607_MREG_ACCESS_DELAY_US);
+
+ *data = val;
+out:
+ /* Restore direct access. */
+ ret2 = regmap_write(map, INV_ICM42607_REG_BLK_SEL_R, 0);
+ inv_icm42607_mclk_put(map, idle_set);
+
+ return ret ? ret : ret2;
+}
+
+static int inv_icm42607_mreg_write(struct regmap *map, unsigned int reg,
+ const u8 *data, size_t count)
+{
+ bool idle_set;
+ int ret, ret2;
+ u8 blk_sel;
+
+ /* MREG access is one byte per transaction, no burst support. */
+ if (count != 1)
+ return -EINVAL;
+
+ ret = inv_icm42607_blk_sel(reg, &blk_sel);
+ if (ret)
+ return ret;
+
+ ret = inv_icm42607_mclk_get(map, &idle_set);
+ if (ret)
+ return ret;
+
+ ret = regmap_write(map, INV_ICM42607_REG_BLK_SEL_W, blk_sel);
+ if (ret)
+ goto out;
+
+ ret = regmap_write(map, INV_ICM42607_REG_MADDR_W,
+ FIELD_GET(INV_ICM42607_REG_ADDR_MASK, reg));
+ if (ret)
+ goto out;
+
+ ret = regmap_write(map, INV_ICM42607_REG_M_W, *data);
+ if (ret)
+ goto out;
+
+ fsleep(INV_ICM42607_MREG_ACCESS_DELAY_US);
+
+out:
+ /* Restore direct access. */
+ ret2 = regmap_write(map, INV_ICM42607_REG_BLK_SEL_W, 0);
+ inv_icm42607_mclk_put(map, idle_set);
+
+ return ret ? ret : ret2;
+}
+
+static int inv_icm42607_read(void *context, const void *reg_buf, size_t reg_size,
+ void *val_buf, size_t val_size)
+{
+ u16 reg = get_unaligned_be16(reg_buf);
+ struct regmap *map = context;
+
+ if (FIELD_GET(INV_ICM42607_REG_BANK_MASK, reg) != INV_ICM42607_BANK0)
+ return inv_icm42607_mreg_read(map, reg, val_buf, val_size);
+
+ return regmap_bulk_read(map, FIELD_GET(INV_ICM42607_REG_ADDR_MASK, reg),
+ val_buf, val_size);
+}
+
+static int inv_icm42607_write(void *context, const void *data, size_t count)
+{
+ unsigned int reg = get_unaligned_be16(data);
+ struct regmap *map = context;
+ const u8 *d = data;
+
+ if (FIELD_GET(INV_ICM42607_REG_BANK_MASK, reg) != INV_ICM42607_BANK0)
+ return inv_icm42607_mreg_write(map, reg, d + 2, count - 2);
+
+ return regmap_bulk_write(map, FIELD_GET(INV_ICM42607_REG_ADDR_MASK, reg),
+ d + 2, count - 2);
}
+static const struct regmap_bus inv_icm42607_regmap_bus = {
+ .read = inv_icm42607_read,
+ .write = inv_icm42607_write,
+};
+
static bool inv_icm42607_is_volatile_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case INV_ICM42607_REG_MCLK_RDY:
case INV_ICM42607_REG_SIGNAL_PATH_RESET:
case INV_ICM42607_REG_TEMP_DATA1 ... INV_ICM42607_REG_APEX_DATA5:
+ /* PWR_MGMT0 IDLE bit is toggled behind the cache during MREG access. */
+ case INV_ICM42607_REG_PWR_MGMT0:
case INV_ICM42607_REG_APEX_CONFIG0:
case INV_ICM42607_REG_FIFO_LOST_PKT0 ... INV_ICM42607_REG_APEX_DATA3:
case INV_ICM42607_REG_INT_STATUS_DRDY:
case INV_ICM42607_REG_INT_STATUS ... INV_ICM42607_REG_FIFO_DATA:
+ case INV_ICM42607_REG_BLK_SEL_W ... INV_ICM42607_REG_M_R:
+ return true;
+ }
+
+ return false;
+}
+
+static bool inv_icm42607_is_readable_reg(struct device *dev, unsigned int reg)
+{
+ switch (reg) {
+ case INV_ICM42607_REG_MCLK_RDY ... INV_ICM42607_REG_INT_CONFIG:
+ case INV_ICM42607_REG_TEMP_DATA1 ... INV_ICM42607_REG_TMST_FSYNCL:
+ case INV_ICM42607_REG_APEX_DATA4 ... INV_ICM42607_REG_INTF_CONFIG1:
+ case INV_ICM42607_REG_INT_STATUS_DRDY ... INV_ICM42607_REG_FIFO_DATA:
+ case INV_ICM42607_REG_WHOAMI:
+ case INV_ICM42607_REG_OFFSET_USER0 ... INV_ICM42607_REG_OFFSET_USER8:
return true;
}
return false;
}
-const struct regmap_config inv_icm42607_regmap_config = {
- .reg_bits = 8,
+static bool inv_icm42607_is_writeable_reg(struct device *dev, unsigned int reg)
+{
+ switch (reg) {
+ case INV_ICM42607_REG_DEVICE_CONFIG ... INV_ICM42607_REG_INT_CONFIG:
+ case INV_ICM42607_REG_PWR_MGMT0 ... INV_ICM42607_REG_INT_SOURCE4:
+ case INV_ICM42607_REG_INTF_CONFIG0 ... INV_ICM42607_REG_INTF_CONFIG1:
+ case INV_ICM42607_REG_OFFSET_USER0 ... INV_ICM42607_REG_OFFSET_USER8:
+ return true;
+ }
+
+ return false;
+}
+
+static const struct regmap_config inv_icm42607_virt_regmap_config = {
+ .name = "banks",
+ .reg_bits = 16,
.val_bits = 8,
.writeable_reg = inv_icm42607_is_writeable_reg,
.readable_reg = inv_icm42607_is_readable_reg,
.volatile_reg = inv_icm42607_is_volatile_reg,
- .max_register = INV_ICM42607_REG_WHOAMI,
+ .max_register = INV_ICM42607_REG_ZG_ST_DATA,
.cache_type = REGCACHE_MAPLE,
};
-EXPORT_SYMBOL_NS_GPL(inv_icm42607_regmap_config, "IIO_ICM42607");
/* chip initial default configuration */
static const struct inv_icm42607_conf inv_icm42370_default_conf = {
@@ -606,8 +798,15 @@ int inv_icm42607_core_probe(struct regmap *regmap,
{
struct device *dev = regmap_get_device(regmap);
struct inv_icm42607_state *st;
+ struct regmap *regmap_custom;
int ret;
+ regmap_custom = devm_regmap_init(dev, &inv_icm42607_regmap_bus, regmap,
+ &inv_icm42607_virt_regmap_config);
+ if (IS_ERR(regmap_custom))
+ return dev_err_probe(dev, PTR_ERR(regmap_custom),
+ "Failed to register regmap\n");
+
st = devm_kzalloc(dev, sizeof(*st), GFP_KERNEL);
if (!st)
return -ENOMEM;
@@ -619,7 +818,7 @@ int inv_icm42607_core_probe(struct regmap *regmap,
return ret;
st->hw = hw;
- st->map = regmap;
+ st->map = regmap_custom;
ret = iio_read_mount_matrix(dev, &st->orientation);
if (ret)
diff --git a/drivers/iio/imu/inv_icm42607/inv_icm42607_i2c.c b/drivers/iio/imu/inv_icm42607/inv_icm42607_i2c.c
index 9f34199ce2949..61705b162f86f 100644
--- a/drivers/iio/imu/inv_icm42607/inv_icm42607_i2c.c
+++ b/drivers/iio/imu/inv_icm42607/inv_icm42607_i2c.c
@@ -12,6 +12,12 @@
#include "inv_icm42607.h"
+const struct regmap_config inv_icm42607_regmap_config = {
+ .reg_bits = 8,
+ .val_bits = 8,
+};
+EXPORT_SYMBOL_NS_GPL(inv_icm42607_regmap_config, "IIO_ICM42607");
+
static int inv_icm42607_i2c_bus_setup(struct inv_icm42607_state *st)
{
unsigned int val;
--
2.43.0
^ permalink raw reply [flat|nested] 7+ messages in thread* [PATCH v6 6/6] iio: imu: inv_icm42607: Add accelerometer calibbias support
2026-10-09 14:12 [PATCH v6 0/6] Add support for InvenSense ICM-42370-P accelerometer Kanak Shilledar
` (4 preceding siblings ...)
2026-10-09 14:12 ` [PATCH v6 5/6] iio: imu: inv_icm42607: Implement MREGx register access Kanak Shilledar
@ 2026-10-09 14:12 ` Kanak Shilledar
5 siblings, 0 replies; 7+ messages in thread
From: Kanak Shilledar @ 2026-10-09 14:12 UTC (permalink / raw)
To: Henrik Grimler, Jonathan Cameron, David Lechner, Nuno Sá,
Andy Shevchenko, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Jean-Baptiste Maneyrol, Joshua Crofts, Marcelo Schmitt,
Chris Morgan
Cc: Kanak Shilledar, kernel, linux-iio, devicetree, linux-kernel
Expose IIO_CHAN_INFO_CALIBBIAS on the accelerometer channels. The
registers are stored in MREG1. The calibration bias is written to
OFFSET_USER4 to OFFSET_USER8 registers in MREG1. Reject the out of
limit calibbias values instead of clamping it.
Datasheet: https://www.invensense.tdk.com/en-us/products/3-axis/icm-42370-p
Datasheet: https://www.lcsc.com/product-detail/C5129967.html
Signed-off-by: Kanak Shilledar <kanak.shilledar@axis.com>
---
Note: The accelerometer functionality is tested with Invensense,
ICM42370-P development board.
---
drivers/iio/imu/inv_icm42607/inv_icm42607.h | 8 +
drivers/iio/imu/inv_icm42607/inv_icm42607_accel.c | 189 +++++++++++++++++++++-
2 files changed, 195 insertions(+), 2 deletions(-)
diff --git a/drivers/iio/imu/inv_icm42607/inv_icm42607.h b/drivers/iio/imu/inv_icm42607/inv_icm42607.h
index eecf4c46cbdb0..f4b46597a2bc5 100644
--- a/drivers/iio/imu/inv_icm42607/inv_icm42607.h
+++ b/drivers/iio/imu/inv_icm42607/inv_icm42607.h
@@ -437,6 +437,14 @@ struct inv_icm42607_sensor_state {
*/
#define INV_ICM42607_SUSPEND_DELAY_MS (2 * MSEC_PER_SEC)
+/* OFFSET_USERx shared registers two 4-bit MSB fields */
+#define INV_ICM42607_OFFSET_USER_NIBBLE_HI GENMASK(7, 4)
+#define INV_ICM42607_OFFSET_USER_NIBBLE_LO GENMASK(3, 0)
+
+/* 12-bit signed offset value split across two registers */
+#define INV_ICM42607_OFFSET_MSB GENMASK(11, 8)
+#define INV_ICM42607_OFFSET_LSB GENMASK(7, 0)
+
typedef int (*inv_icm42607_bus_setup)(struct inv_icm42607_state *);
extern const struct regmap_config inv_icm42607_regmap_config;
diff --git a/drivers/iio/imu/inv_icm42607/inv_icm42607_accel.c b/drivers/iio/imu/inv_icm42607/inv_icm42607_accel.c
index 9a3ace3e7fcf9..fb7ede65d9acd 100644
--- a/drivers/iio/imu/inv_icm42607/inv_icm42607_accel.c
+++ b/drivers/iio/imu/inv_icm42607/inv_icm42607_accel.c
@@ -5,6 +5,7 @@
#include <linux/array_size.h>
#include <linux/bits.h>
+#include <linux/bitfield.h>
#include <linux/cleanup.h>
#include <linux/device/devres.h>
#include <linux/err.h>
@@ -13,6 +14,7 @@
#include <linux/pm_runtime.h>
#include <linux/regmap.h>
#include <linux/types.h>
+#include <linux/units.h>
#include "inv_icm42607.h"
#include "inv_icm42607_temp.h"
@@ -22,9 +24,11 @@
.type = IIO_ACCEL, \
.modified = 1, \
.channel2 = _modifier, \
- .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
+ .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
+ BIT(IIO_CHAN_INFO_CALIBBIAS), \
.info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
- .info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_SCALE), \
+ .info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_SCALE) | \
+ BIT(IIO_CHAN_INFO_CALIBBIAS), \
.info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
.info_mask_shared_by_all_available = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
.scan_index = _index, \
@@ -56,6 +60,16 @@ static const struct iio_chan_spec inv_icm42607_accel_channels[] = {
INV_ICM42607_TEMP_CHAN(INV_ICM42607_ACCEL_SCAN_TEMP),
};
+/*
+ * Calibration bias values, IIO range format int + micro.
+ * Value is limited to +/-1g coded on 12 bits signed. Step is 0.5mg.
+ */
+static const int inv_icm42607_accel_calibbias[] = {
+ -10, 42010, /* Min : -2^11 * 0.0005 * 9.80665 = -10.042010 m/s² */
+ 0, 4903, /* Step: 0.0005 * 9.80665 = 0.004903 m/s² */
+ 10, 37106, /* Max : (2^11 - 1) * 0.0005 * 9.80665 = 10.037106 m/s² */
+};
+
static const int inv_icm42607_accel_scale_nano[][2] = {
[INV_ICM42607_ACCEL_FS_16G] = { 0, 4788403 },
[INV_ICM42607_ACCEL_FS_8G] = { 0, 2394202 },
@@ -176,6 +190,166 @@ static int inv_icm42607_accel_write_odr(struct iio_dev *indio_dev,
return inv_icm42607_set_sensor_conf(st, &conf, IIO_ACCEL);
}
+static int inv_icm42607_accel_read_offset(struct inv_icm42607_state *st,
+ struct iio_chan_spec const *chan, int *val, int *val2)
+{
+ struct device *dev = regmap_get_device(st->map);
+ unsigned int msb_reg, lsb_reg, nib, byte;
+ int offset;
+ s64 val64;
+ s32 bias;
+ int ret;
+ u32 raw;
+
+ if (chan->type != IIO_ACCEL)
+ return -EINVAL;
+
+ switch (chan->channel2) {
+ case IIO_MOD_X:
+ msb_reg = INV_ICM42607_REG_OFFSET_USER4;
+ lsb_reg = INV_ICM42607_REG_OFFSET_USER5;
+ break;
+ case IIO_MOD_Y:
+ msb_reg = INV_ICM42607_REG_OFFSET_USER7;
+ lsb_reg = INV_ICM42607_REG_OFFSET_USER6;
+ break;
+ case IIO_MOD_Z:
+ msb_reg = INV_ICM42607_REG_OFFSET_USER7;
+ lsb_reg = INV_ICM42607_REG_OFFSET_USER8;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ PM_RUNTIME_ACQUIRE_AUTOSUSPEND(dev, pm);
+ ret = PM_RUNTIME_ACQUIRE_ERR(&pm);
+ if (ret)
+ return ret;
+
+ guard(mutex)(&st->lock);
+
+ ret = regmap_read(st->map, msb_reg, &nib);
+ if (ret)
+ return ret;
+
+ ret = regmap_read(st->map, lsb_reg, &byte);
+ if (ret)
+ return ret;
+
+ /* 12 bits signed value */
+ if (chan->channel2 == IIO_MOD_Y)
+ raw = FIELD_PREP(INV_ICM42607_OFFSET_MSB,
+ FIELD_GET(INV_ICM42607_OFFSET_USER_NIBBLE_LO, nib));
+ else
+ raw = FIELD_PREP(INV_ICM42607_OFFSET_MSB,
+ FIELD_GET(INV_ICM42607_OFFSET_USER_NIBBLE_HI, nib));
+
+ raw |= FIELD_PREP(INV_ICM42607_OFFSET_LSB, byte);
+ offset = sign_extend32(raw, 11);
+
+ /*
+ * Convert raw offset to g then to m/s²
+ * 12 bits signed raw step 0.5mg to g: 5 / 10000
+ * g to m/s²: 9.806650
+ * Result in micro (1000000)
+ * (offset * 5 * 9.806650 * 1000000) / 10000
+ */
+ val64 = (s64)offset * 5LL * 9806650LL;
+ /* For rounding, add + or - divisor (10000) divided by 2 */
+ bias = DIV_S64_ROUND_CLOSEST(val64, 10000L);
+ *val = bias / (long)MEGA;
+ *val2 = bias % (long)MEGA;
+
+ return IIO_VAL_INT_PLUS_MICRO;
+}
+
+static int inv_icm42607_accel_write_offset(struct iio_dev *indio_dev,
+ struct iio_chan_spec const *chan,
+ int val, int val2)
+{
+ struct inv_icm42607_state *st = iio_device_get_drvdata(indio_dev);
+ struct device *dev = regmap_get_device(st->map);
+ s32 min, max;
+ u8 msb, lsb;
+ s16 offset;
+ s64 val64;
+ int ret;
+
+ if (chan->type != IIO_ACCEL)
+ return -EINVAL;
+
+ /* inv_icm42607_accel_calibbias: min - step - max in micro */
+ min = inv_icm42607_accel_calibbias[0] * (long)MEGA -
+ inv_icm42607_accel_calibbias[1];
+ max = inv_icm42607_accel_calibbias[4] * (long)MEGA +
+ inv_icm42607_accel_calibbias[5];
+
+ val64 = val * (s64)MEGA;
+ if (val >= 0)
+ val64 += val2;
+ else
+ val64 -= val2;
+
+ if (val64 < min || val64 > max)
+ return -EINVAL;
+
+ /*
+ * Convert m/s² to g then to raw value
+ * m/s² to g: 1 / 9.806650
+ * g to raw 12 bits signed, step 0.5mg: 10000 / 5
+ * val in micro (1000000)
+ * val * 10000 / (9.806650 * 1000000 * 5)
+ */
+ val64 *= 10000LL;
+ offset = DIV_S64_ROUND_CLOSEST(val64, 9806650 * 5);
+
+ /* Value is limited to 12 bits signed, return -EINVAL if out of range */
+ if (offset < -2048 || offset > 2047)
+ return -EINVAL;
+
+ msb = FIELD_GET(INV_ICM42607_OFFSET_MSB, offset);
+ lsb = FIELD_GET(INV_ICM42607_OFFSET_LSB, offset);
+
+ PM_RUNTIME_ACQUIRE_AUTOSUSPEND(dev, pm);
+ ret = PM_RUNTIME_ACQUIRE_ERR(&pm);
+ if (ret)
+ return ret;
+
+ guard(mutex)(&st->lock);
+
+ switch (chan->channel2) {
+ case IIO_MOD_X:
+ /* OFFSET_USER4 upper nibble is shared. */
+ ret = regmap_update_bits(st->map, INV_ICM42607_REG_OFFSET_USER4,
+ INV_ICM42607_OFFSET_USER_NIBBLE_HI,
+ FIELD_PREP(INV_ICM42607_OFFSET_USER_NIBBLE_HI, msb));
+ if (ret)
+ return ret;
+
+ return regmap_write(st->map, INV_ICM42607_REG_OFFSET_USER5, lsb);
+ case IIO_MOD_Y:
+ /* OFFSET_USER7 lower nibble is shared. */
+ ret = regmap_update_bits(st->map, INV_ICM42607_REG_OFFSET_USER7,
+ INV_ICM42607_OFFSET_USER_NIBBLE_LO,
+ FIELD_PREP(INV_ICM42607_OFFSET_USER_NIBBLE_LO, msb));
+ if (ret)
+ return ret;
+
+ return regmap_write(st->map, INV_ICM42607_REG_OFFSET_USER6, lsb);
+ case IIO_MOD_Z:
+ /* OFFSET_USER7 upper nibble is shared. */
+ ret = regmap_update_bits(st->map, INV_ICM42607_REG_OFFSET_USER7,
+ INV_ICM42607_OFFSET_USER_NIBBLE_HI,
+ FIELD_PREP(INV_ICM42607_OFFSET_USER_NIBBLE_HI, msb));
+ if (ret)
+ return ret;
+
+ return regmap_write(st->map, INV_ICM42607_REG_OFFSET_USER8, lsb);
+ default:
+ return -EINVAL;
+ }
+}
+
static int inv_icm42607_accel_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan,
int *val, int *val2, long mask)
@@ -207,6 +381,8 @@ static int inv_icm42607_accel_read_raw(struct iio_dev *indio_dev,
return inv_icm42607_accel_read_scale(indio_dev, val, val2);
case IIO_CHAN_INFO_SAMP_FREQ:
return inv_icm42607_accel_read_odr(st, val, val2);
+ case IIO_CHAN_INFO_CALIBBIAS:
+ return inv_icm42607_accel_read_offset(st, chan, val, val2);
default:
return -EINVAL;
}
@@ -231,6 +407,12 @@ static int inv_icm42607_accel_read_avail(struct iio_dev *indio_dev,
*length = (ARRAY_SIZE(inv_icm42607_accel_odr) -
INV_ICM42607_ODR_1600HZ) * 2;
return IIO_AVAIL_LIST;
+ case IIO_CHAN_INFO_CALIBBIAS:
+ if (chan->type != IIO_ACCEL)
+ return -EINVAL;
+ *vals = inv_icm42607_accel_calibbias;
+ *type = IIO_VAL_INT_PLUS_MICRO;
+ return IIO_AVAIL_RANGE;
default:
return -EINVAL;
}
@@ -250,6 +432,8 @@ static int inv_icm42607_accel_write_raw(struct iio_dev *indio_dev,
return ret;
case IIO_CHAN_INFO_SAMP_FREQ:
return inv_icm42607_accel_write_odr(indio_dev, val, val2);
+ case IIO_CHAN_INFO_CALIBBIAS:
+ return inv_icm42607_accel_write_offset(indio_dev, chan, val, val2);
default:
return -EINVAL;
}
@@ -265,6 +449,7 @@ static int inv_icm42607_accel_write_raw_get_fmt(struct iio_dev *indio_dev,
return -EINVAL;
return IIO_VAL_INT_PLUS_NANO;
case IIO_CHAN_INFO_SAMP_FREQ:
+ case IIO_CHAN_INFO_CALIBBIAS:
return IIO_VAL_INT_PLUS_MICRO;
default:
return -EINVAL;
--
2.43.0
^ permalink raw reply [flat|nested] 7+ messages in thread