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From: Michael Burch <me@michaelburch.net>
To: Qiang Yu <qiang.yu@oss.qualcomm.com>
Cc: "Manivannan Sadhasivam" <mani@kernel.org>,
	"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
	"Krzysztof Wilczyński" <kwilczynski@kernel.org>,
	"Rob Herring" <robh@kernel.org>,
	"Bjorn Helgaas" <bhelgaas@google.com>,
	"Vinod Koul" <vkoul@kernel.org>,
	"Neil Armstrong" <neil.armstrong@linaro.org>,
	"Philipp Zabel" <p.zabel@pengutronix.de>,
	"Krishna Chaitanya Chundru" <krishna.chundru@oss.qualcomm.com>,
	"Konrad Dybcio" <konrad.dybcio@oss.qualcomm.com>,
	"Abel Vesa" <abel.vesa@oss.qualcomm.com>,
	linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org,
	linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org
Subject: Re: [PATCH 4/4] phy: qcom-qmp-pcie: Split phy_ops into init/exit/reset/power_on
Date: Tue, 13 Oct 2026 09:26:19 -0500	[thread overview]
Message-ID: <20261013142621.10328-1-me@michaelburch.net> (raw)
In-Reply-To: <20260915-align_pcie_init_sequence_0916-v1-4-0b2195836f30@oss.qualcomm.com>

On Tue, Sep 15, 2026 at 11:04:24PM -0700, Qiang Yu wrote:
> -	skip_reset = qmp->skip_init && !qphy_checkbits(pcs, cfg->regs[QPHY_PCS_STATUS],
> +	qmp->skip_reset = qmp->skip_init && !qphy_checkbits(pcs, cfg->regs[QPHY_PCS_STATUS],
>  							    cfg->phy_status);

[...]

> +static int qmp_pcie_reset(struct phy *phy)
> +{
> +	struct qmp_pcie *qmp = phy_get_drvdata(phy);
> +	const struct qmp_phy_cfg *cfg = qmp->cfg;
> +	int ret;
> +
> +	if (qmp->skip_reset)
> +		return 0;

This keeps the skip from 910b828b22b7 ("phy: qcom: qmp-pcie: Skip PHY
reset if already up"). That skip stops v7.3-rc7 from booting on the
Dell XPS 13 9345 (X1E80100), and I've sent a revert [1].

UEFI boots from the NVMe behind pcie6a, so the PHY is already up when
Linux probes it and the no-csr reset is skipped. pcie-qcom still
asserts PERST# and resets the controller, so the link has to train
again, and it doesn't:

  qcom-pcie 1bf8000.pcie: Device found, but not active

910b828b22b7 only changes whether that reset runs, and reverting it
fixes boot.

With patch 1/4, X1E (qcom_pcie_init_2_7_0()) would run:

  qcom_pcie_perst_assert()
  phy_init()                        skip_reset = true
  reset_control_assert(res->rst)
  phy_reset()                       returns 0, PHY not reset
  reset_control_deassert(res->rst)
  phy_power_on()                    skip_init: no tables, no SERDES start

That is the same sequence as 910b828b22b7, so this series would bring
the failure back. It also doesn't follow the HPG order in the cover
letter: the controller reset is toggled, the PHY reset isn't.

Could qmp_pcie_reset() always toggle the reset that skip_init selects,
with qmp->skip_reset dropped? If link retention comes back, the
controller knows whether it is keeping the link, so it can skip both
its own reset and phy_reset() then.

[1] https://lore.kernel.org/r/20261013-qmp-pcie-skip-reset-revert-v1@michaelburch.net

Michael

  parent reply	other threads:[~2026-10-13 14:26 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-09-16  6:04 [PATCH 0/4] PCI: qcom: Align PHY init sequence with HPG Qiang Yu
2026-09-16  6:04 ` [PATCH 1/4] PCI: qcom: Move PHY init and add PHY reset call to align " Qiang Yu
2026-09-21  9:14   ` Kathiravan Thirumoorthy
2026-09-16  6:04 ` [PATCH 2/4] PCI: qcom-ep: Move PHY init and drive PHY reset " Qiang Yu
2026-10-12 15:29   ` Manivannan Sadhasivam
2026-09-16  6:04 ` [PATCH 3/4] phy: qcom-qmp-pcie-multiphy: Split phy_ops into init/exit/reset/power_on Qiang Yu
2026-10-12 15:32   ` Manivannan Sadhasivam
2026-09-16  6:04 ` [PATCH 4/4] phy: qcom-qmp-pcie: " Qiang Yu
2026-09-21  9:15   ` Kathiravan Thirumoorthy
2026-10-13 14:26   ` Michael Burch [this message]
2026-09-16 15:55 ` [PATCH 0/4] PCI: qcom: Align PHY init sequence with HPG Bjorn Helgaas
2026-09-21 11:16   ` Manivannan Sadhasivam

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