From: Luke Macken <luke@phorex.org>
To: ritesh.kumar@oss.qualcomm.com, nabige.aala@oss.qualcomm.com
Cc: vkoul@kernel.org, neil.armstrong@linaro.org, mani@kernel.org,
manivannan.sadhasivam@oss.qualcomm.com, abelvesa@kernel.org,
abel.vesa@oss.qualcomm.com, dmitry.baryshkov@oss.qualcomm.com,
lumag@kernel.org, konrad.dybcio@oss.qualcomm.com,
johan+linaro@kernel.org, wesley.cheng@oss.qualcomm.com,
mahadevan.p@oss.qualcomm.com, quic_bjorande@quicinc.com,
linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org,
linux-kernel@vger.kernel.org, Luke Macken <luke@phorex.org>
Subject: Re: [PATCH v5 00/11] phy: qualcomm: qmp-combo: update DP PHY PLL programming on Glymur
Date: Fri, 16 Oct 2026 17:50:50 -0600 [thread overview]
Message-ID: <20261016235050.4060422-1-luke@phorex.org> (raw)
In-Reply-To: <20261001-glymur-phy-v3-v5-0-3848c2615d5a@oss.qualcomm.com>
Tested on a Lenovo ThinkPad T14s Gen 7 (Mahua / Snapdragon X2 Elite, which
uses the qcom,glymur-qmp-usb3-dp-phy compatible) with linux-next
next-20261013 plus this series: external DisplayPort over USB-C works,
Dell U3818DW at 3840x1600@60 over HBR2 x4, and the internal eDP panel keeps
working.
Tested-by: Luke Macken <luke@phorex.org>
One data point in case it is useful: without the series, link training on
this machine already succeeds at HBR2 x4, DPCD 0x202-0x205 read 77 77 01 01
and the symbol error counters stay at zero, but no picture is produced. The
DPU interface frame counter runs at 30 fps for the 60 Hz mode and the sink's
TEST_CRC count stays at zero, which is consistent with the DP pixel clock
running at half the requested rate. With the series the frame counter runs
at 60 fps and the sink returns a CRC, with the unchanged 5400000000 / 4 in
qmp_v8_configure_dp_clocks(). The same half-rate symptom was also seen
without the series at 2 lanes.
prev parent reply other threads:[~2026-10-16 23:51 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-01 9:34 Nabige Aala
2026-10-01 9:34 ` [PATCH v5 01/11] phy: qualcomm: qmp-combo: Add DP COM v8 header and fix register layout Nabige Aala
2026-10-01 9:34 ` [PATCH v5 02/11] phy: qualcomm: qmp-combo: Update DP PHY common init tables Nabige Aala
2026-10-01 9:34 ` [PATCH v5 03/11] phy: qualcomm: qmp-combo: Update link rate specific DP PHY tables Nabige Aala
2026-10-01 9:34 ` [PATCH v5 04/11] phy: qualcomm: qmp-combo: Ignore Type-C orientation for Glymur DP mode Nabige Aala
2026-10-01 10:01 ` Dmitry Baryshkov
2026-10-01 13:14 ` Nabige Aala
2026-10-22 11:01 ` Konrad Dybcio
2026-10-01 9:34 ` [PATCH v5 05/11] phy: qualcomm: qmp-combo: Add hardware-specific dp_aux_cfg2 and dp_phy_cfg1 fields Nabige Aala
2026-10-22 10:34 ` Konrad Dybcio
2026-10-01 9:34 ` [PATCH v5 06/11] phy: qualcomm: qmp-combo: Add v8 PCS-level drive level tables for Glymur Nabige Aala
2026-10-22 10:40 ` Konrad Dybcio
2026-10-01 9:34 ` [PATCH v5 07/11] phy: qualcomm: qmp-combo: Extract common DP PHY init sequence Nabige Aala
2026-10-01 9:34 ` [PATCH v5 08/11] phy: qualcomm: qmp-combo: Remove VCO_DIV programming from qmp_v8_configure_dp_clocks() Nabige Aala
2026-10-22 10:36 ` Konrad Dybcio
2026-10-01 9:34 ` [PATCH v5 09/11] phy: qualcomm: qmp-combo: Add per-link-rate auxless/LFPS and drive level for Glymur Nabige Aala
2026-10-01 9:34 ` [PATCH v5 10/11] phy: qualcomm: qmp-combo: Fix Glymur v8 DP PHY init and configure sequences Nabige Aala
2026-10-22 11:00 ` Konrad Dybcio
2026-10-01 9:34 ` [PATCH v5 11/11] phy: qualcomm: qmp-combo: Fix error propagation in qmp_combo_dp_power_on() Nabige Aala
2026-10-22 11:01 ` Konrad Dybcio
2026-10-16 23:50 ` Luke Macken [this message]
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