Re: [PATCH v5 10/11] phy: qualcomm: qmp-combo: Fix Glymur v8 DP PHY init and configure sequences

[Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>]

On 10/1/26 11:34 AM, Nabige Aala wrote:
> From: Ritesh Kumar <ritesh.kumar@oss.qualcomm.com>
> 
> Update qmp_v8_dp_aux_init():
> - Add CLK_FWD_CONFIG_1 initialization (0x3f) before power-down control
> - Replace PSR_PWRDN with LANE_0_1_PWRDN and LANE_2_3_PWRDN in PD_CTL
>   to correctly power down the data lanes
> - Correct BIAS_EN_CLKBUFLR_EN value from 0x1c to 0x17
> 
> Update qmp_v4_configure_dp_tx():
> - Correct default TX_EMP_POST1_LVL value from 0x20 to 0x2b
> 
> Update qmp_v8_configure_dp_phy():
> - Correct 2-lane and 4-lane driver enable values to 0x30 (was 0x10/0x34)
> - Add CLKBUF_ENABLE (0x87) programming for both TX lanes before driver
>   enable writes
> - Add TSYNC_OVRD sequence (0x03 -> 0x23 -> 0x22 -> 0x3e) and
>   LALB_RESET_TSYNC_EN_CTRL (0x0a) programming for proper TSYNC handling
> - Fix QPHY_DP_PHY_STATUS poll to check BIT(0) instead of BIT(1)
> - Replace post-lock TX_DRV_LVL/TX_EMP writes with two COM_CMN_STATUS
>   polls (BIT(0) and BIT(1)) to properly verify PLL lock completion

If I didn't have the LLM at my disposal this would be really really
hard to review

[...]

> +	writel(0x87, qmp->dp_tx + QSERDES_V8_LALB_CLKBUF_ENABLE);
> +	writel(0x87, qmp->dp_tx2 + QSERDES_V8_LALB_CLKBUF_ENABLE);

The HPG asks to first write 0x8f to first

[...]

> +	ret = readl_poll_timeout(qmp->dp_serdes + cfg->regs[QPHY_COM_CMN_STATUS],
> +			status,
> +			((status & BIT(1)) > 0),
> +			500,
> +			10000);

The programming guide doesn't ask to check this bit and the way I read
the description of this bit within the register, bit0 already asserts
this being true

The rest is OK

Konrad