From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
To: Nabige Aala <nabige.aala@oss.qualcomm.com>,
Vinod Koul <vkoul@kernel.org>,
Neil Armstrong <neil.armstrong@linaro.org>,
Manivannan Sadhasivam <mani@kernel.org>,
Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>,
Wesley Cheng <wesley.cheng@oss.qualcomm.com>,
Abel Vesa <abelvesa@kernel.org>,
Johan Hovold <johan+linaro@kernel.org>,
Bjorn Andersson <quic_bjorande@quicinc.com>,
Dmitry Baryshkov <lumag@kernel.org>
Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org,
linux-kernel@vger.kernel.org,
Ritesh Kumar <ritesh.kumar@oss.qualcomm.com>,
Mahadevan P <mahadevan.p@oss.qualcomm.com>
Subject: Re: [PATCH v5 05/11] phy: qualcomm: qmp-combo: Add hardware-specific dp_aux_cfg2 and dp_phy_cfg1 fields
Date: Thu, 22 Oct 2026 12:34:46 +0200 [thread overview]
Message-ID: <e3a8d06e-5f7f-4743-a332-b2a8ef30e781@oss.qualcomm.com> (raw)
In-Reply-To: <20261001-glymur-phy-v3-v5-5-3848c2615d5a@oss.qualcomm.com>
On 10/1/26 11:34 AM, Nabige Aala wrote:
> From: Ritesh Kumar <ritesh.kumar@oss.qualcomm.com>
>
> Add dp_aux_cfg2 and dp_phy_cfg1 fields to qmp_phy_cfg to allow
> hardware-specific DP PHY register values to be specified per-platform
> rather than hardcoded in the configure functions.
>
> Define named constants QSERDES_DP_PHY_AUX_CFG2_V456/V8 and
> QSERDES_DP_PHY_CFG1_V456/V8 for better readability and maintainability.
>
> Populate the new fields in all existing DP PHY cfg structures:
> - V456-based platforms (sar2130p, sc8180x, sc8280xp, x1e80100, sm8250,
> sm8350, sm8475, sm8550, sm8650, sm8750) use V456 constants
> - Glymur (V8) uses V8 constants
>
> Signed-off-by: Ritesh Kumar <ritesh.kumar@oss.qualcomm.com>
> Signed-off-by: Mahadevan P <mahadevan.p@oss.qualcomm.com>
> Signed-off-by: Nabige Aala <nabige.aala@oss.qualcomm.com>
> ---
> drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 37 ++++++++++++++++++++++++++++++-
> 1 file changed, 36 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
> index 646e97a52886..ebe2e6136f7a 100644
> --- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
> @@ -2486,6 +2486,14 @@ static const struct qmp_combo_lane_mapping dp_data_lanes[] = {
>
> struct qmp_combo;
>
> +/* DP PHY AUX_CFG2 register values for different hardware versions */
> +#define QSERDES_DP_PHY_AUX_CFG2_V456 0xa4
> +#define QSERDES_DP_PHY_AUX_CFG2_V8 0x06
The doc says this should be 0x16 for flipped typec
> +/* DP PHY CFG_1 register values for different hardware versions */
> +#define QSERDES_DP_PHY_CFG1_V456 0x0f
> +#define QSERDES_DP_PHY_CFG1_V8 0x2f
And this should reportedly be 0x13/0x53 for normal/flipped
Konrad
next prev parent reply other threads:[~2026-10-22 10:34 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-01 9:34 [PATCH v5 00/11] phy: qualcomm: qmp-combo: update DP PHY PLL programming on Glymur Nabige Aala
2026-10-01 9:34 ` [PATCH v5 01/11] phy: qualcomm: qmp-combo: Add DP COM v8 header and fix register layout Nabige Aala
2026-10-01 9:34 ` [PATCH v5 02/11] phy: qualcomm: qmp-combo: Update DP PHY common init tables Nabige Aala
2026-10-01 9:34 ` [PATCH v5 03/11] phy: qualcomm: qmp-combo: Update link rate specific DP PHY tables Nabige Aala
2026-10-01 9:34 ` [PATCH v5 04/11] phy: qualcomm: qmp-combo: Ignore Type-C orientation for Glymur DP mode Nabige Aala
2026-10-01 10:01 ` Dmitry Baryshkov
2026-10-01 13:14 ` Nabige Aala
2026-10-22 11:01 ` Konrad Dybcio
2026-10-01 9:34 ` [PATCH v5 05/11] phy: qualcomm: qmp-combo: Add hardware-specific dp_aux_cfg2 and dp_phy_cfg1 fields Nabige Aala
2026-10-22 10:34 ` Konrad Dybcio [this message]
2026-10-01 9:34 ` [PATCH v5 06/11] phy: qualcomm: qmp-combo: Add v8 PCS-level drive level tables for Glymur Nabige Aala
2026-10-22 10:40 ` Konrad Dybcio
2026-10-01 9:34 ` [PATCH v5 07/11] phy: qualcomm: qmp-combo: Extract common DP PHY init sequence Nabige Aala
2026-10-01 9:34 ` [PATCH v5 08/11] phy: qualcomm: qmp-combo: Remove VCO_DIV programming from qmp_v8_configure_dp_clocks() Nabige Aala
2026-10-22 10:36 ` Konrad Dybcio
2026-10-01 9:34 ` [PATCH v5 09/11] phy: qualcomm: qmp-combo: Add per-link-rate auxless/LFPS and drive level for Glymur Nabige Aala
2026-10-01 9:34 ` [PATCH v5 10/11] phy: qualcomm: qmp-combo: Fix Glymur v8 DP PHY init and configure sequences Nabige Aala
2026-10-22 11:00 ` Konrad Dybcio
2026-10-01 9:34 ` [PATCH v5 11/11] phy: qualcomm: qmp-combo: Fix error propagation in qmp_combo_dp_power_on() Nabige Aala
2026-10-22 11:01 ` Konrad Dybcio
2026-10-16 23:50 ` [PATCH v5 00/11] phy: qualcomm: qmp-combo: update DP PHY PLL programming on Glymur Luke Macken
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