[PATCH 0/9] Fix USB2 and USB3 on NSP SoCs

[PATCH 0/9] Fix USB2 and USB3 on NSP SoCs

[Florian Fainelli]

Similar to the SATA patch series, USB2 and USB3 on Northstar Plus SoCs
was broken in a few different areas:

- the NSP variant was not described properly at the USB PHY level which
  prevented SoC-specific initialization from occurring
- the lack of DMP registers meant that the USB PHY could not complete
  the initilization and instead relies on the boot loader
- the EHCI controller requires some FIFO tuning which is similar to the
  XGS iProc SoC, otherwise DMA transfers eventually fail
- finally, the USB controllers are non coherent

Florian Fainelli (9):
  phy: broadcom: ns-usb3: Propagate Bx initialization write errors
  dt-bindings: phy: bcm-ns-usb3-phy: Describe the NSP variant
  phy: broadcom: ns-usb3: Coordinate NSP USB2 and USB3 initialization
  ARM: dts: broadcom: Add the NSP USB2 DMP registers
  ARM: dts: broadcom: Share USB PHY initialization on BCM958625HR
  dt-bindings: usb: generic-ehci: Add the NSP compatible
  usb: host: ehci-platform: Set the FIFO threshold on NSP
  ARM: dts: broadcom: Identify the NSP EHCI controller
  ARM: dts: broadcom: Use noncoherent USB DMA on BCM958625HR

 .../bindings/phy/bcm-ns-usb3-phy.yaml         |  23 +++
 .../devicetree/bindings/usb/generic-ehci.yaml |   1 +
 arch/arm/boot/dts/broadcom/bcm-nsp.dtsi       |   6 +-
 arch/arm/boot/dts/broadcom/bcm958625hr.dts    |   9 ++
 drivers/phy/broadcom/phy-bcm-ns-usb3.c        | 134 +++++++++++++-----
 drivers/usb/host/ehci-platform.c              |   3 +-
 6 files changed, 139 insertions(+), 37 deletions(-)

-- 
2.53.0

[PATCH 2/9] dt-bindings: phy: bcm-ns-usb3-phy: Describe the NSP variant

[Florian Fainelli]

Northstar Plus uses the Northstar Bx PHY register sequence but also
requires coordinated USB2 and USB3 core resets and a USB2 IDM interface
clock enable.

Add an NSP compatible with a required USB2 DMP phandle. Describe the
shared PHY relationship with EHCI, OHCI and xHCI so initialization
finishes before any host starts operating.

Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
---
 .../bindings/phy/bcm-ns-usb3-phy.yaml         | 23 +++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/Documentation/devicetree/bindings/phy/bcm-ns-usb3-phy.yaml b/Documentation/devicetree/bindings/phy/bcm-ns-usb3-phy.yaml
index 7fd419db45d0..00d69b86cbff 100644
--- a/Documentation/devicetree/bindings/phy/bcm-ns-usb3-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/bcm-ns-usb3-phy.yaml
@@ -14,6 +14,9 @@ description: |
   Known B1: BCM4707 rev 6
   Known C0: BCM47094 rev 0
 
+  Northstar Plus uses the Bx programming sequence, with coordinated USB2 and
+  USB3 resets. Its PHY is shared by the EHCI, OHCI and xHCI controllers.
+
 maintainers:
   - Rafał Miłecki <rafal@milecki.pl>
 
@@ -22,6 +25,7 @@ properties:
     enum:
       - brcm,ns-ax-usb3-phy
       - brcm,ns-bx-usb3-phy
+      - brcm,nsp-usb3-phy
 
   reg:
     description: address of MDIO bus device
@@ -32,6 +36,13 @@ properties:
     description:
       Phandle to the DMP (Device Management Plugin) syscon
 
+  usb2-dmp-syscon:
+    $ref: /schemas/types.yaml#/definitions/phandle
+    description:
+      Phandle to the USB2 DMP on Northstar Plus, for its interface clock and
+      reset. All USB host controllers must reference this shared PHY so that
+      initialization completes before any of them starts using it.
+
   "#phy-cells":
     const: 0
 
@@ -41,6 +52,18 @@ required:
   - usb3-dmp-syscon
   - "#phy-cells"
 
+allOf:
+  - if:
+      properties:
+        compatible:
+          const: brcm,nsp-usb3-phy
+    then:
+      required:
+        - usb2-dmp-syscon
+    else:
+      properties:
+        usb2-dmp-syscon: false
+
 additionalProperties: false
 
 examples:
-- 
2.53.0

[PATCH 3/9] phy: broadcom: ns-usb3: Coordinate NSP USB2 and USB3 initialization

[Florian Fainelli]

The iProc SDK holds both USB2 and USB3 cores in reset while programming
the USB3 PLL, then releases USB2 before USB3. It also enables the USB2
IDM interface clock. The Northstar Bx initialization used by NSP does
not perform the USB2 setup or retain the SDK settling intervals.

Implement an NSP variant with the coordinated reset sequence and
interface clock enable. Sharing one PHY between the HCDs lets the PHY
core serialize and reference-count initialization, preventing a later
host probe from resetting an already active USB2 controller.

Retain the downstream delays around reset and MDIO operations, and
leave both NSP cores reset if programming fails. Keep existing
Northstar Ax and Bx reset behavior unchanged.

Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
---
 drivers/phy/broadcom/phy-bcm-ns-usb3.c | 55 ++++++++++++++++++++++++++
 1 file changed, 55 insertions(+)

diff --git a/drivers/phy/broadcom/phy-bcm-ns-usb3.c b/drivers/phy/broadcom/phy-bcm-ns-usb3.c
index b40033144080..b3b5b74ead09 100644
--- a/drivers/phy/broadcom/phy-bcm-ns-usb3.c
+++ b/drivers/phy/broadcom/phy-bcm-ns-usb3.c
@@ -44,12 +44,14 @@ enum bcm_ns_family {
 	BCM_NS_UNKNOWN,
 	BCM_NS_AX,
 	BCM_NS_BX,
+	BCM_NSP,
 };
 
 struct bcm_ns_usb3 {
 	struct device *dev;
 	enum bcm_ns_family family;
 	void __iomem *dmp;
+	void __iomem *usb2_dmp;
 	struct mdio_device *mdiodev;
 	struct phy *phy;
 };
@@ -63,6 +65,10 @@ static const struct of_device_id bcm_ns_usb3_id_table[] = {
 		.compatible = "brcm,ns-bx-usb3-phy",
 		.data = (int *)BCM_NS_BX,
 	},
+	{
+		.compatible = "brcm,nsp-usb3-phy",
+		.data = (void *)BCM_NSP,
+	},
 	{},
 };
 MODULE_DEVICE_TABLE(of, bcm_ns_usb3_id_table);
@@ -86,6 +92,9 @@ static int bcm_ns_usb3_write_seq(struct bcm_ns_usb3 *usb3,
 		err = bcm_ns_usb3_mdio_phy_write(usb3, seq[i].reg, seq[i].value);
 		if (err)
 			return err;
+
+		if (usb3->family == BCM_NSP)
+			usleep_range(10000, 20000);
 	}
 
 	return 0;
@@ -121,8 +130,18 @@ static int bcm_ns_usb3_phy_init_ns_bx(struct bcm_ns_usb3 *usb3)
 	if (err)
 		return err;
 
+	if (usb3->usb2_dmp) {
+		writel(0, usb3->usb2_dmp + BCMA_RESET_CTL);
+		readl(usb3->usb2_dmp + BCMA_RESET_CTL);
+		usleep_range(10000, 20000);
+	}
+
 	/* Deasserting USB3 system reset */
 	writel(0, usb3->dmp + BCMA_RESET_CTL);
+	if (usb3->family == BCM_NSP) {
+		readl(usb3->dmp + BCMA_RESET_CTL);
+		usleep_range(10000, 20000);
+	}
 
 	return bcm_ns_usb3_write_seq(usb3, phy_seq, ARRAY_SIZE(phy_seq));
 }
@@ -160,16 +179,35 @@ static int bcm_ns_usb3_phy_init_ns_ax(struct bcm_ns_usb3 *usb3)
 static int bcm_ns_usb3_phy_init(struct phy *phy)
 {
 	struct bcm_ns_usb3 *usb3 = phy_get_drvdata(phy);
+	u32 val;
 	int err;
 
+	/*
+	 * NSP requires both hosts to remain in reset while programming the PLL.
+	 * Sharing this PHY between all three HCDs makes the PHY core serialize
+	 * and reference-count this sequence, regardless of their probe order.
+	 */
+	if (usb3->usb2_dmp) {
+		val = readl(usb3->usb2_dmp + BCMA_IOCTL);
+		writel(val | BCMA_IOCTL_CLK, usb3->usb2_dmp + BCMA_IOCTL);
+		writel(BCMA_RESET_CTL_RESET, usb3->usb2_dmp + BCMA_RESET_CTL);
+		readl(usb3->usb2_dmp + BCMA_RESET_CTL);
+		usleep_range(10000, 20000);
+	}
+
 	/* Perform USB3 system soft reset */
 	writel(BCMA_RESET_CTL_RESET, usb3->dmp + BCMA_RESET_CTL);
+	if (usb3->family == BCM_NSP) {
+		readl(usb3->dmp + BCMA_RESET_CTL);
+		usleep_range(10000, 20000);
+	}
 
 	switch (usb3->family) {
 	case BCM_NS_AX:
 		err = bcm_ns_usb3_phy_init_ns_ax(usb3);
 		break;
 	case BCM_NS_BX:
+	case BCM_NSP:
 		err = bcm_ns_usb3_phy_init_ns_bx(usb3);
 		break;
 	default:
@@ -177,6 +215,11 @@ static int bcm_ns_usb3_phy_init(struct phy *phy)
 		err = -ENOTSUPP;
 	}
 
+	if (err && usb3->usb2_dmp) {
+		writel(BCMA_RESET_CTL_RESET, usb3->usb2_dmp + BCMA_RESET_CTL);
+		writel(BCMA_RESET_CTL_RESET, usb3->dmp + BCMA_RESET_CTL);
+	}
+
 	return err;
 }
 
@@ -225,6 +268,18 @@ static int bcm_ns_usb3_mdio_probe(struct mdio_device *mdiodev)
 	if (IS_ERR(usb3->dmp))
 		return PTR_ERR(usb3->dmp);
 
+	if (usb3->family == BCM_NSP) {
+		syscon_np = of_parse_phandle(dev->of_node, "usb2-dmp-syscon", 0);
+		err = of_address_to_resource(syscon_np, 0, &res);
+		of_node_put(syscon_np);
+		if (err)
+			return err;
+
+		usb3->usb2_dmp = devm_ioremap_resource(dev, &res);
+		if (IS_ERR(usb3->usb2_dmp))
+			return PTR_ERR(usb3->usb2_dmp);
+	}
+
 	usb3->phy = devm_phy_create(dev, NULL, &ops);
 	if (IS_ERR(usb3->phy)) {
 		dev_err(dev, "Failed to create PHY\n");
-- 
2.53.0

[PATCH 6/9] dt-bindings: usb: generic-ehci: Add the NSP compatible

[Florian Fainelli]

Describe the EHCI controller in Broadcom Northstar Plus SoCs with a
SoC-specific compatible. It needs the same FIFO threshold programming
as other iProc EHCI controllers, which generic-ehci alone cannot select.

Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
---
 Documentation/devicetree/bindings/usb/generic-ehci.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/usb/generic-ehci.yaml b/Documentation/devicetree/bindings/usb/generic-ehci.yaml
index ae9fb70d0212..6462772b51dc 100644
--- a/Documentation/devicetree/bindings/usb/generic-ehci.yaml
+++ b/Documentation/devicetree/bindings/usb/generic-ehci.yaml
@@ -48,6 +48,7 @@ properties:
               - brcm,bcm7420-ehci
               - brcm,bcm7425-ehci
               - brcm,bcm7435-ehci
+              - brcm,nsp-ehci
               - hpe,gxp-ehci
               - ibm,476gtr-ehci
               - nxp,lpc1850-ehci
-- 
2.53.0

[PATCH 7/9] usb: host: ehci-platform: Set the FIFO threshold on NSP

[Florian Fainelli]

The NSP SDK programs the EHCI INSNREG01 FIFO threshold to 0x00800040.
This is the same setting already applied by ehci-platform for the
brcm,xgs-iproc-ehci compatible to avoid problems with large transfers.

Apply the existing workaround to the NSP compatible as well.

Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
---
 drivers/usb/host/ehci-platform.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/usb/host/ehci-platform.c b/drivers/usb/host/ehci-platform.c
index f61f095cedab..9b7188d9c288 100644
--- a/drivers/usb/host/ehci-platform.c
+++ b/drivers/usb/host/ehci-platform.c
@@ -77,7 +77,8 @@ static int ehci_platform_reset(struct usb_hcd *hcd)
 	if (pdata->no_io_watchdog)
 		ehci->need_io_watchdog = 0;
 
-	if (of_device_is_compatible(pdev->dev.of_node, "brcm,xgs-iproc-ehci"))
+	if (of_device_is_compatible(pdev->dev.of_node, "brcm,xgs-iproc-ehci") ||
+	    of_device_is_compatible(pdev->dev.of_node, "brcm,nsp-ehci"))
 		ehci_writel(ehci, BCM_USB_FIFO_THRESHOLD,
 			    &ehci->regs->brcm_insnreg[1]);
 
-- 
2.53.0

[PATCH 8/9] ARM: dts: broadcom: Identify the NSP EHCI controller

[Florian Fainelli]

The NSP SDK programs the EHCI FIFO threshold to 0x00800040, but the
upstream device tree describes the controller only as generic-ehci.
This prevents ehci-platform from selecting the required initialization.

Add the NSP compatible to select its FIFO threshold workaround while
retaining generic-ehci as a fallback.

Fixes: 1d8ece6639e1 ("ARM: dts: NSP: Add EHCI/OHCI USB nodes to device tree")
Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
---
 arch/arm/boot/dts/broadcom/bcm-nsp.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/broadcom/bcm-nsp.dtsi b/arch/arm/boot/dts/broadcom/bcm-nsp.dtsi
index c3c33f18b92a..b3f0190d0d86 100644
--- a/arch/arm/boot/dts/broadcom/bcm-nsp.dtsi
+++ b/arch/arm/boot/dts/broadcom/bcm-nsp.dtsi
@@ -325,7 +325,7 @@ xhci: usb@29000 {
 		};
 
 		ehci0: usb@2a000 {
-			compatible = "generic-ehci";
+			compatible = "brcm,nsp-ehci", "generic-ehci";
 			reg = <0x2a000 0x100>;
 			interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
 			dma-coherent;
-- 
2.53.0

[PATCH 9/9] ARM: dts: broadcom: Use noncoherent USB DMA on BCM958625HR

[Florian Fainelli]

The USB hosts on BCM958625HR fail when using the dma-coherent properties
inherited from bcm-nsp.dtsi. xHCI aborts commands, while EHCI and OHCI
report fatal errors during enumeration and stop servicing their shared
interrupt.

Removing these properties restores high-speed USB2 device enumeration
and SuperSpeed USB3 operation on the board. Use noncoherent DMA for all
three hosts so the ARM DMA API maintains their descriptors and buffers,
as in the downstream SDK. Limit the override to the tested board.

Fixes: 56e2ff0346a3 ("ARM: dts: NSP: Add dma-coherent to relevant DT entries")
Fixes: bbe526f55b60 ("ARM: dts: NSP: Add USB3 and USB3 PHY to NSP")
Signed-off-by: Florian Fainelli <florian.fainelli@broadcom.com>
---
 arch/arm/boot/dts/broadcom/bcm958625hr.dts | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm/boot/dts/broadcom/bcm958625hr.dts b/arch/arm/boot/dts/broadcom/bcm958625hr.dts
index 0105afeca748..c896c390f042 100644
--- a/arch/arm/boot/dts/broadcom/bcm958625hr.dts
+++ b/arch/arm/boot/dts/broadcom/bcm958625hr.dts
@@ -86,6 +86,7 @@ &amac2 {
 };
 
 &ehci0 {
+	/delete-property/ dma-coherent;
 	phys = <&usb3_phy>;
 	phy-names = "usb";
 	status = "okay";
@@ -130,6 +131,7 @@ partition@4000000 {
 };
 
 &ohci0 {
+	/delete-property/ dma-coherent;
 	phys = <&usb3_phy>;
 	phy-names = "usb";
 	status = "okay";
@@ -255,5 +257,6 @@ &usb3_phy {
 };
 
 &xhci {
+	/delete-property/ dma-coherent;
 	status = "okay";
 };
-- 
2.53.0