[PATCH v2 0/4] powerpc/topology: Introduce llc_override kernel parameter

[PATCH v2 0/4] powerpc/topology: Introduce llc_override kernel parameter

[Shrikanth Hegde]

Provide an option for users to enable cache aware scheduling on powerpc
via a command line parameter.

More details of the problem and context is in cover-letter of v1.
v1: https://lore.kernel.org/all/20261012102037.2477378-1-sshegde@linux.ibm.com/

v1->v2:
- Move to kernel parameters from debugfs. This helps to keep
  llc_id consistent which doesn't change across sched domain
  rebuilds. (Tim Chen)
- Update arch_llc_mask to reflect the override (Tim Chen)
- Limit only to mc, pkg (Srikar Dronamraju)

Notes:

- A selftest for the functional validation of cache aware scheduling
  is a good idea as we discussed in v1. It is a significant change on
  its own and likely takes time. I am thinking it might be good idea to
  revisit selftests for scheduler in general. (We have very few).
  Maybe worth a discussion in coming OSPM. 

- I am on parental leave. This version is pretty much what I had last week
  and I haven't gotten any chance to update since. just sending it out.
  Sorry if I have missed to address any comments.
  Please expect delays in my response.

Shrikanth Hegde (4):
  powerpc/topology: Introduce llc_override kernel parameter
  powerpc/topology: Update mc/pkg flags based on llc_override
  powerpc/topology: update arch_llc_mask based llc_override
  Documentation/powerpc: Add details about llc_override

 .../admin-guide/kernel-parameters.txt         | 15 ++++
 arch/powerpc/include/asm/topology.h           |  8 +--
 arch/powerpc/kernel/smp.c                     | 69 +++++++++++++++++--
 3 files changed, 81 insertions(+), 11 deletions(-)

-- 
2.52.0

[PATCH v2 1/4] powerpc/topology: Introduce llc_override kernel parameter

[Shrikanth Hegde]

There is a new feature in scheduler called as Cache Aware Scheduling.
It tries to keep related tasks within the same LLC domain while
keeping the system reasonably balanced.

Cache Aware Scheduling assumes that the scheduler LLC domain is large
enough to be a useful placement target. This is true on many systems
where an LLC spans several cores, but not on PowerPC systems where the
scheduler-visible LLC is at the SMT level.
In that case, sd_llc_size is effectively the SMT width.

This becomes visible in the capacity check:

  !fits_capacity((mm->sc_stat.nr_running_avg * cpu_smt_num_threads),
                  scale * per_cpu(sd_llc_size, cpu));

As a result, it may be enabled but has no room to operate.
Hence provide a kernel parameter so that one can try experiment
their workload with cache aware scheduling. This also provides ways to
explore it on system with SMT=4 to see if there are any opportunities
to improve or uncover bugs if there is any.

This does not change the hardware cache topology. It only changes the
sched-domain level at which SD_SHARE_LLC is set.

There is no point in setting NUMA as the LLC domain. So give option
until pkg to experiment with.

Actual flag manipulations for sched domain flags and llc mask is updated
in the subsequent patches.

Signed-off-by: Shrikanth Hegde <sshegde@linux.ibm.com>
---
 arch/powerpc/kernel/smp.c | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/arch/powerpc/kernel/smp.c b/arch/powerpc/kernel/smp.c
index 6a5a5469aaae..6b1201ea3572 100644
--- a/arch/powerpc/kernel/smp.c
+++ b/arch/powerpc/kernel/smp.c
@@ -1059,6 +1059,29 @@ static bool has_coregroup_support(void)
 	return coregroup_enabled;
 }
 
+enum llc_override_values {
+	LLC_OVERRIDE_MC		= 1,
+	LLC_OVERRIDE_PKG	= 2,
+};
+
+static int llc_override;
+
+static int __init set_llc_override(char *str)
+{
+	if (!strcasecmp(str, "mc") && has_coregroup_support())
+		WRITE_ONCE(llc_override, LLC_OVERRIDE_MC);
+	else if (!strcasecmp(str, "pkg"))
+		WRITE_ONCE(llc_override, LLC_OVERRIDE_PKG);
+	else {
+		pr_warn("Unsupported llc_override=%s\n", str);
+		return 1;
+	}
+
+	pr_info("llc_override set at domain: %s\n", str);
+	return 1;
+}
+__setup("llc_override=", set_llc_override);
+
 static int __init init_big_cores(void)
 {
 	int cpu;
-- 
2.52.0

Re: [PATCH v2 1/4] powerpc/topology: Introduce llc_override kernel parameter

[Chen Yu]

Hi Shrikanth,

On Fri, Oct 23, 2026 at 06:46:43PM +0530, Shrikanth Hegde wrote:

[ ... ]

> ---
>  arch/powerpc/kernel/smp.c | 23 +++++++++++++++++++++++
>  1 file changed, 23 insertions(+)
> 
> diff --git a/arch/powerpc/kernel/smp.c b/arch/powerpc/kernel/smp.c
> index 6a5a5469aaae..6b1201ea3572 100644
> --- a/arch/powerpc/kernel/smp.c
> +++ b/arch/powerpc/kernel/smp.c
> @@ -1059,6 +1059,29 @@ static bool has_coregroup_support(void)
>  	return coregroup_enabled;
>  }
>  
> +enum llc_override_values {
> +	LLC_OVERRIDE_MC		= 1,
> +	LLC_OVERRIDE_PKG	= 2,
> +};
> +
> +static int llc_override;
> +
> +static int __init set_llc_override(char *str)
> +{
> +	if (!strcasecmp(str, "mc") && has_coregroup_support())
> +		WRITE_ONCE(llc_override, LLC_OVERRIDE_MC);

There is only 1 booting CPU at the moment, maybe WRITE_ONCE() is not needed.

> +	else if (!strcasecmp(str, "pkg"))
> +		WRITE_ONCE(llc_override, LLC_OVERRIDE_PKG);
> +	else {
> +		pr_warn("Unsupported llc_override=%s\n", str);
> +		return 1;
> +	}
> +
> +	pr_info("llc_override set at domain: %s\n", str);
> +	return 1;
> +}
> +__setup("llc_override=", set_llc_override);
> +
>  static int __init init_big_cores(void)
>  {
>  	int cpu;

On PowerPC, it seems that get_effective_llc_bytes() always returns 0,
which makes exceed_llc_capacity() return true, so cache-aware scheduling
is disabled on PowerPC. We might need to provide an arch_llc_bytes() that
is adjusted based on llc_override - sometimes calculate the sum of L2 across
several cores.

thanks,
Chenyu

[PATCH v2 2/4] powerpc/topology: Update mc/pkg flags based on llc_override

[Shrikanth Hegde]

Update the flags passed for building the scheduler topology based on
llc_override.

SD_SHARE_LLC is used to determine the highest domain where the LLC is.
Also when set at a particular domain, all the child domains are expected
to have it set as well.

Signed-off-by: Shrikanth Hegde <sshegde@linux.ibm.com>
---
 arch/powerpc/kernel/smp.c | 41 +++++++++++++++++++++++++++------------
 1 file changed, 29 insertions(+), 12 deletions(-)

diff --git a/arch/powerpc/kernel/smp.c b/arch/powerpc/kernel/smp.c
index 6b1201ea3572..ca1821dedc98 100644
--- a/arch/powerpc/kernel/smp.c
+++ b/arch/powerpc/kernel/smp.c
@@ -1007,6 +1007,12 @@ static int powerpc_smt_flags(void)
  */
 static __ro_after_init DEFINE_STATIC_KEY_FALSE(splpar_asym_pack);
 
+static int llc_override;
+enum llc_override_values {
+	LLC_OVERRIDE_MC		= 1,
+	LLC_OVERRIDE_PKG	= 2,
+};
+
 /*
  * P9 has a slightly odd architecture where pairs of cores share an L2 cache.
  * This topology makes it *much* cheaper to migrate tasks between adjacent cores
@@ -1021,12 +1027,30 @@ static int powerpc_shared_cache_flags(void)
 	return SD_SHARE_LLC;
 }
 
-static int powerpc_shared_proc_flags(void)
+static int powerpc_mc_flags(void)
 {
+	int flags = 0;
+
 	if (static_branch_unlikely(&splpar_asym_pack))
-		return SD_ASYM_PACKING;
+		flags |= SD_ASYM_PACKING;
 
-	return 0;
+	if (READ_ONCE(llc_override) >= LLC_OVERRIDE_MC)
+		flags |= SD_SHARE_LLC;
+
+	return flags;
+}
+
+static int powerpc_pkg_flags(void)
+{
+	int flags = 0;
+
+	if (static_branch_unlikely(&splpar_asym_pack))
+		flags |= SD_ASYM_PACKING;
+
+	if (READ_ONCE(llc_override) >= LLC_OVERRIDE_PKG)
+		flags |= SD_SHARE_LLC;
+
+	return flags;
 }
 
 /*
@@ -1059,13 +1083,6 @@ static bool has_coregroup_support(void)
 	return coregroup_enabled;
 }
 
-enum llc_override_values {
-	LLC_OVERRIDE_MC		= 1,
-	LLC_OVERRIDE_PKG	= 2,
-};
-
-static int llc_override;
-
 static int __init set_llc_override(char *str)
 {
 	if (!strcasecmp(str, "mc") && has_coregroup_support())
@@ -1759,10 +1776,10 @@ static void __init build_sched_topology(void)
 
 	if (has_coregroup_support()) {
 		powerpc_topology[i++] =
-			SDTL_INIT(tl_mc_mask, powerpc_shared_proc_flags, MC);
+			SDTL_INIT(tl_mc_mask, powerpc_mc_flags, MC);
 	}
 
-	powerpc_topology[i++] = SDTL_INIT(tl_pkg_mask, powerpc_shared_proc_flags, PKG);
+	powerpc_topology[i++] = SDTL_INIT(tl_pkg_mask, powerpc_pkg_flags, PKG);
 
 	/* There must be one trailing NULL entry left.  */
 	BUG_ON(i >= ARRAY_SIZE(powerpc_topology) - 1);
-- 
2.52.0

[PATCH v2 3/4] powerpc/topology: Update arch_llc_mask based llc_override

[Shrikanth Hegde]

Update the arch_llc_mask passed for building the cache aware scheduling
data structures such as llc_id etc.

Since llc_override is kernel parameter, this helps to keep the
arch_llc_mask stable after boot which in turn keeps llc_id consistent,
since llc_id are not updated even on rebuilding the sched domains.

Signed-off-by: Shrikanth Hegde <sshegde@linux.ibm.com>
---
 arch/powerpc/include/asm/topology.h |  8 ++------
 arch/powerpc/kernel/smp.c           | 19 +++++++++++++++++++
 2 files changed, 21 insertions(+), 6 deletions(-)

diff --git a/arch/powerpc/include/asm/topology.h b/arch/powerpc/include/asm/topology.h
index 44ec416fa489..e1ca91d9b2c2 100644
--- a/arch/powerpc/include/asm/topology.h
+++ b/arch/powerpc/include/asm/topology.h
@@ -135,12 +135,8 @@ struct cpumask *cpu_coregroup_mask(int cpu);
 const struct cpumask *cpu_die_mask(int cpu);
 int cpu_die_id(int cpu);
 
-/*
- * Points to where the LLC is. On power9 this will point at CACHE
- * domain, On others it will point to SMT domain. In all cases
- * cpu_l2_cache_mask points to where LLC is
- */
-#define arch_llc_mask(cpu)     cpu_l2_cache_mask(cpu)
+const struct cpumask *arch_llc_mask(int cpu);
+#define arch_llc_mask arch_llc_mask
 
 #ifdef CONFIG_PPC64
 #include <asm/smp.h>
diff --git a/arch/powerpc/kernel/smp.c b/arch/powerpc/kernel/smp.c
index ca1821dedc98..4ece21abb1c4 100644
--- a/arch/powerpc/kernel/smp.c
+++ b/arch/powerpc/kernel/smp.c
@@ -1099,6 +1099,25 @@ static int __init set_llc_override(char *str)
 }
 __setup("llc_override=", set_llc_override);
 
+/*
+ * Points to where the LLC is. On power9 this will point at CACHE
+ * domain, On others it will point to SMT domain. In all cases
+ * cpu_l2_cache_mask points to where LLC is.
+ *
+ * If there is llc_override set, return the appropriate mask
+ */
+const struct cpumask *arch_llc_mask(int cpu)
+{
+	switch (READ_ONCE(llc_override)) {
+	case LLC_OVERRIDE_MC:
+		return cpu_coregroup_mask(cpu);
+	case LLC_OVERRIDE_PKG:
+		return cpu_node_mask(cpu);
+	default:
+		return cpu_l2_cache_mask(cpu);
+	}
+}
+
 static int __init init_big_cores(void)
 {
 	int cpu;
-- 
2.52.0

[PATCH v2 4/4] Documentation/powerpc: Add details about llc_override

[Shrikanth Hegde]

Provide documentation for the newly introduced llc_override kernel
parameter.

This may help one if they want to experiment with cache aware
scheduling on powerpc.

Signed-off-by: Shrikanth Hegde <sshegde@linux.ibm.com>
---
 Documentation/admin-guide/kernel-parameters.txt | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt
index fbee7b544903..e13514076c18 100644
--- a/Documentation/admin-guide/kernel-parameters.txt
+++ b/Documentation/admin-guide/kernel-parameters.txt
@@ -3568,6 +3568,21 @@ Kernel parameters
 			Enable Live Update Orchestrator (LUO).
 			Default: off.
 
+	llc_override=	[PPC] Override the scheduler-visible LLC domain.
+			Format: { mc | pkg }
+
+			Use the specified topology domain as the LLC domain
+			for scheduler decisions. This is intended for
+			experimenting with Cache Aware Scheduling.
+
+			mc	Use the MC domain as the LLC domain.
+			pkg	Use the package domain as the LLC domain.
+
+			If unset, use the platform-provided LLC topology.
+
+			This is a debug option only. It does not change the
+			hardware cache topology.
+
 	lockd.nlm_grace_period=P  [NFS] Assign grace period.
 			Format: <integer>
 
-- 
2.52.0