* [PATCH 1/9] arm64: dts: airoha: en7581: reorder nodes following incremental regs
2026-10-26 9:57 [PATCH 0/9] arm64: dts: airoha: en7581: cumulative nodes addition Christian Marangi
@ 2026-10-26 9:57 ` Christian Marangi
2026-10-26 9:57 ` [PATCH 2/9] arm64: dts: airoha: en7581: add CPU OPP and scaling nodes Christian Marangi
` (7 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Christian Marangi @ 2026-10-26 9:57 UTC (permalink / raw)
To: Matthias Brugger, AngeloGioacchino Del Regno, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Christian Marangi,
linux-arm-kernel, linux-mediatek, devicetree, linux-kernel
Reorder nods position following incremental register. This is to tidy
things up and no additional code is added.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
arch/arm64/boot/dts/airoha/en7581.dtsi | 246 ++++++++++++-------------
1 file changed, 123 insertions(+), 123 deletions(-)
diff --git a/arch/arm64/boot/dts/airoha/en7581.dtsi b/arch/arm64/boot/dts/airoha/en7581.dtsi
index ff6908a76e8e..83b30a340950 100644
--- a/arch/arm64/boot/dts/airoha/en7581.dtsi
+++ b/arch/arm64/boot/dts/airoha/en7581.dtsi
@@ -173,18 +173,6 @@ spi_nand: nand@0 {
};
};
- scuclk: clock-controller@1fb00000 {
- compatible = "airoha,en7581-scu";
- reg = <0x0 0x1fb00000 0x0 0x970>;
- #clock-cells = <1>;
- #reset-cells = <1>;
- };
-
- pbus_csr: syscon@1fbe3400 {
- compatible = "airoha,en7581-pbus-csr", "syscon";
- reg = <0x0 0x1fbe3400 0x0 0xff>;
- };
-
pciephy: phy@1fa5a000 {
compatible = "airoha,en7581-pcie-phy";
reg = <0x0 0x1fa5a000 0x0 0xfff>,
@@ -199,6 +187,129 @@ pciephy: phy@1fa5a000 {
#phy-cells = <0>;
};
+ rng@1faa1000 {
+ compatible = "airoha,en7581-trng";
+ reg = <0x0 0x1faa1000 0x0 0xc04>;
+ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ scuclk: clock-controller@1fb00000 {
+ compatible = "airoha,en7581-scu";
+ reg = <0x0 0x1fb00000 0x0 0x970>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ eth: ethernet@1fb50000 {
+ compatible = "airoha,en7581-eth";
+ reg = <0 0x1fb50000 0 0x2600>,
+ <0 0x1fb54000 0 0x2000>,
+ <0 0x1fb56000 0 0x2000>;
+ reg-names = "fe", "qdma0", "qdma1";
+
+ resets = <&scuclk EN7581_FE_RST>,
+ <&scuclk EN7581_FE_PDMA_RST>,
+ <&scuclk EN7581_FE_QDMA_RST>,
+ <&scuclk EN7581_XSI_MAC_RST>,
+ <&scuclk EN7581_DUAL_HSI0_MAC_RST>,
+ <&scuclk EN7581_DUAL_HSI1_MAC_RST>,
+ <&scuclk EN7581_HSI_MAC_RST>,
+ <&scuclk EN7581_XFP_MAC_RST>;
+ reset-names = "fe", "pdma", "qdma",
+ "xsi-mac", "hsi0-mac", "hsi1-mac",
+ "hsi-mac", "xfp-mac";
+
+ interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
+
+ status = "disabled";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gdm1: ethernet@1 {
+ compatible = "airoha,eth-mac";
+ reg = <1>;
+ phy-mode = "internal";
+ status = "disabled";
+
+ fixed-link {
+ speed = <10000>;
+ full-duplex;
+ pause;
+ };
+ };
+ };
+
+ pbus_csr: syscon@1fbe3400 {
+ compatible = "airoha,en7581-pbus-csr", "syscon";
+ reg = <0x0 0x1fbe3400 0x0 0xff>;
+ };
+
+ uart1: serial@1fbf0000 {
+ compatible = "ns16550";
+ reg = <0x0 0x1fbf0000 0x0 0x30>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <1843200>;
+ };
+
+ system-controller@1fbf0200 {
+ compatible = "airoha,en7581-gpio-sysctl", "syscon",
+ "simple-mfd";
+ reg = <0x0 0x1fbf0200 0x0 0xc0>;
+
+ en7581_pinctrl: pinctrl {
+ compatible = "airoha,en7581-pinctrl";
+
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ i2c0: i2c@1fbf8000 {
+ compatible = "mediatek,mt7621-i2c";
+ reg = <0x0 0x1fbf8000 0x0 0x100>;
+
+ resets = <&scuclk EN7581_I2C2_RST>;
+
+ clocks = <&clk20m>;
+ clock-frequency = <100000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ i2c1: i2c@1fbf8100 {
+ compatible = "mediatek,mt7621-i2c";
+ reg = <0x0 0x1fbf8100 0x0 0x100>;
+
+ resets = <&scuclk EN7581_I2C_MASTER_RST>;
+
+ clocks = <&clk20m>;
+ clock-frequency = <100000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
pcie0: pcie@1fc00000 {
compatible = "airoha,en7581-pcie";
device_type = "pci";
@@ -284,116 +395,5 @@ pcie_intc1: interrupt-controller {
#interrupt-cells = <1>;
};
};
-
- uart1: serial@1fbf0000 {
- compatible = "ns16550";
- reg = <0x0 0x1fbf0000 0x0 0x30>;
- reg-io-width = <4>;
- reg-shift = <2>;
- interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
- clock-frequency = <1843200>;
- };
-
- rng@1faa1000 {
- compatible = "airoha,en7581-trng";
- reg = <0x0 0x1faa1000 0x0 0xc04>;
- interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- system-controller@1fbf0200 {
- compatible = "airoha,en7581-gpio-sysctl", "syscon",
- "simple-mfd";
- reg = <0x0 0x1fbf0200 0x0 0xc0>;
-
- en7581_pinctrl: pinctrl {
- compatible = "airoha,en7581-pinctrl";
-
- interrupt-parent = <&gic>;
- interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
-
- gpio-controller;
- #gpio-cells = <2>;
-
- interrupt-controller;
- #interrupt-cells = <2>;
- };
- };
-
- i2c0: i2c@1fbf8000 {
- compatible = "mediatek,mt7621-i2c";
- reg = <0x0 0x1fbf8000 0x0 0x100>;
-
- resets = <&scuclk EN7581_I2C2_RST>;
-
- clocks = <&clk20m>;
- clock-frequency = <100000>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- status = "disabled";
- };
-
- i2c1: i2c@1fbf8100 {
- compatible = "mediatek,mt7621-i2c";
- reg = <0x0 0x1fbf8100 0x0 0x100>;
-
- resets = <&scuclk EN7581_I2C_MASTER_RST>;
-
- clocks = <&clk20m>;
- clock-frequency = <100000>;
- #address-cells = <1>;
- #size-cells = <0>;
-
- status = "disabled";
- };
-
- eth: ethernet@1fb50000 {
- compatible = "airoha,en7581-eth";
- reg = <0 0x1fb50000 0 0x2600>,
- <0 0x1fb54000 0 0x2000>,
- <0 0x1fb56000 0 0x2000>;
- reg-names = "fe", "qdma0", "qdma1";
-
- resets = <&scuclk EN7581_FE_RST>,
- <&scuclk EN7581_FE_PDMA_RST>,
- <&scuclk EN7581_FE_QDMA_RST>,
- <&scuclk EN7581_XSI_MAC_RST>,
- <&scuclk EN7581_DUAL_HSI0_MAC_RST>,
- <&scuclk EN7581_DUAL_HSI1_MAC_RST>,
- <&scuclk EN7581_HSI_MAC_RST>,
- <&scuclk EN7581_XFP_MAC_RST>;
- reset-names = "fe", "pdma", "qdma",
- "xsi-mac", "hsi0-mac", "hsi1-mac",
- "hsi-mac", "xfp-mac";
-
- interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
-
- status = "disabled";
-
- #address-cells = <1>;
- #size-cells = <0>;
-
- gdm1: ethernet@1 {
- compatible = "airoha,eth-mac";
- reg = <1>;
- phy-mode = "internal";
- status = "disabled";
-
- fixed-link {
- speed = <10000>;
- full-duplex;
- pause;
- };
- };
- };
};
};
--
2.55.0
^ permalink raw reply [flat|nested] 10+ messages in thread* [PATCH 2/9] arm64: dts: airoha: en7581: add CPU OPP and scaling nodes
2026-10-26 9:57 [PATCH 0/9] arm64: dts: airoha: en7581: cumulative nodes addition Christian Marangi
2026-10-26 9:57 ` [PATCH 1/9] arm64: dts: airoha: en7581: reorder nodes following incremental regs Christian Marangi
@ 2026-10-26 9:57 ` Christian Marangi
2026-10-26 9:57 ` [PATCH 3/9] arm64: dts: airoha: en7581: add Chip-SCU accessor node Christian Marangi
` (6 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Christian Marangi @ 2026-10-26 9:57 UTC (permalink / raw)
To: Matthias Brugger, AngeloGioacchino Del Regno, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Christian Marangi,
linux-arm-kernel, linux-mediatek, devicetree, linux-kernel
Add required CPU OPP and PD nodes to support CPU frequency scaling.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
arch/arm64/boot/dts/airoha/en7581.dtsi | 177 ++++++++++++++++++++++++-
1 file changed, 173 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/airoha/en7581.dtsi b/arch/arm64/boot/dts/airoha/en7581.dtsi
index 83b30a340950..c5a335086741 100644
--- a/arch/arm64/boot/dts/airoha/en7581.dtsi
+++ b/arch/arm64/boot/dts/airoha/en7581.dtsi
@@ -74,8 +74,12 @@ cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0>;
+ operating-points-v2 = <&cpu_opp_table>;
enable-method = "psci";
- clock-frequency = <80000000>;
+ clocks = <&cpufreq>;
+ clock-names = "cpu";
+ power-domains = <&cpufreq>;
+ power-domain-names = "perf";
next-level-cache = <&l2>;
};
@@ -83,8 +87,12 @@ cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x1>;
+ operating-points-v2 = <&cpu_opp_table>;
enable-method = "psci";
- clock-frequency = <80000000>;
+ clocks = <&cpufreq>;
+ clock-names = "cpu";
+ power-domains = <&cpufreq>;
+ power-domain-names = "perf";
next-level-cache = <&l2>;
};
@@ -92,8 +100,12 @@ cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x2>;
+ operating-points-v2 = <&cpu_opp_table>;
enable-method = "psci";
- clock-frequency = <80000000>;
+ clocks = <&cpufreq>;
+ clock-names = "cpu";
+ power-domains = <&cpufreq>;
+ power-domain-names = "perf";
next-level-cache = <&l2>;
};
@@ -101,8 +113,12 @@ cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x3>;
+ operating-points-v2 = <&cpu_opp_table>;
enable-method = "psci";
- clock-frequency = <80000000>;
+ clocks = <&cpufreq>;
+ clock-names = "cpu";
+ power-domains = <&cpufreq>;
+ power-domain-names = "perf";
next-level-cache = <&l2>;
};
@@ -115,6 +131,159 @@ l2: l2-cache {
};
};
+ cpufreq: cpufreq {
+ compatible = "airoha,en7581-cpufreq";
+
+ operating-points-v2 = <&cpu_smcc_opp_table>;
+
+ #power-domain-cells = <0>;
+ #clock-cells = <0>;
+ };
+
+ cpu_opp_table: opp-table {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ required-opps = <&smcc_opp0>;
+ };
+
+ opp-550000000 {
+ opp-hz = /bits/ 64 <550000000>;
+ required-opps = <&smcc_opp1>;
+ };
+
+ opp-600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ required-opps = <&smcc_opp2>;
+ };
+
+ opp-650000000 {
+ opp-hz = /bits/ 64 <650000000>;
+ required-opps = <&smcc_opp3>;
+ };
+
+ opp-700000000 {
+ opp-hz = /bits/ 64 <700000000>;
+ required-opps = <&smcc_opp4>;
+ };
+
+ opp-750000000 {
+ opp-hz = /bits/ 64 <750000000>;
+ required-opps = <&smcc_opp5>;
+ };
+
+ opp-800000000 {
+ opp-hz = /bits/ 64 <800000000>;
+ required-opps = <&smcc_opp6>;
+ };
+
+ opp-850000000 {
+ opp-hz = /bits/ 64 <850000000>;
+ required-opps = <&smcc_opp7>;
+ };
+
+ opp-900000000 {
+ opp-hz = /bits/ 64 <900000000>;
+ required-opps = <&smcc_opp8>;
+ };
+
+ opp-950000000 {
+ opp-hz = /bits/ 64 <950000000>;
+ required-opps = <&smcc_opp9>;
+ };
+
+ opp-1000000000 {
+ opp-hz = /bits/ 64 <1000000000>;
+ required-opps = <&smcc_opp10>;
+ };
+
+ opp-1050000000 {
+ opp-hz = /bits/ 64 <1050000000>;
+ required-opps = <&smcc_opp11>;
+ };
+
+ opp-1100000000 {
+ opp-hz = /bits/ 64 <1100000000>;
+ required-opps = <&smcc_opp12>;
+ };
+
+ opp-1150000000 {
+ opp-hz = /bits/ 64 <1150000000>;
+ required-opps = <&smcc_opp13>;
+ };
+
+ opp-1200000000 {
+ opp-hz = /bits/ 64 <1200000000>;
+ required-opps = <&smcc_opp14>;
+ };
+ };
+
+ cpu_smcc_opp_table: opp-table-smcc {
+ compatible = "operating-points-v2";
+
+ smcc_opp0: opp-0 {
+ opp-level = <0>;
+ };
+
+ smcc_opp1: opp-1 {
+ opp-level = <1>;
+ };
+
+ smcc_opp2: opp-2 {
+ opp-level = <2>;
+ };
+
+ smcc_opp3: opp-3 {
+ opp-level = <3>;
+ };
+
+ smcc_opp4: opp-4 {
+ opp-level = <4>;
+ };
+
+ smcc_opp5: opp-5 {
+ opp-level = <5>;
+ };
+
+ smcc_opp6: opp-6 {
+ opp-level = <6>;
+ };
+
+ smcc_opp7: opp-7 {
+ opp-level = <7>;
+ };
+
+ smcc_opp8: opp-8 {
+ opp-level = <8>;
+ };
+
+ smcc_opp9: opp-9 {
+ opp-level = <9>;
+ };
+
+ smcc_opp10: opp-10 {
+ opp-level = <10>;
+ };
+
+ smcc_opp11: opp-11 {
+ opp-level = <11>;
+ };
+
+ smcc_opp12: opp-12 {
+ opp-level = <12>;
+ };
+
+ smcc_opp13: opp-13 {
+ opp-level = <13>;
+ };
+
+ smcc_opp14: opp-14 {
+ opp-level = <14>;
+ };
+ };
+
timer {
compatible = "arm,armv8-timer";
interrupt-parent = <&gic>;
--
2.55.0
^ permalink raw reply [flat|nested] 10+ messages in thread* [PATCH 3/9] arm64: dts: airoha: en7581: add Chip-SCU accessor node
2026-10-26 9:57 [PATCH 0/9] arm64: dts: airoha: en7581: cumulative nodes addition Christian Marangi
2026-10-26 9:57 ` [PATCH 1/9] arm64: dts: airoha: en7581: reorder nodes following incremental regs Christian Marangi
2026-10-26 9:57 ` [PATCH 2/9] arm64: dts: airoha: en7581: add CPU OPP and scaling nodes Christian Marangi
@ 2026-10-26 9:57 ` Christian Marangi
2026-10-26 9:57 ` [PATCH 4/9] arm64: dts: airoha: en7581: add thermal sensor nodes Christian Marangi
` (5 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Christian Marangi @ 2026-10-26 9:57 UTC (permalink / raw)
To: Matthias Brugger, AngeloGioacchino Del Regno, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Christian Marangi,
linux-arm-kernel, linux-mediatek, devicetree, linux-kernel
Add Chip-SCU accessor node as a companion of the SCU node to permit
additional configuration for clock, MUX and thermal related registers.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
arch/arm64/boot/dts/airoha/en7581.dtsi | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/airoha/en7581.dtsi b/arch/arm64/boot/dts/airoha/en7581.dtsi
index c5a335086741..fbc5ee47523c 100644
--- a/arch/arm64/boot/dts/airoha/en7581.dtsi
+++ b/arch/arm64/boot/dts/airoha/en7581.dtsi
@@ -342,6 +342,11 @@ spi_nand: nand@0 {
};
};
+ chip_scu: syscon@1fa20000 {
+ compatible = "airoha,en7581-chip-scu", "syscon";
+ reg = <0x0 0x1fa20000 0x0 0x388>;
+ };
+
pciephy: phy@1fa5a000 {
compatible = "airoha,en7581-pcie-phy";
reg = <0x0 0x1fa5a000 0x0 0xfff>,
--
2.55.0
^ permalink raw reply [flat|nested] 10+ messages in thread* [PATCH 4/9] arm64: dts: airoha: en7581: add thermal sensor nodes
2026-10-26 9:57 [PATCH 0/9] arm64: dts: airoha: en7581: cumulative nodes addition Christian Marangi
` (2 preceding siblings ...)
2026-10-26 9:57 ` [PATCH 3/9] arm64: dts: airoha: en7581: add Chip-SCU accessor node Christian Marangi
@ 2026-10-26 9:57 ` Christian Marangi
2026-10-26 9:57 ` [PATCH 5/9] arm64: dts: airoha: en7581: add watchdog node Christian Marangi
` (4 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Christian Marangi @ 2026-10-26 9:57 UTC (permalink / raw)
To: Matthias Brugger, AngeloGioacchino Del Regno, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Christian Marangi,
linux-arm-kernel, linux-mediatek, devicetree, linux-kernel
Add thermal sensor nodes and attach them to the CPU node to control passive
throttle and define critical temperature of the SoC.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
arch/arm64/boot/dts/airoha/en7581.dtsi | 47 ++++++++++++++++++++++++++
1 file changed, 47 insertions(+)
diff --git a/arch/arm64/boot/dts/airoha/en7581.dtsi b/arch/arm64/boot/dts/airoha/en7581.dtsi
index fbc5ee47523c..58bd8b318910 100644
--- a/arch/arm64/boot/dts/airoha/en7581.dtsi
+++ b/arch/arm64/boot/dts/airoha/en7581.dtsi
@@ -4,6 +4,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/en7523-clk.h>
#include <dt-bindings/reset/airoha,en7581-reset.h>
+#include <dt-bindings/thermal/thermal.h>
/ {
interrupt-parent = <&gic>;
@@ -81,6 +82,7 @@ cpu0: cpu@0 {
power-domains = <&cpufreq>;
power-domain-names = "perf";
next-level-cache = <&l2>;
+ #cooling-cells = <2>;
};
cpu1: cpu@1 {
@@ -94,6 +96,7 @@ cpu1: cpu@1 {
power-domains = <&cpufreq>;
power-domain-names = "perf";
next-level-cache = <&l2>;
+ #cooling-cells = <2>;
};
cpu2: cpu@2 {
@@ -107,6 +110,7 @@ cpu2: cpu@2 {
power-domains = <&cpufreq>;
power-domain-names = "perf";
next-level-cache = <&l2>;
+ #cooling-cells = <2>;
};
cpu3: cpu@3 {
@@ -120,6 +124,7 @@ cpu3: cpu@3 {
power-domains = <&cpufreq>;
power-domain-names = "perf";
next-level-cache = <&l2>;
+ #cooling-cells = <2>;
};
l2: l2-cache {
@@ -293,6 +298,39 @@ timer {
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
};
+ thermal-zones {
+ cpu_thermal: cpu-thermal {
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+
+ thermal-sensors = <&thermal 0>;
+
+ trips {
+ cpu_hot: cpu-hot {
+ temperature = <95000>;
+ hysteresis = <1000>;
+ type = "hot";
+ };
+
+ cpu-critical {
+ temperature = <120000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu_hot>;
+ cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+ <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ };
+ };
+ };
+ };
+
clk20m: clock-20000000 {
compatible = "fixed-clock";
#clock-cells = <0>;
@@ -319,6 +357,15 @@ gic: interrupt-controller@9000000 {
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
};
+ thermal: thermal-sensor@1efbd000 {
+ compatible = "airoha,en7581-thermal";
+ reg = <0x0 0x1efbd000 0x0 0xd5c>;
+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+ airoha,chip-scu = <&chip_scu>;
+
+ #thermal-sensor-cells = <0>;
+ };
+
spi@1fa10000 {
compatible = "airoha,en7581-snand";
reg = <0x0 0x1fa10000 0x0 0x140>,
--
2.55.0
^ permalink raw reply [flat|nested] 10+ messages in thread* [PATCH 5/9] arm64: dts: airoha: en7581: add watchdog node
2026-10-26 9:57 [PATCH 0/9] arm64: dts: airoha: en7581: cumulative nodes addition Christian Marangi
` (3 preceding siblings ...)
2026-10-26 9:57 ` [PATCH 4/9] arm64: dts: airoha: en7581: add thermal sensor nodes Christian Marangi
@ 2026-10-26 9:57 ` Christian Marangi
2026-10-26 9:57 ` [PATCH 6/9] arm64: dts: airoha: en7581: add PWM node Christian Marangi
` (3 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Christian Marangi @ 2026-10-26 9:57 UTC (permalink / raw)
To: Matthias Brugger, AngeloGioacchino Del Regno, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Christian Marangi,
linux-arm-kernel, linux-mediatek, devicetree, linux-kernel
Add watchdog node to catch stall and correctly reboot the system.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
arch/arm64/boot/dts/airoha/en7581.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/airoha/en7581.dtsi b/arch/arm64/boot/dts/airoha/en7581.dtsi
index 58bd8b318910..3a4a4fb0eba9 100644
--- a/arch/arm64/boot/dts/airoha/en7581.dtsi
+++ b/arch/arm64/boot/dts/airoha/en7581.dtsi
@@ -484,6 +484,14 @@ uart1: serial@1fbf0000 {
clock-frequency = <1843200>;
};
+ watchdog@1fbf0100 {
+ compatible = "airoha,en7581-wdt";
+ reg = <0x0 0x1fbf0100 0x0 0x38>;
+
+ clocks = <&scuclk EN7523_CLK_BUS>;
+ clock-names = "bus";
+ };
+
system-controller@1fbf0200 {
compatible = "airoha,en7581-gpio-sysctl", "syscon",
"simple-mfd";
--
2.55.0
^ permalink raw reply [flat|nested] 10+ messages in thread* [PATCH 6/9] arm64: dts: airoha: en7581: add PWM node
2026-10-26 9:57 [PATCH 0/9] arm64: dts: airoha: en7581: cumulative nodes addition Christian Marangi
` (4 preceding siblings ...)
2026-10-26 9:57 ` [PATCH 5/9] arm64: dts: airoha: en7581: add watchdog node Christian Marangi
@ 2026-10-26 9:57 ` Christian Marangi
2026-10-26 9:57 ` [PATCH 7/9] arm64: dts: airoha: en7581: add nodes for all supported uart and hsuart Christian Marangi
` (2 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Christian Marangi @ 2026-10-26 9:57 UTC (permalink / raw)
To: Matthias Brugger, AngeloGioacchino Del Regno, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Christian Marangi,
linux-arm-kernel, linux-mediatek, devicetree, linux-kernel
Add PWM node to control all status leds generally attached to Vendor
boards.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
arch/arm64/boot/dts/airoha/en7581.dtsi | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm64/boot/dts/airoha/en7581.dtsi b/arch/arm64/boot/dts/airoha/en7581.dtsi
index 3a4a4fb0eba9..760f0c3e6090 100644
--- a/arch/arm64/boot/dts/airoha/en7581.dtsi
+++ b/arch/arm64/boot/dts/airoha/en7581.dtsi
@@ -509,6 +509,12 @@ en7581_pinctrl: pinctrl {
interrupt-controller;
#interrupt-cells = <2>;
};
+
+ en7581_pwm: pwm {
+ compatible = "airoha,en7581-pwm";
+
+ #pwm-cells = <3>;
+ };
};
i2c0: i2c@1fbf8000 {
--
2.55.0
^ permalink raw reply [flat|nested] 10+ messages in thread* [PATCH 7/9] arm64: dts: airoha: en7581: add nodes for all supported uart and hsuart
2026-10-26 9:57 [PATCH 0/9] arm64: dts: airoha: en7581: cumulative nodes addition Christian Marangi
` (5 preceding siblings ...)
2026-10-26 9:57 ` [PATCH 6/9] arm64: dts: airoha: en7581: add PWM node Christian Marangi
@ 2026-10-26 9:57 ` Christian Marangi
2026-10-26 9:57 ` [PATCH 8/9] arm64: dts: airoha: en7581: add crypto node Christian Marangi
2026-10-26 9:57 ` [PATCH 9/9] arm64: dts: airoha: en7581: add integrated switch node Christian Marangi
8 siblings, 0 replies; 10+ messages in thread
From: Christian Marangi @ 2026-10-26 9:57 UTC (permalink / raw)
To: Matthias Brugger, AngeloGioacchino Del Regno, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Christian Marangi,
linux-arm-kernel, linux-mediatek, devicetree, linux-kernel
Add all the nodes to support the existing uart and hsuart present on the
SoC. Also update the compatible for the already defined uart to use the
more specific UART configuration.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
arch/arm64/boot/dts/airoha/en7581.dtsi | 46 +++++++++++++++++++++++++-
1 file changed, 45 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/airoha/en7581.dtsi b/arch/arm64/boot/dts/airoha/en7581.dtsi
index 760f0c3e6090..ee1633f01068 100644
--- a/arch/arm64/boot/dts/airoha/en7581.dtsi
+++ b/arch/arm64/boot/dts/airoha/en7581.dtsi
@@ -470,13 +470,24 @@ fixed-link {
};
};
+ serial@1fbe1000 {
+ compatible = "airoha,an7581-hsuart";
+ reg = <0x0 0x1fbe1000 0x0 0x40>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <7372800>;
+
+ status = "disabled";
+ };
+
pbus_csr: syscon@1fbe3400 {
compatible = "airoha,en7581-pbus-csr", "syscon";
reg = <0x0 0x1fbe3400 0x0 0xff>;
};
uart1: serial@1fbf0000 {
- compatible = "ns16550";
+ compatible = "airoha,en7523-uart";
reg = <0x0 0x1fbf0000 0x0 0x30>;
reg-io-width = <4>;
reg-shift = <2>;
@@ -517,6 +528,39 @@ en7581_pwm: pwm {
};
};
+ serial@1fbf0300 {
+ compatible = "airoha,en7523-uart";
+ reg = <0x0 0x1fbf0300 0x0 0x30>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <7372800>;
+
+ status = "disabled";
+ };
+
+ serial@1fbf0600 {
+ compatible = "airoha,en7523-uart";
+ reg = <0x0 0x1fbf0600 0x0 0x30>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <7372800>;
+
+ status = "disabled";
+ };
+
+ serial@1fbf0700 {
+ compatible = "airoha,en7523-uart";
+ reg = <0x0 0x1fbf0700 0x0 0x30>;
+ reg-io-width = <4>;
+ reg-shift = <2>;
+ interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+ clock-frequency = <7372800>;
+
+ status = "disabled";
+ };
+
i2c0: i2c@1fbf8000 {
compatible = "mediatek,mt7621-i2c";
reg = <0x0 0x1fbf8000 0x0 0x100>;
--
2.55.0
^ permalink raw reply [flat|nested] 10+ messages in thread* [PATCH 8/9] arm64: dts: airoha: en7581: add crypto node
2026-10-26 9:57 [PATCH 0/9] arm64: dts: airoha: en7581: cumulative nodes addition Christian Marangi
` (6 preceding siblings ...)
2026-10-26 9:57 ` [PATCH 7/9] arm64: dts: airoha: en7581: add nodes for all supported uart and hsuart Christian Marangi
@ 2026-10-26 9:57 ` Christian Marangi
2026-10-26 9:57 ` [PATCH 9/9] arm64: dts: airoha: en7581: add integrated switch node Christian Marangi
8 siblings, 0 replies; 10+ messages in thread
From: Christian Marangi @ 2026-10-26 9:57 UTC (permalink / raw)
To: Matthias Brugger, AngeloGioacchino Del Regno, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Christian Marangi,
linux-arm-kernel, linux-mediatek, devicetree, linux-kernel
Add crypto node to support the integrated Inside Secure SafeXcel EIP93.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
arch/arm64/boot/dts/airoha/en7581.dtsi | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/airoha/en7581.dtsi b/arch/arm64/boot/dts/airoha/en7581.dtsi
index ee1633f01068..f214fa3a3e2b 100644
--- a/arch/arm64/boot/dts/airoha/en7581.dtsi
+++ b/arch/arm64/boot/dts/airoha/en7581.dtsi
@@ -470,6 +470,13 @@ fixed-link {
};
};
+ crypto@1fb70000 {
+ compatible = "airoha,en7581-eip93", "inside-secure,safexcel-eip93ies";
+ reg = <0x0 0x1fb70000 0x0 0x1000>;
+
+ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
serial@1fbe1000 {
compatible = "airoha,an7581-hsuart";
reg = <0x0 0x1fbe1000 0x0 0x40>;
--
2.55.0
^ permalink raw reply [flat|nested] 10+ messages in thread* [PATCH 9/9] arm64: dts: airoha: en7581: add integrated switch node
2026-10-26 9:57 [PATCH 0/9] arm64: dts: airoha: en7581: cumulative nodes addition Christian Marangi
` (7 preceding siblings ...)
2026-10-26 9:57 ` [PATCH 8/9] arm64: dts: airoha: en7581: add crypto node Christian Marangi
@ 2026-10-26 9:57 ` Christian Marangi
8 siblings, 0 replies; 10+ messages in thread
From: Christian Marangi @ 2026-10-26 9:57 UTC (permalink / raw)
To: Matthias Brugger, AngeloGioacchino Del Regno, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Christian Marangi,
linux-arm-kernel, linux-mediatek, devicetree, linux-kernel
Add the integrated switch node complete of the internal PHY with the PHY
address and the supported leds attached.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
arch/arm64/boot/dts/airoha/en7581.dtsi | 147 +++++++++++++++++++++++++
1 file changed, 147 insertions(+)
diff --git a/arch/arm64/boot/dts/airoha/en7581.dtsi b/arch/arm64/boot/dts/airoha/en7581.dtsi
index f214fa3a3e2b..83ae41271f96 100644
--- a/arch/arm64/boot/dts/airoha/en7581.dtsi
+++ b/arch/arm64/boot/dts/airoha/en7581.dtsi
@@ -4,6 +4,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/en7523-clk.h>
#include <dt-bindings/reset/airoha,en7581-reset.h>
+#include <dt-bindings/leds/common.h>
#include <dt-bindings/thermal/thermal.h>
/ {
@@ -470,6 +471,152 @@ fixed-link {
};
};
+ switch: switch@1fb58000 {
+ compatible = "airoha,en7581-switch";
+ reg = <0 0x1fb58000 0 0x8000>;
+ resets = <&scuclk EN7581_GSW_RST>;
+
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+
+ status = "disabled";
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gsw_port1: port@1 {
+ reg = <1>;
+ phy-mode = "internal";
+ phy-handle = <&gsw_phy1>;
+ };
+
+ gsw_port2: port@2 {
+ reg = <2>;
+ phy-mode = "internal";
+ phy-handle = <&gsw_phy2>;
+ };
+
+ gsw_port3: port@3 {
+ reg = <3>;
+ phy-mode = "internal";
+ phy-handle = <&gsw_phy3>;
+ };
+
+ gsw_port4: port@4 {
+ reg = <4>;
+ phy-mode = "internal";
+ phy-handle = <&gsw_phy4>;
+ };
+
+ port@6 {
+ reg = <6>;
+ ethernet = <&gdm1>;
+ phy-mode = "internal";
+
+ fixed-link {
+ speed = <10000>;
+ full-duplex;
+ pause;
+ };
+ };
+ };
+
+ mdio: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gsw_phy1: ethernet-phy@9 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <9>;
+ phy-mode = "internal";
+
+ leds {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gsw_phy1_led0: led@0 {
+ reg = <0>;
+ status = "disabled";
+ };
+
+ gsw_phy1_led1: led@1 {
+ reg = <1>;
+ status = "disabled";
+ };
+ };
+ };
+
+ gsw_phy2: ethernet-phy@a {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <10>;
+ phy-mode = "internal";
+
+ leds {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gsw_phy2_led0: led@0 {
+ reg = <0>;
+ status = "disabled";
+ };
+
+ gsw_phy2_led1: led@1 {
+ reg = <1>;
+ status = "disabled";
+ };
+ };
+ };
+
+ gsw_phy3: ethernet-phy@b {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <11>;
+ phy-mode = "internal";
+
+ leds {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gsw_phy3_led0: led@0 {
+ reg = <0>;
+ status = "disabled";
+ };
+
+ gsw_phy3_led1: led@1 {
+ reg = <1>;
+ status = "disabled";
+ };
+ };
+ };
+
+ gsw_phy4: ethernet-phy@c {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <12>;
+ phy-mode = "internal";
+
+ leds {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gsw_phy4_led0: led@0 {
+ reg = <0>;
+ status = "disabled";
+ };
+
+ gsw_phy4_led1: led@1 {
+ reg = <1>;
+ status = "disabled";
+ };
+ };
+ };
+ };
+ };
+
crypto@1fb70000 {
compatible = "airoha,en7581-eip93", "inside-secure,safexcel-eip93ies";
reg = <0x0 0x1fb70000 0x0 0x1000>;
--
2.55.0
^ permalink raw reply [flat|nested] 10+ messages in thread