* [PATCH v2 1/9] perf jevents: Add support for NVIDIA Tegra410 UCF PMU aliasing
2026-10-30 17:48 [PATCH v2 0/9] perf: Add NVIDIA Tegra410 uncore PMU events and metrics Besar Wicaksono
@ 2026-10-30 17:48 ` Besar Wicaksono
2026-10-30 17:48 ` [PATCH v2 2/9] perf jevents: Add support for NVIDIA Tegra410 PCIE " Besar Wicaksono
` (8 subsequent siblings)
9 siblings, 0 replies; 12+ messages in thread
From: Besar Wicaksono @ 2026-10-30 17:48 UTC (permalink / raw)
To: acme, namhyung, irogers, ctshao
Cc: linux-tegra, linux-arm-kernel, linux-perf-users, linux-kernel,
vsethi, rwiley, skelley, mochs, rajjoshi, treding, jonathanh,
john.garry, will, james.clark, mike.leach, leo.yan, mark.rutland,
alexander.shishkin, jolsa, adrian.hunter, Besar Wicaksono
Add alias support for NVIDIA Tegra410 UCF PMU events and metrics.
Signed-off-by: Besar Wicaksono <bwicaksono@nvidia.com>
---
.../arch/arm64/nvidia/t410/uncore-ucf.json | 764 ++++++++++++++++++
1 file changed, 764 insertions(+)
create mode 100644 tools/perf/pmu-events/arch/arm64/nvidia/t410/uncore-ucf.json
diff --git a/tools/perf/pmu-events/arch/arm64/nvidia/t410/uncore-ucf.json b/tools/perf/pmu-events/arch/arm64/nvidia/t410/uncore-ucf.json
new file mode 100644
index 000000000000..9cb964f7c53d
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/nvidia/t410/uncore-ucf.json
@@ -0,0 +1,764 @@
+[
+ {
+ "EventCode": "0x100000000",
+ "EventName": "UCF_CYCLES",
+ "BriefDescription": "Counts UCF cycles using the dedicated PMU cycle counter.",
+ "PublicDescription": "Counts UCF cycles using the PMU's dedicated cycle counter.",
+ "Unit": "nvidia_ucf_pmu_"
+ },
+ {
+ "EventCode": "0x1d",
+ "EventName": "UCF_BUS_CYCLES",
+ "BriefDescription": "Counts UCF cycles using a programmable event counter.",
+ "PublicDescription": "Counts UCF cycles using a programmable event counter. The count is identical to UCF_CYCLES. Source and destination filters are ignored.",
+ "Unit": "nvidia_ucf_pmu_"
+ },
+ {
+ "EventCode": "0x111",
+ "EventName": "UCF_SLC_ACCESS_RD",
+ "BriefDescription": "Counts read requests from a requester to the SLC.",
+ "PublicDescription": "Counts read requests from a requester to the SLC. A read is a request for which the completer returns data: dataless MakeReadUnique and snoop requests are not reads, and prefetches issued by the cores' L1/L2 caches count as reads rather than as prefetch requests. Filters: src_loc_cpu, src_loc_noncpu and src_rem select the request initiator: local CPU, local non-CPU device or remote socket. dst_loc_cmem, dst_loc_gmem, dst_loc_other and dst_rem select the memory type of the request address: local CMEM, local GMEM, local CXL memory or remote memory; local or remote is determined by the home socket of the address. An unset group counts all.",
+ "Unit": "nvidia_ucf_pmu_"
+ },
+ {
+ "EventCode": "0x112",
+ "EventName": "UCF_SLC_ACCESS_WR",
+ "BriefDescription": "Counts write requests from a requester to the SLC.",
+ "PublicDescription": "Counts write requests from a requester to the SLC. A write is a request in which the requester sends data: dataless WriteEvictOrEvict is not a write, and CHI Write*Zero is a write because it eventually consumes DRAM bandwidth although it sends no data over the interface. Filters: src_loc_cpu, src_loc_noncpu and src_rem select the request initiator: local CPU, local non-CPU device or remote socket. dst_loc_cmem, dst_loc_gmem, dst_loc_other and dst_rem select the memory type of the request address: local CMEM, local GMEM, local CXL memory or remote memory; local or remote is determined by the home socket of the address. An unset group counts all.",
+ "Unit": "nvidia_ucf_pmu_"
+ },
+ {
+ "EventCode": "0x183",
+ "EventName": "UCF_SLC_ACCESS_DATALESS",
+ "BriefDescription": "Counts CHI Dataless requests to the SLC.",
+ "PublicDescription": "Counts CHI Dataless requests to the SLC. Dataless MakeReadUnique and WriteEvictOrEvict requests are not counted. Filters: src_loc_cpu, src_loc_noncpu and src_rem select the request initiator: local CPU, local non-CPU device or remote socket. dst_loc_cmem, dst_loc_gmem, dst_loc_other and dst_rem select the memory type of the request address: local CMEM, local GMEM, local CXL memory or remote memory; local or remote is determined by the home socket of the address. An unset group counts all.",
+ "Unit": "nvidia_ucf_pmu_"
+ },
+ {
+ "EventCode": "0x184",
+ "EventName": "UCF_SLC_ACCESS_ATOMIC",
+ "BriefDescription": "Counts CHI Atomic requests to the SLC.",
+ "PublicDescription": "Counts CHI Atomic requests to the SLC. Filters: src_loc_cpu, src_loc_noncpu and src_rem select the request initiator: local CPU, local non-CPU device or remote socket. dst_loc_cmem, dst_loc_gmem, dst_loc_other and dst_rem select the memory type of the request address: local CMEM, local GMEM, local CXL memory or remote memory; local or remote is determined by the home socket of the address. An unset group counts all.",
+ "Unit": "nvidia_ucf_pmu_"
+ },
+ {
+ "EventCode": "0x113",
+ "EventName": "UCF_SLC_BYTES_RD",
+ "BriefDescription": "Counts bytes transferred by the read requests counted by UCF_SLC_ACCESS_RD.",
+ "PublicDescription": "Counts the bytes transferred by the read requests counted by UCF_SLC_ACCESS_RD, including read data sent by Direct Memory Transfer (DMT) or Direct Cache Transfer (DCT). For transfers of an odd number of bytes, the count is rounded to the nearest power of 2 greater than the bytes transferred. Because reads can be smaller than 64 bytes, the count may not equal UCF_SLC_ACCESS_RD times 64. Source and destination filters work as described for UCF_SLC_ACCESS_RD.",
+ "Unit": "nvidia_ucf_pmu_"
+ },
+ {
+ "EventCode": "0x114",
+ "EventName": "UCF_SLC_BYTES_WR",
+ "BriefDescription": "Counts bytes transferred by the write requests counted by UCF_SLC_ACCESS_WR.",
+ "PublicDescription": "Counts the bytes transferred by the write requests counted by UCF_SLC_ACCESS_WR, including write data sent by Direct Write Transfer (DWT). For transfers of an odd number of bytes, the count is rounded to the nearest power of 2. Data returned to the SLC by a requester's cache in response to a snoop is not counted. Because writes can be smaller than 64 bytes, the count may not equal UCF_SLC_ACCESS_WR times 64. Source and destination filters work as described for UCF_SLC_ACCESS_WR.",
+ "Unit": "nvidia_ucf_pmu_"
+ },
+ {
+ "EventCode": "0x119",
+ "EventName": "UCF_SLC_HIT_RD",
+ "BriefDescription": "Counts inbound read requests that hit in the SLC's L3 cache or in a peer requester cache.",
+ "PublicDescription": "Counts inbound read requests that hit in the SLC's L3 cache or in a peer requester cache, including one in a remote socket. Some hits are still refilled from memory (see UCF_SLC_REFILL_RD). Filters: src_loc_cpu, src_loc_noncpu and src_rem select the request initiator: local CPU, local non-CPU device or remote socket. dst_loc_cmem, dst_loc_gmem, dst_loc_other and dst_rem select the memory type of the request address: local CMEM, local GMEM, local CXL memory or remote memory; local or remote is determined by the home socket of the address. An unset group counts all.",
+ "Unit": "nvidia_ucf_pmu_"
+ },
+ {
+ "EventCode": "0x109",
+ "EventName": "UCF_SLC_REFILL_RD",
+ "BriefDescription": "Counts inbound read requests not supplied by the local socket's L1, L2 or L3 caches.",
+ "PublicDescription": "Counts inbound read requests not supplied by the local socket's L1, L2 or L3 caches. For remote-memory addresses, it also counts each Shared-to-Unique permission upgrade (dataless MakeReadUnique) of a cache line shared by requesters in different sockets. A refill is not the same as a miss: the SLC may fetch data from memory even when a requester cache holds clean data, and such accesses are hits that are still refilled. Filters: src_loc_cpu, src_loc_noncpu and src_rem select the request initiator: local CPU, local non-CPU device or remote socket. dst_loc_cmem, dst_loc_gmem, dst_loc_other and dst_rem select the memory type of the request address: local CMEM, local GMEM, local CXL memory or remote memory; local or remote is determined by the home socket of the address. An unset group counts all.",
+ "Unit": "nvidia_ucf_pmu_"
+ },
+ {
+ "EventCode": "0x10a",
+ "EventName": "UCF_SLC_REFILL_WR",
+ "BriefDescription": "Counts inbound write requests not supplied by the local socket's L1, L2 or L3 caches.",
+ "PublicDescription": "Counts inbound write requests not supplied by the local socket's L1, L2 or L3 caches. A write refill occurs only for a partial write that needs the existing data; dataless write requests do not cause a refill and are not counted. Filters: src_loc_cpu, src_loc_noncpu and src_rem select the request initiator: local CPU, local non-CPU device or remote socket. dst_loc_cmem, dst_loc_gmem, dst_loc_other and dst_rem select the memory type of the request address: local CMEM, local GMEM, local CXL memory or remote memory; local or remote is determined by the home socket of the address. An unset group counts all.",
+ "Unit": "nvidia_ucf_pmu_"
+ },
+ {
+ "EventCode": "0xf0",
+ "EventName": "UCF_SLC_ALLOCATE",
+ "BriefDescription": "Counts read, write, atomic or prefetch accesses that allocate a line in the SLC's L3 cache.",
+ "PublicDescription": "Counts read, write, atomic or prefetch accesses that allocate a line in the SLC's L3 cache. Filters: src_loc_cpu, src_loc_noncpu and src_rem select the request initiator: local CPU, local non-CPU device or remote socket. dst_loc_cmem, dst_loc_gmem, dst_loc_other and dst_rem select the memory type of the request address: local CMEM, local GMEM, local CXL memory or remote memory; local or remote is determined by the home socket of the address. An unset group counts all.",
+ "Unit": "nvidia_ucf_pmu_"
+ },
+ {
+ "EventCode": "0xf3",
+ "EventName": "UCF_SLC_WB",
+ "BriefDescription": "Counts SLC eviction and coherence write-backs, and non-allocating write-backs from upstream clients.",
+ "PublicDescription": "Counts SLC write-backs: eviction write-backs, coherence write-backs, and non-allocating write-backs from upstream clients. Evictions include L3 cache and snoop filter evictions. A coherence write-back occurs when data is dirty in the L3 cache or another requester node cache, but a requesting agent needs clean data. A home SLC in another socket, or the GL2 of a connected local or remote GPU (the point of coherence for GPU memory), can evict a line and snoop this SLC. A data-bearing snoop response from this SLC is not counted by this event, though it uses this SLC's downstream bandwidth. For a home SLC eviction, the home SLC's events count the downstream write traffic it causes. Filters: src_loc_cpu, src_loc_noncpu and src_rem select the initiator of the request that caused the write-back: local CPU, local non-CPU device or remote socket. This need not be the agent that produced or modified the data. dst_loc_cmem, dst_loc_gmem, dst_loc_other and dst_rem select the memory type of the memory written back: local CMEM, local GMEM, local CXL memory or remote memory; local or remote is determined by the home socket of the address. An unset group counts all.",
+ "Unit": "nvidia_ucf_pmu_"
+ },
+ {
+ "EventCode": "0x180",
+ "EventName": "UCF_LOCAL_SNOOP",
+ "BriefDescription": "Counts snoop requests sent by this SLC to local fully coherent requester nodes or to an SLC in another socket.",
+ "PublicDescription": "Counts snoop requests sent by this SLC to fully coherent requester nodes in the local socket or to an SLC in another socket, including an SLC that this SLC tracks as a sharing node. Invalidating, forwarding, and non-forwarding snoops are included. Each snoop request is counted separately, even when one transaction snoops several clients for the same cache line. Snoops generated for atomic requests or dataless requests are not counted. Filters: src_loc_cpu, src_loc_noncpu and src_rem select the initiator of the request that caused the snoop: local CPU, local non-CPU device or remote socket. dst_loc_cmem, dst_loc_gmem, dst_loc_other and dst_rem select the memory type of the request address: local CMEM, local GMEM, local CXL memory or remote memory; local or remote is determined by the home socket of the address. An unset group counts all.",
+ "Unit": "nvidia_ucf_pmu_"
+ },
+ {
+ "EventCode": "0x181",
+ "EventName": "UCF_EXT_SNP_ACCESS",
+ "BriefDescription": "Counts snoop requests that a home SLC or GL2 in another socket sends to this SLC.",
+ "PublicDescription": "Counts snoop requests that a home SLC or GL2 in another socket sends to this SLC. Snoops are counted whether or not the response carries data. Filters: every counted snoop matches src_rem and dst_rem, since it comes from a remote initiator for an address homed in another socket. An unset source or destination group counts all.",
+ "Unit": "nvidia_ucf_pmu_"
+ },
+ {
+ "EventCode": "0x182",
+ "EventName": "UCF_EXT_SNP_EVICT",
+ "BriefDescription": "Counts snoop requests from a home SLC or GL2 in another socket that invalidate an L3 cache or snoop filter entry in this SLC.",
+ "PublicDescription": "Counts snoop requests from a home SLC or GL2 in another socket that invalidate an L3 cache entry or snoop filter entry in this SLC. Snoops are counted whether or not the response carries data, so this event cannot give the number or volume of data-bearing snoop responses (see UCF_SLC_WB). Filters: every counted snoop matches src_rem and dst_rem, since it comes from a remote initiator for an address homed in another socket. An unset source or destination group counts all.",
+ "Unit": "nvidia_ucf_pmu_"
+ },
+ {
+ "EventCode": "0x121",
+ "EventName": "UCF_MEM_ACCESS_RD",
+ "BriefDescription": "Counts read requests from the SLC toward local CMEM, local GMEM, local CXL memory or remote memory.",
+ "PublicDescription": "Counts read requests from the SLC toward local CMEM, local GMEM, local CXL memory or remote memory. For remote memory it can overcount: it also increments for each Shared-to-Unique permission upgrade (dataless MakeReadUnique) of a cache line shared by requesters in different sockets. To count reads from remote sources without this overcount, count UCF_SLC_ACCESS_RD on the memory's home socket with src_rem, dst_loc_cmem, dst_loc_gmem and dst_loc_other set. Filters: src_loc_cpu, src_loc_noncpu and src_rem select the request initiator: local CPU, local non-CPU device or remote socket. dst_loc_cmem, dst_loc_gmem, dst_loc_other and dst_rem select the memory type of the request address: local CMEM, local GMEM, local CXL memory or remote memory; local or remote is determined by the home socket of the address. An unset group counts all.",
+ "Unit": "nvidia_ucf_pmu_"
+ },
+ {
+ "EventCode": "0x122",
+ "EventName": "UCF_MEM_ACCESS_WR",
+ "BriefDescription": "Counts write requests from the SLC toward local CMEM, local GMEM, local CXL memory or remote memory.",
+ "PublicDescription": "Counts write requests from the SLC toward local CMEM, local GMEM, local CXL memory or remote memory. It includes SLC write-backs, which are attributed as described for UCF_SLC_WB. Data-bearing snoop responses to evictions by a home SLC in another socket or a connected GPU's GL2 are not counted (see UCF_SLC_WB). Filters: src_loc_cpu, src_loc_noncpu and src_rem select the request initiator: local CPU, local non-CPU device or remote socket. dst_loc_cmem, dst_loc_gmem, dst_loc_other and dst_rem select the memory type of the request address: local CMEM, local GMEM, local CXL memory or remote memory; local or remote is determined by the home socket of the address. An unset group counts all.",
+ "Unit": "nvidia_ucf_pmu_"
+ },
+ {
+ "EventCode": "0x123",
+ "EventName": "UCF_MEM_BYTES_RD",
+ "BriefDescription": "Counts bytes transferred by the read requests counted by UCF_MEM_ACCESS_RD.",
+ "PublicDescription": "Counts bytes transferred by the read requests counted by UCF_MEM_ACCESS_RD. Source and destination filters work as described for UCF_MEM_ACCESS_RD.",
+ "Unit": "nvidia_ucf_pmu_"
+ },
+ {
+ "EventCode": "0x124",
+ "EventName": "UCF_MEM_BYTES_WR",
+ "BriefDescription": "Counts bytes transferred by the write requests counted by UCF_MEM_ACCESS_WR.",
+ "PublicDescription": "Counts bytes transferred by the write requests counted by UCF_MEM_ACCESS_WR, including write-back data attributed as described for UCF_SLC_WB. Data-bearing snoop responses to evictions by a home SLC in another socket or a connected GPU's GL2 are not counted (see UCF_SLC_WB). Source and destination filters work as described for UCF_MEM_ACCESS_WR.",
+ "Unit": "nvidia_ucf_pmu_"
+ },
+ {
+ "MetricName": "ucf_freq",
+ "MetricGroup": "UCF_Frequency",
+ "MetricConstraint": "NO_GROUP_EVENTS",
+ "MetricExpr": "(UCF_CYCLES / aggr_nr(UCF_CYCLES)) / 1e9 / duration_time",
+ "ScaleUnit": "1GHz",
+ "BriefDescription": "UCF clock frequency.",
+ "PublicDescription": "Average UCF clock frequency over the measurement interval.",
+ "Unit": "nvidia_ucf_pmu_"
+ },
+ {
+ "MetricName": "ucf_avg_slc_rd_bandwidth_all_src_to_all_dst",
+ "MetricGroup": "UCF_BW_Upstream_RD;UCF_BW_All_Src_To_All_Dst",
+ "MetricExpr": "UCF_SLC_BYTES_RD@src_loc_cpu=1,src_loc_noncpu=1,src_rem=1,dst_loc_cmem=1,dst_loc_gmem=1,dst_loc_other=1,dst_rem=1@ / 1e6 / duration_time",
+ "ScaleUnit": "1MB/s",
+ "BriefDescription": "Average requester-to-SLC read bandwidth for requests from all sources to all destinations.",
+ "PublicDescription": "Average requester-to-SLC read bandwidth of requests from local CPUs, local non-CPU devices and remote sockets for local CMEM, local GMEM, local CXL memory and remote memory addresses.",
+ "Unit": "nvidia_ucf_pmu_"
+ },
+ {
+ "MetricName": "ucf_avg_mem_rd_bandwidth_all_src_to_all_dst",
+ "MetricGroup": "UCF_BW_Downstream_RD;UCF_BW_All_Src_To_All_Dst",
+ "MetricExpr": "UCF_MEM_BYTES_RD@src_loc_cpu=1,src_loc_noncpu=1,src_rem=1,dst_loc_cmem=1,dst_loc_gmem=1,dst_loc_other=1,dst_rem=1@ / 1e6 / duration_time",
+ "ScaleUnit": "1MB/s",
+ "BriefDescription": "Average SLC-to-memory read bandwidth for all memory destinations, for requests from all initiators.",
+ "PublicDescription": "Average SLC-to-memory read bandwidth for local CMEM, local GMEM, local CXL memory and remote memory, for requests initiated by local CPUs, local non-CPU devices and remote sockets.",
+ "Unit": "nvidia_ucf_pmu_"
+ },
+ {
+ "MetricName": "ucf_avg_slc_wr_bandwidth_all_src_to_all_dst",
+ "MetricGroup": "UCF_BW_Upstream_WR;UCF_BW_All_Src_To_All_Dst",
+ "MetricExpr": "UCF_SLC_BYTES_WR@src_loc_cpu=1,src_loc_noncpu=1,src_rem=1,dst_loc_cmem=1,dst_loc_gmem=1,dst_loc_other=1,dst_rem=1@ / 1e6 / duration_time",
+ "ScaleUnit": "1MB/s",
+ "BriefDescription": "Average requester-to-SLC write bandwidth for requests from all sources to all destinations.",
+ "PublicDescription": "Average requester-to-SLC write bandwidth of requests from local CPUs, local non-CPU devices and remote sockets for local CMEM, local GMEM, local CXL memory and remote memory addresses.",
+ "Unit": "nvidia_ucf_pmu_"
+ },
+ {
+ "MetricName": "ucf_avg_mem_wr_bandwidth_all_src_to_all_dst",
+ "MetricGroup": "UCF_BW_Downstream_WR;UCF_BW_All_Src_To_All_Dst",
+ "MetricExpr": "UCF_MEM_BYTES_WR@src_loc_cpu=1,src_loc_noncpu=1,src_rem=1,dst_loc_cmem=1,dst_loc_gmem=1,dst_loc_other=1,dst_rem=1@ / 1e6 / duration_time",
+ "ScaleUnit": "1MB/s",
+ "BriefDescription": "Average SLC-to-memory write bandwidth for local and remote memory, for traffic from all initiators.",
+ "PublicDescription": "Average SLC-to-memory write bandwidth for local CMEM, local GMEM, local CXL memory and remote memory, for traffic initiated by local CPUs, local non-CPU devices and remote sockets. Includes write-backs, attributed as described for UCF_SLC_WB. Data-bearing snoop responses to evictions by a home SLC in another socket or a connected GPU's GL2 are not counted (see UCF_SLC_WB).",
+ "Unit": "nvidia_ucf_pmu_"
+ },
+ {
+ "MetricName": "ucf_avg_slc_bandwidth_all_src_to_all_dst",
+ "MetricGroup": "UCF_BW_All_Src_To_All_Dst",
+ "MetricExpr": "ucf_avg_slc_rd_bandwidth_all_src_to_all_dst + ucf_avg_slc_wr_bandwidth_all_src_to_all_dst",
+ "ScaleUnit": "1MB/s",
+ "BriefDescription": "Average requester-to-SLC read and write bandwidth for requests from all sources to all destinations.",
+ "PublicDescription": "Average requester-to-SLC read and write bandwidth of requests from local CPUs, local non-CPU devices and remote sockets for local CMEM, local GMEM, local CXL memory and remote memory addresses.",
+ "Unit": "nvidia_ucf_pmu_"
+ },
+ {
+ "MetricName": "ucf_avg_mem_bandwidth_all_src_to_all_dst",
+ "MetricGroup": "UCF_BW_All_Src_To_All_Dst",
+ "MetricExpr": "ucf_avg_mem_rd_bandwidth_all_src_to_all_dst + ucf_avg_mem_wr_bandwidth_all_src_to_all_dst",
+ "ScaleUnit": "1MB/s",
+ "BriefDescription": "Average SLC-to-memory read and write bandwidth for local and remote memory, for traffic from all initiators.",
+ "PublicDescription": "Average SLC-to-memory read and write bandwidth for local CMEM, local GMEM, local CXL memory and remote memory, for traffic initiated by local CPUs, local non-CPU devices and remote sockets. Writes include write-backs, attributed as described for UCF_SLC_WB. Data-bearing snoop responses to evictions by a home SLC in another socket or a connected GPU's GL2 are not counted (see UCF_SLC_WB).",
+ "Unit": "nvidia_ucf_pmu_"
+ },
+ {
+ "MetricName": "ucf_avg_slc_rd_bandwidth_all_src_to_local_cmem",
+ "MetricGroup": "UCF_BW_Upstream_RD;UCF_BW_Local_CMEM;UCF_BW_All_Src_To_Local_CMEM",
+ "MetricExpr": "UCF_SLC_BYTES_RD@src_loc_cpu=1,src_loc_noncpu=1,src_rem=1,dst_loc_cmem=1@ / 1e6 / duration_time",
+ "ScaleUnit": "1MB/s",
+ "BriefDescription": "Average requester-to-SLC read bandwidth for requests from all sources to local CMEM addresses.",
+ "PublicDescription": "Average requester-to-SLC read bandwidth of requests from local CPUs, local non-CPU devices and remote sockets for local CMEM addresses.",
+ "Unit": "nvidia_ucf_pmu_"
+ },
+ {
+ "MetricName": "ucf_avg_mem_rd_bandwidth_all_src_to_local_cmem",
+ "MetricGroup": "UCF_BW_Downstream_RD;UCF_BW_Local_CMEM;UCF_BW_All_Src_To_Local_CMEM",
+ "MetricExpr": "UCF_MEM_BYTES_RD@src_loc_cpu=1,src_loc_noncpu=1,src_rem=1,dst_loc_cmem=1@ / 1e6 / duration_time",
+ "ScaleUnit": "1MB/s",
+ "BriefDescription": "Average SLC-to-memory read bandwidth for local CMEM, for requests from all initiators.",
+ "PublicDescription": "Average SLC-to-memory read bandwidth for local CMEM, for requests initiated by local CPUs, local non-CPU devices and remote sockets.",
+ "Unit": "nvidia_ucf_pmu_"
+ },
+ {
+ "MetricName": "ucf_avg_slc_wr_bandwidth_all_src_to_local_cmem",
+ "MetricGroup": "UCF_BW_Upstream_WR;UCF_BW_Local_CMEM;UCF_BW_All_Src_To_Local_CMEM",
+ "MetricExpr": "UCF_SLC_BYTES_WR@src_loc_cpu=1,src_loc_noncpu=1,src_rem=1,dst_loc_cmem=1@ / 1e6 / duration_time",
+ "ScaleUnit": "1MB/s",
+ "BriefDescription": "Average requester-to-SLC write bandwidth for requests from all sources to local CMEM addresses.",
+ "PublicDescription": "Average requester-to-SLC write bandwidth of requests from local CPUs, local non-CPU devices and remote sockets for local CMEM addresses.",
+ "Unit": "nvidia_ucf_pmu_"
+ },
+ {
+ "MetricName": "ucf_avg_mem_wr_bandwidth_all_src_to_local_cmem",
+ "MetricGroup": "UCF_BW_Downstream_WR;UCF_BW_Local_CMEM;UCF_BW_All_Src_To_Local_CMEM",
+ "MetricExpr": "UCF_MEM_BYTES_WR@src_loc_cpu=1,src_loc_noncpu=1,src_rem=1,dst_loc_cmem=1@ / 1e6 / duration_time",
+ "ScaleUnit": "1MB/s",
+ "BriefDescription": "Average SLC-to-memory write bandwidth for local CMEM, for traffic from all initiators.",
+ "PublicDescription": "Average SLC-to-memory write bandwidth for local CMEM, for traffic initiated by local CPUs, local non-CPU devices and remote sockets. Includes write-backs, attributed as described for UCF_SLC_WB.",
+ "Unit": "nvidia_ucf_pmu_"
+ },
+ {
+ "MetricName": "ucf_avg_slc_bandwidth_all_src_to_local_cmem",
+ "MetricGroup": "UCF_BW_All_Src_To_Local_CMEM",
+ "MetricExpr": "ucf_avg_slc_rd_bandwidth_all_src_to_local_cmem + ucf_avg_slc_wr_bandwidth_all_src_to_local_cmem",
+ "ScaleUnit": "1MB/s",
+ "BriefDescription": "Average requester-to-SLC read and write bandwidth for requests from all sources to local CMEM addresses.",
+ "PublicDescription": "Average requester-to-SLC read and write bandwidth of requests from local CPUs, local non-CPU devices and remote sockets for local CMEM addresses.",
+ "Unit": "nvidia_ucf_pmu_"
+ },
+ {
+ "MetricName": "ucf_avg_mem_bandwidth_all_src_to_local_cmem",
+ "MetricGroup": "UCF_BW_All_Src_To_Local_CMEM",
+ "MetricExpr": "ucf_avg_mem_rd_bandwidth_all_src_to_local_cmem + ucf_avg_mem_wr_bandwidth_all_src_to_local_cmem",
+ "ScaleUnit": "1MB/s",
+ "BriefDescription": "Average SLC-to-memory read and write bandwidth for local CMEM, for traffic from all initiators.",
+ "PublicDescription": "Average SLC-to-memory read and write bandwidth for local CMEM, for traffic initiated by local CPUs, local non-CPU devices and remote sockets. Writes include write-backs, attributed as described for UCF_SLC_WB.",
+ "Unit": "nvidia_ucf_pmu_"
+ },
+ {
+ "MetricName": "ucf_avg_slc_rd_bandwidth_local_src_to_local_cmem",
+ "MetricGroup": "UCF_BW_Upstream_RD;UCF_BW_Local_CMEM;UCF_BW_Local_Src_To_Local_CMEM",
+ "MetricExpr": "ucf_avg_slc_rd_bandwidth_local_cpu_to_local_cmem + ucf_avg_slc_rd_bandwidth_local_noncpu_to_local_cmem",
+ "ScaleUnit": "1MB/s",
+ "BriefDescription": "Average requester-to-SLC read bandwidth for local CPU and local non-CPU requests to local CMEM addresses.",
+ "PublicDescription": "Average requester-to-SLC read bandwidth of requests from local CPUs and local non-CPU devices such as the GPU and PCIe devices for local CMEM addresses.",
+ "Unit": "nvidia_ucf_pmu_"
+ },
+ {
+ "MetricName": "ucf_avg_mem_rd_bandwidth_local_src_to_local_cmem",
+ "MetricGroup": "UCF_BW_Downstream_RD;UCF_BW_Local_CMEM;UCF_BW_Local_Src_To_Local_CMEM",
+ "MetricExpr": "ucf_avg_mem_rd_bandwidth_local_cpu_to_local_cmem + ucf_avg_mem_rd_bandwidth_local_noncpu_to_local_cmem",
+ "ScaleUnit": "1MB/s",
+ "BriefDescription": "Average SLC-to-memory read bandwidth for local CMEM, for requests initiated by local CPUs and local non-CPU devices.",
+ "PublicDescription": "Average SLC-to-memory read bandwidth for local CMEM, for requests initiated by local CPUs and local non-CPU devices such as the GPU and PCIe devices.",
+ "Unit": "nvidia_ucf_pmu_"
+ },
+ {
+ "MetricName": "ucf_avg_slc_wr_bandwidth_local_src_to_local_cmem",
+ "MetricGroup": "UCF_BW_Upstream_WR;UCF_BW_Local_CMEM;UCF_BW_Local_Src_To_Local_CMEM",
+ "MetricExpr": "ucf_avg_slc_wr_bandwidth_local_cpu_to_local_cmem + ucf_avg_slc_wr_bandwidth_local_noncpu_to_local_cmem",
+ "ScaleUnit": "1MB/s",
+ "BriefDescription": "Average requester-to-SLC write bandwidth for local CPU and local non-CPU requests to local CMEM addresses.",
+ "PublicDescription": "Average requester-to-SLC write bandwidth of requests from local CPUs and local non-CPU devices such as the GPU and PCIe devices for local CMEM addresses.",
+ "Unit": "nvidia_ucf_pmu_"
+ },
+ {
+ "MetricName": "ucf_avg_mem_wr_bandwidth_local_src_to_local_cmem",
+ "MetricGroup": "UCF_BW_Downstream_WR;UCF_BW_Local_CMEM;UCF_BW_Local_Src_To_Local_CMEM",
+ "MetricExpr": "ucf_avg_mem_wr_bandwidth_local_cpu_to_local_cmem + ucf_avg_mem_wr_bandwidth_local_noncpu_to_local_cmem",
+ "ScaleUnit": "1MB/s",
+ "BriefDescription": "Average SLC-to-memory write bandwidth for local CMEM, for traffic initiated by local CPUs and local non-CPU devices.",
+ "PublicDescription": "Average SLC-to-memory write bandwidth for local CMEM, for traffic initiated by local CPUs and local non-CPU devices such as the GPU and PCIe devices. Includes write-backs, attributed as described for UCF_SLC_WB.",
+ "Unit": "nvidia_ucf_pmu_"
+ },
+ {
+ "MetricName": "ucf_avg_slc_rd_bandwidth_local_src_to_remote_mem",
+ "MetricGroup": "UCF_BW_Upstream_RD;UCF_BW_Remote_Memory;UCF_BW_Local_Src_To_Remote_Memory",
+ "MetricExpr": "ucf_avg_slc_rd_bandwidth_local_cpu_to_remote_mem + ucf_avg_slc_rd_bandwidth_local_noncpu_to_remote_mem",
+ "ScaleUnit": "1MB/s",
+ "BriefDescription": "Average requester-to-SLC read bandwidth for local CPU and local non-CPU requests to remote memory addresses.",
+ "PublicDescription": "Average requester-to-SLC read bandwidth of requests from local CPUs and local non-CPU devices such as the GPU and PCIe devices for remote memory addresses.",
+ "Unit": "nvidia_ucf_pmu_"
+ },
+ {
+ "MetricName": "ucf_avg_mem_rd_bandwidth_local_src_to_remote_mem",
+ "MetricGroup": "UCF_BW_Downstream_RD;UCF_BW_Remote_Memory;UCF_BW_Local_Src_To_Remote_Memory",
+ "MetricExpr": "ucf_avg_mem_rd_bandwidth_local_cpu_to_remote_mem + ucf_avg_mem_rd_bandwidth_local_noncpu_to_remote_mem",
+ "ScaleUnit": "1MB/s",
+ "BriefDescription": "Average SLC-to-memory read bandwidth for remote memory, for requests initiated by local CPUs and local non-CPU devices.",
+ "PublicDescription": "Average SLC-to-memory read bandwidth for remote memory, for requests initiated by local CPUs and local non-CPU devices such as the GPU and PCIe devices.",
+ "Unit": "nvidia_ucf_pmu_"
+ },
+ {
+ "MetricName": "ucf_avg_slc_wr_bandwidth_local_src_to_remote_mem",
+ "MetricGroup": "UCF_BW_Upstream_WR;UCF_BW_Remote_Memory;UCF_BW_Local_Src_To_Remote_Memory",
+ "MetricExpr": "ucf_avg_slc_wr_bandwidth_local_cpu_to_remote_mem + ucf_avg_slc_wr_bandwidth_local_noncpu_to_remote_mem",
+ "ScaleUnit": "1MB/s",
+ "BriefDescription": "Average requester-to-SLC write bandwidth for local CPU and local non-CPU requests to remote memory addresses.",
+ "PublicDescription": "Average requester-to-SLC write bandwidth of requests from local CPUs and local non-CPU devices such as the GPU and PCIe devices for remote memory addresses.",
+ "Unit": "nvidia_ucf_pmu_"
+ },
+ {
+ "MetricName": "ucf_avg_mem_wr_bandwidth_local_src_to_remote_mem",
+ "MetricGroup": "UCF_BW_Downstream_WR;UCF_BW_Remote_Memory;UCF_BW_Local_Src_To_Remote_Memory",
+ "MetricExpr": "ucf_avg_mem_wr_bandwidth_local_cpu_to_remote_mem + ucf_avg_mem_wr_bandwidth_local_noncpu_to_remote_mem",
+ "ScaleUnit": "1MB/s",
+ "BriefDescription": "Average SLC-to-memory write bandwidth for remote memory, for traffic initiated by local CPUs and local non-CPU devices.",
+ "PublicDescription": "Average SLC-to-memory write bandwidth for remote memory, for traffic initiated by local CPUs and local non-CPU devices such as the GPU and PCIe devices. Includes write-backs, attributed as described for UCF_SLC_WB. Data-bearing snoop responses to evictions by a home SLC in another socket or a connected GPU's GL2 are not counted (see UCF_SLC_WB).",
+ "Unit": "nvidia_ucf_pmu_"
+ },
+ {
+ "MetricName": "ucf_avg_slc_rd_bandwidth_local_cpu_to_local_cmem",
+ "MetricGroup": "UCF_BW_Upstream_RD;UCF_BW_Local_CPU;UCF_BW_Local_CMEM;UCF_BW_Local_CPU_To_Local_CMEM",
+ "MetricExpr": "UCF_SLC_BYTES_RD@src_loc_cpu=1,dst_loc_cmem=1@ / 1e6 / duration_time",
+ "ScaleUnit": "1MB/s",
+ "BriefDescription": "Average requester-to-SLC read bandwidth for local CPU requests to local CMEM addresses.",
+ "PublicDescription": "Average requester-to-SLC read bandwidth of requests from local CPUs for local CMEM addresses.",
+ "Unit": "nvidia_ucf_pmu_"
+ },
+ {
+ "MetricName": "ucf_avg_mem_rd_bandwidth_local_cpu_to_local_cmem",
+ "MetricGroup": "UCF_BW_Downstream_RD;UCF_BW_Local_CPU;UCF_BW_Local_CMEM;UCF_BW_Local_CPU_To_Local_CMEM",
+ "MetricExpr": "UCF_MEM_BYTES_RD@src_loc_cpu=1,dst_loc_cmem=1@ / 1e6 / duration_time",
+ "ScaleUnit": "1MB/s",
+ "BriefDescription": "Average SLC-to-memory read bandwidth for local CMEM, for requests initiated by local CPUs.",
+ "PublicDescription": "Average SLC-to-memory read bandwidth for local CMEM, for requests initiated by local CPUs.",
+ "Unit": "nvidia_ucf_pmu_"
+ },
+ {
+ "MetricName": "ucf_avg_slc_wr_bandwidth_local_cpu_to_local_cmem",
+ "MetricGroup": "UCF_BW_Upstream_WR;UCF_BW_Local_CPU;UCF_BW_Local_CMEM;UCF_BW_Local_CPU_To_Local_CMEM",
+ "MetricExpr": "UCF_SLC_BYTES_WR@src_loc_cpu=1,dst_loc_cmem=1@ / 1e6 / duration_time",
+ "ScaleUnit": "1MB/s",
+ "BriefDescription": "Average requester-to-SLC write bandwidth for local CPU requests to local CMEM addresses.",
+ "PublicDescription": "Average requester-to-SLC write bandwidth of requests from local CPUs for local CMEM addresses.",
+ "Unit": "nvidia_ucf_pmu_"
+ },
+ {
+ "MetricName": "ucf_avg_mem_wr_bandwidth_local_cpu_to_local_cmem",
+ "MetricGroup": "UCF_BW_Downstream_WR;UCF_BW_Local_CPU;UCF_BW_Local_CMEM;UCF_BW_Local_CPU_To_Local_CMEM",
+ "MetricExpr": "UCF_MEM_BYTES_WR@src_loc_cpu=1,dst_loc_cmem=1@ / 1e6 / duration_time",
+ "ScaleUnit": "1MB/s",
+ "BriefDescription": "Average SLC-to-memory write bandwidth for local CMEM, for traffic initiated by local CPUs.",
+ "PublicDescription": "Average SLC-to-memory write bandwidth for local CMEM, for traffic initiated by local CPUs. Includes write-backs, attributed as described for UCF_SLC_WB.",
+ "Unit": "nvidia_ucf_pmu_"
+ },
+ {
+ "MetricName": "ucf_avg_slc_rd_bandwidth_local_cpu_to_local_gmem",
+ "MetricGroup": "UCF_BW_Upstream_RD;UCF_BW_Local_CPU;UCF_BW_Local_GMEM;UCF_BW_Local_CPU_To_Local_GMEM",
+ "MetricExpr": "UCF_SLC_BYTES_RD@src_loc_cpu=1,dst_loc_gmem=1@ / 1e6 / duration_time",
+ "ScaleUnit": "1MB/s",
+ "BriefDescription": "Average requester-to-SLC read bandwidth for local CPU requests to local GMEM addresses.",
+ "PublicDescription": "Average requester-to-SLC read bandwidth of requests from local CPUs for local GMEM addresses.",
+ "Unit": "nvidia_ucf_pmu_"
+ },
+ {
+ "MetricName": "ucf_avg_mem_rd_bandwidth_local_cpu_to_local_gmem",
+ "MetricGroup": "UCF_BW_Downstream_RD;UCF_BW_Local_CPU;UCF_BW_Local_GMEM;UCF_BW_Local_CPU_To_Local_GMEM",
+ "MetricExpr": "UCF_MEM_BYTES_RD@src_loc_cpu=1,dst_loc_gmem=1@ / 1e6 / duration_time",
+ "ScaleUnit": "1MB/s",
+ "BriefDescription": "Average SLC-to-memory read bandwidth for local GMEM, for requests initiated by local CPUs.",
+ "PublicDescription": "Average SLC-to-memory read bandwidth for local GMEM, for requests initiated by local CPUs.",
+ "Unit": "nvidia_ucf_pmu_"
+ },
+ {
+ "MetricName": "ucf_avg_slc_wr_bandwidth_local_cpu_to_local_gmem",
+ "MetricGroup": "UCF_BW_Upstream_WR;UCF_BW_Local_CPU;UCF_BW_Local_GMEM;UCF_BW_Local_CPU_To_Local_GMEM",
+ "MetricExpr": "UCF_SLC_BYTES_WR@src_loc_cpu=1,dst_loc_gmem=1@ / 1e6 / duration_time",
+ "ScaleUnit": "1MB/s",
+ "BriefDescription": "Average requester-to-SLC write bandwidth for local CPU requests to local GMEM addresses.",
+ "PublicDescription": "Average requester-to-SLC write bandwidth of requests from local CPUs for local GMEM addresses.",
+ "Unit": "nvidia_ucf_pmu_"
+ },
+ {
+ "MetricName": "ucf_avg_mem_wr_bandwidth_local_cpu_to_local_gmem",
+ "MetricGroup": "UCF_BW_Downstream_WR;UCF_BW_Local_CPU;UCF_BW_Local_GMEM;UCF_BW_Local_CPU_To_Local_GMEM",
+ "MetricExpr": "UCF_MEM_BYTES_WR@src_loc_cpu=1,dst_loc_gmem=1@ / 1e6 / duration_time",
+ "ScaleUnit": "1MB/s",
+ "BriefDescription": "Average SLC-to-memory write bandwidth for local GMEM, for traffic initiated by local CPUs.",
+ "PublicDescription": "Average SLC-to-memory write bandwidth for local GMEM, for traffic initiated by local CPUs. Includes write-backs, attributed as described for UCF_SLC_WB. Data-bearing snoop responses to evictions by a home SLC in another socket or a connected GPU's GL2 are not counted (see UCF_SLC_WB).",
+ "Unit": "nvidia_ucf_pmu_"
+ },
+ {
+ "MetricName": "ucf_avg_slc_rd_bandwidth_local_cpu_to_local_cxlmem",
+ "MetricGroup": "UCF_BW_Upstream_RD;UCF_BW_Local_CPU;UCF_BW_Local_CXLMEM;UCF_BW_Local_CPU_To_Local_CXLMEM",
+ "MetricExpr": "UCF_SLC_BYTES_RD@src_loc_cpu=1,dst_loc_other=1@ / 1e6 / duration_time",
+ "ScaleUnit": "1MB/s",
+ "BriefDescription": "Average requester-to-SLC read bandwidth for local CPU requests to local CXL memory addresses.",
+ "PublicDescription": "Average requester-to-SLC read bandwidth of requests from local CPUs for local CXL memory addresses.",
+ "Unit": "nvidia_ucf_pmu_"
+ },
+ {
+ "MetricName": "ucf_avg_mem_rd_bandwidth_local_cpu_to_local_cxlmem",
+ "MetricGroup": "UCF_BW_Downstream_RD;UCF_BW_Local_CPU;UCF_BW_Local_CXLMEM;UCF_BW_Local_CPU_To_Local_CXLMEM",
+ "MetricExpr": "UCF_MEM_BYTES_RD@src_loc_cpu=1,dst_loc_other=1@ / 1e6 / duration_time",
+ "ScaleUnit": "1MB/s",
+ "BriefDescription": "Average SLC-to-memory read bandwidth for local CXL memory, for requests initiated by local CPUs.",
+ "PublicDescription": "Average SLC-to-memory read bandwidth for local CXL memory, for requests initiated by local CPUs.",
+ "Unit": "nvidia_ucf_pmu_"
+ },
+ {
+ "MetricName": "ucf_avg_slc_wr_bandwidth_local_cpu_to_local_cxlmem",
+ "MetricGroup": "UCF_BW_Upstream_WR;UCF_BW_Local_CPU;UCF_BW_Local_CXLMEM;UCF_BW_Local_CPU_To_Local_CXLMEM",
+ "MetricExpr": "UCF_SLC_BYTES_WR@src_loc_cpu=1,dst_loc_other=1@ / 1e6 / duration_time",
+ "ScaleUnit": "1MB/s",
+ "BriefDescription": "Average requester-to-SLC write bandwidth for local CPU requests to local CXL memory addresses.",
+ "PublicDescription": "Average requester-to-SLC write bandwidth of requests from local CPUs for local CXL memory addresses.",
+ "Unit": "nvidia_ucf_pmu_"
+ },
+ {
+ "MetricName": "ucf_avg_mem_wr_bandwidth_local_cpu_to_local_cxlmem",
+ "MetricGroup": "UCF_BW_Downstream_WR;UCF_BW_Local_CPU;UCF_BW_Local_CXLMEM;UCF_BW_Local_CPU_To_Local_CXLMEM",
+ "MetricExpr": "UCF_MEM_BYTES_WR@src_loc_cpu=1,dst_loc_other=1@ / 1e6 / duration_time",
+ "ScaleUnit": "1MB/s",
+ "BriefDescription": "Average SLC-to-memory write bandwidth for local CXL memory, for traffic initiated by local CPUs.",
+ "PublicDescription": "Average SLC-to-memory write bandwidth for local CXL memory, for traffic initiated by local CPUs. Includes write-backs, attributed as described for UCF_SLC_WB.",
+ "Unit": "nvidia_ucf_pmu_"
+ },
+ {
+ "MetricName": "ucf_avg_slc_rd_bandwidth_local_cpu_to_remote_mem",
+ "MetricGroup": "UCF_BW_Upstream_RD;UCF_BW_Local_CPU;UCF_BW_Remote_Memory;UCF_BW_Local_CPU_To_Remote_Memory",
+ "MetricExpr": "UCF_SLC_BYTES_RD@src_loc_cpu=1,dst_rem=1@ / 1e6 / duration_time",
+ "ScaleUnit": "1MB/s",
+ "BriefDescription": "Average requester-to-SLC read bandwidth for local CPU requests to remote memory addresses.",
+ "PublicDescription": "Average requester-to-SLC read bandwidth of requests from local CPUs for remote memory addresses.",
+ "Unit": "nvidia_ucf_pmu_"
+ },
+ {
+ "MetricName": "ucf_avg_mem_rd_bandwidth_local_cpu_to_remote_mem",
+ "MetricGroup": "UCF_BW_Downstream_RD;UCF_BW_Local_CPU;UCF_BW_Remote_Memory;UCF_BW_Local_CPU_To_Remote_Memory",
+ "MetricExpr": "UCF_MEM_BYTES_RD@src_loc_cpu=1,dst_rem=1@ / 1e6 / duration_time",
+ "ScaleUnit": "1MB/s",
+ "BriefDescription": "Average SLC-to-memory read bandwidth for remote memory, for requests initiated by local CPUs.",
+ "PublicDescription": "Average SLC-to-memory read bandwidth for remote memory, for requests initiated by local CPUs.",
+ "Unit": "nvidia_ucf_pmu_"
+ },
+ {
+ "MetricName": "ucf_avg_slc_wr_bandwidth_local_cpu_to_remote_mem",
+ "MetricGroup": "UCF_BW_Upstream_WR;UCF_BW_Local_CPU;UCF_BW_Remote_Memory;UCF_BW_Local_CPU_To_Remote_Memory",
+ "MetricExpr": "UCF_SLC_BYTES_WR@src_loc_cpu=1,dst_rem=1@ / 1e6 / duration_time",
+ "ScaleUnit": "1MB/s",
+ "BriefDescription": "Average requester-to-SLC write bandwidth for local CPU requests to remote memory addresses.",
+ "PublicDescription": "Average requester-to-SLC write bandwidth of requests from local CPUs for remote memory addresses.",
+ "Unit": "nvidia_ucf_pmu_"
+ },
+ {
+ "MetricName": "ucf_avg_mem_wr_bandwidth_local_cpu_to_remote_mem",
+ "MetricGroup": "UCF_BW_Downstream_WR;UCF_BW_Local_CPU;UCF_BW_Remote_Memory;UCF_BW_Local_CPU_To_Remote_Memory",
+ "MetricExpr": "UCF_MEM_BYTES_WR@src_loc_cpu=1,dst_rem=1@ / 1e6 / duration_time",
+ "ScaleUnit": "1MB/s",
+ "BriefDescription": "Average SLC-to-memory write bandwidth for remote memory, for traffic initiated by local CPUs.",
+ "PublicDescription": "Average SLC-to-memory write bandwidth for remote memory, for traffic initiated by local CPUs. Includes write-backs, attributed as described for UCF_SLC_WB. Data-bearing snoop responses to evictions by a home SLC in another socket or a connected GPU's GL2 are not counted (see UCF_SLC_WB).",
+ "Unit": "nvidia_ucf_pmu_"
+ },
+ {
+ "MetricName": "ucf_avg_slc_rd_bandwidth_local_noncpu_to_local_cmem",
+ "MetricGroup": "UCF_BW_Upstream_RD;UCF_BW_Local_NonCPU;UCF_BW_Local_CMEM;UCF_BW_Local_NonCPU_To_Local_CMEM",
+ "MetricExpr": "UCF_SLC_BYTES_RD@src_loc_noncpu=1,dst_loc_cmem=1@ / 1e6 / duration_time",
+ "ScaleUnit": "1MB/s",
+ "BriefDescription": "Average requester-to-SLC read bandwidth for local non-CPU requests to local CMEM addresses.",
+ "PublicDescription": "Average requester-to-SLC read bandwidth of requests from local non-CPU devices such as the GPU and PCIe devices for local CMEM addresses.",
+ "Unit": "nvidia_ucf_pmu_"
+ },
+ {
+ "MetricName": "ucf_avg_mem_rd_bandwidth_local_noncpu_to_local_cmem",
+ "MetricGroup": "UCF_BW_Downstream_RD;UCF_BW_Local_NonCPU;UCF_BW_Local_CMEM;UCF_BW_Local_NonCPU_To_Local_CMEM",
+ "MetricExpr": "UCF_MEM_BYTES_RD@src_loc_noncpu=1,dst_loc_cmem=1@ / 1e6 / duration_time",
+ "ScaleUnit": "1MB/s",
+ "BriefDescription": "Average SLC-to-memory read bandwidth for local CMEM, for requests initiated by local non-CPU devices.",
+ "PublicDescription": "Average SLC-to-memory read bandwidth for local CMEM, for requests initiated by local non-CPU devices such as the GPU and PCIe devices.",
+ "Unit": "nvidia_ucf_pmu_"
+ },
+ {
+ "MetricName": "ucf_avg_slc_wr_bandwidth_local_noncpu_to_local_cmem",
+ "MetricGroup": "UCF_BW_Upstream_WR;UCF_BW_Local_NonCPU;UCF_BW_Local_CMEM;UCF_BW_Local_NonCPU_To_Local_CMEM",
+ "MetricExpr": "UCF_SLC_BYTES_WR@src_loc_noncpu=1,dst_loc_cmem=1@ / 1e6 / duration_time",
+ "ScaleUnit": "1MB/s",
+ "BriefDescription": "Average requester-to-SLC write bandwidth for local non-CPU requests to local CMEM addresses.",
+ "PublicDescription": "Average requester-to-SLC write bandwidth of requests from local non-CPU devices such as the GPU and PCIe devices for local CMEM addresses.",
+ "Unit": "nvidia_ucf_pmu_"
+ },
+ {
+ "MetricName": "ucf_avg_mem_wr_bandwidth_local_noncpu_to_local_cmem",
+ "MetricGroup": "UCF_BW_Downstream_WR;UCF_BW_Local_NonCPU;UCF_BW_Local_CMEM;UCF_BW_Local_NonCPU_To_Local_CMEM",
+ "MetricExpr": "UCF_MEM_BYTES_WR@src_loc_noncpu=1,dst_loc_cmem=1@ / 1e6 / duration_time",
+ "ScaleUnit": "1MB/s",
+ "BriefDescription": "Average SLC-to-memory write bandwidth for local CMEM, for traffic initiated by local non-CPU devices.",
+ "PublicDescription": "Average SLC-to-memory write bandwidth for local CMEM, for traffic initiated by local non-CPU devices such as the GPU and PCIe devices. Includes write-backs, attributed as described for UCF_SLC_WB.",
+ "Unit": "nvidia_ucf_pmu_"
+ },
+ {
+ "MetricName": "ucf_avg_slc_rd_bandwidth_local_noncpu_to_local_gmem",
+ "MetricGroup": "UCF_BW_Upstream_RD;UCF_BW_Local_NonCPU;UCF_BW_Local_GMEM;UCF_BW_Local_NonCPU_To_Local_GMEM",
+ "MetricExpr": "UCF_SLC_BYTES_RD@src_loc_noncpu=1,dst_loc_gmem=1@ / 1e6 / duration_time",
+ "ScaleUnit": "1MB/s",
+ "BriefDescription": "Average requester-to-SLC read bandwidth for local non-CPU requests to local GMEM addresses.",
+ "PublicDescription": "Average requester-to-SLC read bandwidth of requests from local non-CPU devices such as the GPU and PCIe devices for local GMEM addresses.",
+ "Unit": "nvidia_ucf_pmu_"
+ },
+ {
+ "MetricName": "ucf_avg_mem_rd_bandwidth_local_noncpu_to_local_gmem",
+ "MetricGroup": "UCF_BW_Downstream_RD;UCF_BW_Local_NonCPU;UCF_BW_Local_GMEM;UCF_BW_Local_NonCPU_To_Local_GMEM",
+ "MetricExpr": "UCF_MEM_BYTES_RD@src_loc_noncpu=1,dst_loc_gmem=1@ / 1e6 / duration_time",
+ "ScaleUnit": "1MB/s",
+ "BriefDescription": "Average SLC-to-memory read bandwidth for local GMEM, for requests initiated by local non-CPU devices.",
+ "PublicDescription": "Average SLC-to-memory read bandwidth for local GMEM, for requests initiated by local non-CPU devices such as the GPU and PCIe devices.",
+ "Unit": "nvidia_ucf_pmu_"
+ },
+ {
+ "MetricName": "ucf_avg_slc_wr_bandwidth_local_noncpu_to_local_gmem",
+ "MetricGroup": "UCF_BW_Upstream_WR;UCF_BW_Local_NonCPU;UCF_BW_Local_GMEM;UCF_BW_Local_NonCPU_To_Local_GMEM",
+ "MetricExpr": "UCF_SLC_BYTES_WR@src_loc_noncpu=1,dst_loc_gmem=1@ / 1e6 / duration_time",
+ "ScaleUnit": "1MB/s",
+ "BriefDescription": "Average requester-to-SLC write bandwidth for local non-CPU requests to local GMEM addresses.",
+ "PublicDescription": "Average requester-to-SLC write bandwidth of requests from local non-CPU devices such as the GPU and PCIe devices for local GMEM addresses.",
+ "Unit": "nvidia_ucf_pmu_"
+ },
+ {
+ "MetricName": "ucf_avg_mem_wr_bandwidth_local_noncpu_to_local_gmem",
+ "MetricGroup": "UCF_BW_Downstream_WR;UCF_BW_Local_NonCPU;UCF_BW_Local_GMEM;UCF_BW_Local_NonCPU_To_Local_GMEM",
+ "MetricExpr": "UCF_MEM_BYTES_WR@src_loc_noncpu=1,dst_loc_gmem=1@ / 1e6 / duration_time",
+ "ScaleUnit": "1MB/s",
+ "BriefDescription": "Average SLC-to-memory write bandwidth for local GMEM, for traffic initiated by local non-CPU devices.",
+ "PublicDescription": "Average SLC-to-memory write bandwidth for local GMEM, for traffic initiated by local non-CPU devices such as the GPU and PCIe devices. Includes write-backs, attributed as described for UCF_SLC_WB. Data-bearing snoop responses to evictions by a home SLC in another socket or a connected GPU's GL2 are not counted (see UCF_SLC_WB).",
+ "Unit": "nvidia_ucf_pmu_"
+ },
+ {
+ "MetricName": "ucf_avg_slc_rd_bandwidth_local_noncpu_to_local_cxlmem",
+ "MetricGroup": "UCF_BW_Upstream_RD;UCF_BW_Local_NonCPU;UCF_BW_Local_CXLMEM;UCF_BW_Local_NonCPU_To_Local_CXLMEM",
+ "MetricExpr": "UCF_SLC_BYTES_RD@src_loc_noncpu=1,dst_loc_other=1@ / 1e6 / duration_time",
+ "ScaleUnit": "1MB/s",
+ "BriefDescription": "Average requester-to-SLC read bandwidth for local non-CPU requests to local CXL memory addresses.",
+ "PublicDescription": "Average requester-to-SLC read bandwidth of requests from local non-CPU devices such as the GPU and PCIe devices for local CXL memory addresses.",
+ "Unit": "nvidia_ucf_pmu_"
+ },
+ {
+ "MetricName": "ucf_avg_mem_rd_bandwidth_local_noncpu_to_local_cxlmem",
+ "MetricGroup": "UCF_BW_Downstream_RD;UCF_BW_Local_NonCPU;UCF_BW_Local_CXLMEM;UCF_BW_Local_NonCPU_To_Local_CXLMEM",
+ "MetricExpr": "UCF_MEM_BYTES_RD@src_loc_noncpu=1,dst_loc_other=1@ / 1e6 / duration_time",
+ "ScaleUnit": "1MB/s",
+ "BriefDescription": "Average SLC-to-memory read bandwidth for local CXL memory, for requests initiated by local non-CPU devices.",
+ "PublicDescription": "Average SLC-to-memory read bandwidth for local CXL memory, for requests initiated by local non-CPU devices such as the GPU and PCIe devices.",
+ "Unit": "nvidia_ucf_pmu_"
+ },
+ {
+ "MetricName": "ucf_avg_slc_wr_bandwidth_local_noncpu_to_local_cxlmem",
+ "MetricGroup": "UCF_BW_Upstream_WR;UCF_BW_Local_NonCPU;UCF_BW_Local_CXLMEM;UCF_BW_Local_NonCPU_To_Local_CXLMEM",
+ "MetricExpr": "UCF_SLC_BYTES_WR@src_loc_noncpu=1,dst_loc_other=1@ / 1e6 / duration_time",
+ "ScaleUnit": "1MB/s",
+ "BriefDescription": "Average requester-to-SLC write bandwidth for local non-CPU requests to local CXL memory addresses.",
+ "PublicDescription": "Average requester-to-SLC write bandwidth of requests from local non-CPU devices such as the GPU and PCIe devices for local CXL memory addresses.",
+ "Unit": "nvidia_ucf_pmu_"
+ },
+ {
+ "MetricName": "ucf_avg_mem_wr_bandwidth_local_noncpu_to_local_cxlmem",
+ "MetricGroup": "UCF_BW_Downstream_WR;UCF_BW_Local_NonCPU;UCF_BW_Local_CXLMEM;UCF_BW_Local_NonCPU_To_Local_CXLMEM",
+ "MetricExpr": "UCF_MEM_BYTES_WR@src_loc_noncpu=1,dst_loc_other=1@ / 1e6 / duration_time",
+ "ScaleUnit": "1MB/s",
+ "BriefDescription": "Average SLC-to-memory write bandwidth for local CXL memory, for traffic initiated by local non-CPU devices.",
+ "PublicDescription": "Average SLC-to-memory write bandwidth for local CXL memory, for traffic initiated by local non-CPU devices such as the GPU and PCIe devices. Includes write-backs, attributed as described for UCF_SLC_WB.",
+ "Unit": "nvidia_ucf_pmu_"
+ },
+ {
+ "MetricName": "ucf_avg_slc_rd_bandwidth_local_noncpu_to_remote_mem",
+ "MetricGroup": "UCF_BW_Upstream_RD;UCF_BW_Local_NonCPU;UCF_BW_Remote_Memory;UCF_BW_Local_NonCPU_To_Remote_Memory",
+ "MetricExpr": "UCF_SLC_BYTES_RD@src_loc_noncpu=1,dst_rem=1@ / 1e6 / duration_time",
+ "ScaleUnit": "1MB/s",
+ "BriefDescription": "Average requester-to-SLC read bandwidth for local non-CPU requests to remote memory addresses.",
+ "PublicDescription": "Average requester-to-SLC read bandwidth of requests from local non-CPU devices such as the GPU and PCIe devices for remote memory addresses.",
+ "Unit": "nvidia_ucf_pmu_"
+ },
+ {
+ "MetricName": "ucf_avg_mem_rd_bandwidth_local_noncpu_to_remote_mem",
+ "MetricGroup": "UCF_BW_Downstream_RD;UCF_BW_Local_NonCPU;UCF_BW_Remote_Memory;UCF_BW_Local_NonCPU_To_Remote_Memory",
+ "MetricExpr": "UCF_MEM_BYTES_RD@src_loc_noncpu=1,dst_rem=1@ / 1e6 / duration_time",
+ "ScaleUnit": "1MB/s",
+ "BriefDescription": "Average SLC-to-memory read bandwidth for remote memory, for requests initiated by local non-CPU devices.",
+ "PublicDescription": "Average SLC-to-memory read bandwidth for remote memory, for requests initiated by local non-CPU devices such as the GPU and PCIe devices.",
+ "Unit": "nvidia_ucf_pmu_"
+ },
+ {
+ "MetricName": "ucf_avg_slc_wr_bandwidth_local_noncpu_to_remote_mem",
+ "MetricGroup": "UCF_BW_Upstream_WR;UCF_BW_Local_NonCPU;UCF_BW_Remote_Memory;UCF_BW_Local_NonCPU_To_Remote_Memory",
+ "MetricExpr": "UCF_SLC_BYTES_WR@src_loc_noncpu=1,dst_rem=1@ / 1e6 / duration_time",
+ "ScaleUnit": "1MB/s",
+ "BriefDescription": "Average requester-to-SLC write bandwidth for local non-CPU requests to remote memory addresses.",
+ "PublicDescription": "Average requester-to-SLC write bandwidth of requests from local non-CPU devices such as the GPU and PCIe devices for remote memory addresses.",
+ "Unit": "nvidia_ucf_pmu_"
+ },
+ {
+ "MetricName": "ucf_avg_mem_wr_bandwidth_local_noncpu_to_remote_mem",
+ "MetricGroup": "UCF_BW_Downstream_WR;UCF_BW_Local_NonCPU;UCF_BW_Remote_Memory;UCF_BW_Local_NonCPU_To_Remote_Memory",
+ "MetricExpr": "UCF_MEM_BYTES_WR@src_loc_noncpu=1,dst_rem=1@ / 1e6 / duration_time",
+ "ScaleUnit": "1MB/s",
+ "BriefDescription": "Average SLC-to-memory write bandwidth for remote memory, for traffic initiated by local non-CPU devices.",
+ "PublicDescription": "Average SLC-to-memory write bandwidth for remote memory, for traffic initiated by local non-CPU devices such as the GPU and PCIe devices. Includes write-backs, attributed as described for UCF_SLC_WB. Data-bearing snoop responses to evictions by a home SLC in another socket or a connected GPU's GL2 are not counted (see UCF_SLC_WB).",
+ "Unit": "nvidia_ucf_pmu_"
+ },
+ {
+ "MetricName": "ucf_avg_slc_rd_bandwidth_remote_to_local_cmem",
+ "MetricGroup": "UCF_BW_Upstream_RD;UCF_BW_Remote_Source;UCF_BW_Local_CMEM;UCF_BW_Remote_To_Local_CMEM",
+ "MetricExpr": "UCF_SLC_BYTES_RD@src_rem=1,dst_loc_cmem=1@ / 1e6 / duration_time",
+ "ScaleUnit": "1MB/s",
+ "BriefDescription": "Average requester-to-SLC read bandwidth for remote-socket requests to local CMEM addresses.",
+ "PublicDescription": "Average requester-to-SLC read bandwidth of requests from a remote socket for local CMEM addresses.",
+ "Unit": "nvidia_ucf_pmu_"
+ },
+ {
+ "MetricName": "ucf_avg_mem_rd_bandwidth_remote_to_local_cmem",
+ "MetricGroup": "UCF_BW_Downstream_RD;UCF_BW_Remote_Source;UCF_BW_Local_CMEM;UCF_BW_Remote_To_Local_CMEM",
+ "MetricExpr": "UCF_MEM_BYTES_RD@src_rem=1,dst_loc_cmem=1@ / 1e6 / duration_time",
+ "ScaleUnit": "1MB/s",
+ "BriefDescription": "Average SLC-to-memory read bandwidth for local CMEM, for requests initiated by a remote socket.",
+ "PublicDescription": "Average SLC-to-memory read bandwidth for local CMEM, for requests initiated by a remote socket.",
+ "Unit": "nvidia_ucf_pmu_"
+ },
+ {
+ "MetricName": "ucf_avg_slc_wr_bandwidth_remote_to_local_cmem",
+ "MetricGroup": "UCF_BW_Upstream_WR;UCF_BW_Remote_Source;UCF_BW_Local_CMEM;UCF_BW_Remote_To_Local_CMEM",
+ "MetricExpr": "UCF_SLC_BYTES_WR@src_rem=1,dst_loc_cmem=1@ / 1e6 / duration_time",
+ "ScaleUnit": "1MB/s",
+ "BriefDescription": "Average requester-to-SLC write bandwidth for remote-socket requests to local CMEM addresses.",
+ "PublicDescription": "Average requester-to-SLC write bandwidth of requests from a remote socket for local CMEM addresses.",
+ "Unit": "nvidia_ucf_pmu_"
+ },
+ {
+ "MetricName": "ucf_avg_mem_wr_bandwidth_remote_to_local_cmem",
+ "MetricGroup": "UCF_BW_Downstream_WR;UCF_BW_Remote_Source;UCF_BW_Local_CMEM;UCF_BW_Remote_To_Local_CMEM",
+ "MetricExpr": "UCF_MEM_BYTES_WR@src_rem=1,dst_loc_cmem=1@ / 1e6 / duration_time",
+ "ScaleUnit": "1MB/s",
+ "BriefDescription": "Average SLC-to-memory write bandwidth for local CMEM, for traffic initiated by a remote socket.",
+ "PublicDescription": "Average SLC-to-memory write bandwidth for local CMEM, for traffic initiated by a remote socket. Includes write-backs, attributed as described for UCF_SLC_WB.",
+ "Unit": "nvidia_ucf_pmu_"
+ },
+ {
+ "MetricName": "ucf_avg_slc_rd_bandwidth_remote_to_local_gmem",
+ "MetricGroup": "UCF_BW_Upstream_RD;UCF_BW_Remote_Source;UCF_BW_Local_GMEM;UCF_BW_Remote_To_Local_GMEM",
+ "MetricExpr": "UCF_SLC_BYTES_RD@src_rem=1,dst_loc_gmem=1@ / 1e6 / duration_time",
+ "ScaleUnit": "1MB/s",
+ "BriefDescription": "Average requester-to-SLC read bandwidth for remote-socket requests to local GMEM addresses.",
+ "PublicDescription": "Average requester-to-SLC read bandwidth of requests from a remote socket for local GMEM addresses.",
+ "Unit": "nvidia_ucf_pmu_"
+ },
+ {
+ "MetricName": "ucf_avg_mem_rd_bandwidth_remote_to_local_gmem",
+ "MetricGroup": "UCF_BW_Downstream_RD;UCF_BW_Remote_Source;UCF_BW_Local_GMEM;UCF_BW_Remote_To_Local_GMEM",
+ "MetricExpr": "UCF_MEM_BYTES_RD@src_rem=1,dst_loc_gmem=1@ / 1e6 / duration_time",
+ "ScaleUnit": "1MB/s",
+ "BriefDescription": "Average SLC-to-memory read bandwidth for local GMEM, for requests initiated by a remote socket.",
+ "PublicDescription": "Average SLC-to-memory read bandwidth for local GMEM, for requests initiated by a remote socket.",
+ "Unit": "nvidia_ucf_pmu_"
+ },
+ {
+ "MetricName": "ucf_avg_slc_wr_bandwidth_remote_to_local_gmem",
+ "MetricGroup": "UCF_BW_Upstream_WR;UCF_BW_Remote_Source;UCF_BW_Local_GMEM;UCF_BW_Remote_To_Local_GMEM",
+ "MetricExpr": "UCF_SLC_BYTES_WR@src_rem=1,dst_loc_gmem=1@ / 1e6 / duration_time",
+ "ScaleUnit": "1MB/s",
+ "BriefDescription": "Average requester-to-SLC write bandwidth for remote-socket requests to local GMEM addresses.",
+ "PublicDescription": "Average requester-to-SLC write bandwidth of requests from a remote socket for local GMEM addresses.",
+ "Unit": "nvidia_ucf_pmu_"
+ },
+ {
+ "MetricName": "ucf_avg_mem_wr_bandwidth_remote_to_local_gmem",
+ "MetricGroup": "UCF_BW_Downstream_WR;UCF_BW_Remote_Source;UCF_BW_Local_GMEM;UCF_BW_Remote_To_Local_GMEM",
+ "MetricExpr": "UCF_MEM_BYTES_WR@src_rem=1,dst_loc_gmem=1@ / 1e6 / duration_time",
+ "ScaleUnit": "1MB/s",
+ "BriefDescription": "Average SLC-to-memory write bandwidth for local GMEM, for traffic initiated by a remote socket.",
+ "PublicDescription": "Average SLC-to-memory write bandwidth for local GMEM, for traffic initiated by a remote socket. Includes write-backs, attributed as described for UCF_SLC_WB. Data-bearing snoop responses to evictions by a home SLC in another socket or a connected GPU's GL2 are not counted (see UCF_SLC_WB).",
+ "Unit": "nvidia_ucf_pmu_"
+ },
+ {
+ "MetricName": "ucf_avg_slc_rd_bandwidth_remote_to_local_cxlmem",
+ "MetricGroup": "UCF_BW_Upstream_RD;UCF_BW_Remote_Source;UCF_BW_Local_CXLMEM;UCF_BW_Remote_To_Local_CXLMEM",
+ "MetricExpr": "UCF_SLC_BYTES_RD@src_rem=1,dst_loc_other=1@ / 1e6 / duration_time",
+ "ScaleUnit": "1MB/s",
+ "BriefDescription": "Average requester-to-SLC read bandwidth for remote-socket requests to local CXL memory addresses.",
+ "PublicDescription": "Average requester-to-SLC read bandwidth of requests from a remote socket for local CXL memory addresses.",
+ "Unit": "nvidia_ucf_pmu_"
+ },
+ {
+ "MetricName": "ucf_avg_mem_rd_bandwidth_remote_to_local_cxlmem",
+ "MetricGroup": "UCF_BW_Downstream_RD;UCF_BW_Remote_Source;UCF_BW_Local_CXLMEM;UCF_BW_Remote_To_Local_CXLMEM",
+ "MetricExpr": "UCF_MEM_BYTES_RD@src_rem=1,dst_loc_other=1@ / 1e6 / duration_time",
+ "ScaleUnit": "1MB/s",
+ "BriefDescription": "Average SLC-to-memory read bandwidth for local CXL memory, for requests initiated by a remote socket.",
+ "PublicDescription": "Average SLC-to-memory read bandwidth for local CXL memory, for requests initiated by a remote socket.",
+ "Unit": "nvidia_ucf_pmu_"
+ },
+ {
+ "MetricName": "ucf_avg_slc_wr_bandwidth_remote_to_local_cxlmem",
+ "MetricGroup": "UCF_BW_Upstream_WR;UCF_BW_Remote_Source;UCF_BW_Local_CXLMEM;UCF_BW_Remote_To_Local_CXLMEM",
+ "MetricExpr": "UCF_SLC_BYTES_WR@src_rem=1,dst_loc_other=1@ / 1e6 / duration_time",
+ "ScaleUnit": "1MB/s",
+ "BriefDescription": "Average requester-to-SLC write bandwidth for remote-socket requests to local CXL memory addresses.",
+ "PublicDescription": "Average requester-to-SLC write bandwidth of requests from a remote socket for local CXL memory addresses.",
+ "Unit": "nvidia_ucf_pmu_"
+ },
+ {
+ "MetricName": "ucf_avg_mem_wr_bandwidth_remote_to_local_cxlmem",
+ "MetricGroup": "UCF_BW_Downstream_WR;UCF_BW_Remote_Source;UCF_BW_Local_CXLMEM;UCF_BW_Remote_To_Local_CXLMEM",
+ "MetricExpr": "UCF_MEM_BYTES_WR@src_rem=1,dst_loc_other=1@ / 1e6 / duration_time",
+ "ScaleUnit": "1MB/s",
+ "BriefDescription": "Average SLC-to-memory write bandwidth for local CXL memory, for traffic initiated by a remote socket.",
+ "PublicDescription": "Average SLC-to-memory write bandwidth for local CXL memory, for traffic initiated by a remote socket. Includes write-backs, attributed as described for UCF_SLC_WB.",
+ "Unit": "nvidia_ucf_pmu_"
+ },
+ {
+ "MetricName": "ucf_avg_slc_rd_bandwidth_remote_to_remote_mem",
+ "MetricGroup": "UCF_BW_Upstream_RD;UCF_BW_Remote_Source;UCF_BW_Remote_Memory;UCF_BW_Remote_To_Remote_Memory",
+ "MetricExpr": "UCF_SLC_BYTES_RD@src_rem=1,dst_rem=1@ / 1e6 / duration_time",
+ "ScaleUnit": "1MB/s",
+ "BriefDescription": "Average requester-to-SLC read bandwidth for remote-socket requests to remote memory addresses.",
+ "PublicDescription": "Average requester-to-SLC read bandwidth of requests from a remote socket for remote memory addresses.",
+ "Unit": "nvidia_ucf_pmu_"
+ },
+ {
+ "MetricName": "ucf_avg_mem_rd_bandwidth_remote_to_remote_mem",
+ "MetricGroup": "UCF_BW_Downstream_RD;UCF_BW_Remote_Source;UCF_BW_Remote_Memory;UCF_BW_Remote_To_Remote_Memory",
+ "MetricExpr": "UCF_MEM_BYTES_RD@src_rem=1,dst_rem=1@ / 1e6 / duration_time",
+ "ScaleUnit": "1MB/s",
+ "BriefDescription": "Average SLC-to-memory read bandwidth for remote memory, for requests initiated by a remote socket.",
+ "PublicDescription": "Average SLC-to-memory read bandwidth for remote memory, for requests initiated by a remote socket.",
+ "Unit": "nvidia_ucf_pmu_"
+ },
+ {
+ "MetricName": "ucf_avg_slc_wr_bandwidth_remote_to_remote_mem",
+ "MetricGroup": "UCF_BW_Upstream_WR;UCF_BW_Remote_Source;UCF_BW_Remote_Memory;UCF_BW_Remote_To_Remote_Memory",
+ "MetricExpr": "UCF_SLC_BYTES_WR@src_rem=1,dst_rem=1@ / 1e6 / duration_time",
+ "ScaleUnit": "1MB/s",
+ "BriefDescription": "Average requester-to-SLC write bandwidth for remote-socket requests to remote memory addresses.",
+ "PublicDescription": "Average requester-to-SLC write bandwidth of requests from a remote socket for remote memory addresses.",
+ "Unit": "nvidia_ucf_pmu_"
+ },
+ {
+ "MetricName": "ucf_avg_mem_wr_bandwidth_remote_to_remote_mem",
+ "MetricGroup": "UCF_BW_Downstream_WR;UCF_BW_Remote_Source;UCF_BW_Remote_Memory;UCF_BW_Remote_To_Remote_Memory",
+ "MetricExpr": "UCF_MEM_BYTES_WR@src_rem=1,dst_rem=1@ / 1e6 / duration_time",
+ "ScaleUnit": "1MB/s",
+ "BriefDescription": "Average SLC-to-memory write bandwidth for remote memory, for traffic initiated by a remote socket.",
+ "PublicDescription": "Average SLC-to-memory write bandwidth for remote memory, for traffic initiated by a remote socket. Includes write-backs, attributed as described for UCF_SLC_WB. Data-bearing snoop responses to evictions by a home SLC in another socket or a connected GPU's GL2 are not counted (see UCF_SLC_WB).",
+ "Unit": "nvidia_ucf_pmu_"
+ }
+]
--
2.43.0
^ permalink raw reply [flat|nested] 12+ messages in thread* [PATCH v2 2/9] perf jevents: Add support for NVIDIA Tegra410 PCIE PMU aliasing
2026-10-30 17:48 [PATCH v2 0/9] perf: Add NVIDIA Tegra410 uncore PMU events and metrics Besar Wicaksono
2026-10-30 17:48 ` [PATCH v2 1/9] perf jevents: Add support for NVIDIA Tegra410 UCF PMU aliasing Besar Wicaksono
@ 2026-10-30 17:48 ` Besar Wicaksono
2026-10-30 17:48 ` [PATCH v2 3/9] perf jevents: Add support for NVIDIA Tegra410 PCIE-TGT " Besar Wicaksono
` (7 subsequent siblings)
9 siblings, 0 replies; 12+ messages in thread
From: Besar Wicaksono @ 2026-10-30 17:48 UTC (permalink / raw)
To: acme, namhyung, irogers, ctshao
Cc: linux-tegra, linux-arm-kernel, linux-perf-users, linux-kernel,
vsethi, rwiley, skelley, mochs, rajjoshi, treding, jonathanh,
john.garry, will, james.clark, mike.leach, leo.yan, mark.rutland,
alexander.shishkin, jolsa, adrian.hunter, Besar Wicaksono
Add alias support for NVIDIA Tegra410 PCIE PMU events and metrics.
Signed-off-by: Besar Wicaksono <bwicaksono@nvidia.com>
---
.../arch/arm64/nvidia/t410/uncore-pcie.json | 249 ++++++++++++++++++
1 file changed, 249 insertions(+)
create mode 100644 tools/perf/pmu-events/arch/arm64/nvidia/t410/uncore-pcie.json
diff --git a/tools/perf/pmu-events/arch/arm64/nvidia/t410/uncore-pcie.json b/tools/perf/pmu-events/arch/arm64/nvidia/t410/uncore-pcie.json
new file mode 100644
index 000000000000..3fbf1799a8bb
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/nvidia/t410/uncore-pcie.json
@@ -0,0 +1,249 @@
+[
+ {
+ "EventCode": "0x100000000",
+ "EventName": "PCIE_CYCLES",
+ "BriefDescription": "Counts cycles at the PCIe interface to the Tegra SoC data fabric.",
+ "PublicDescription": "Counts cycles at the PCIe interface to the Tegra SoC data fabric.",
+ "Unit": "nvidia_pcie_pmu_,rc_"
+ },
+ {
+ "EventCode": "0x2",
+ "EventName": "PCIE_RD_REQ",
+ "BriefDescription": "Counts read requests from PCIe devices under this PCIe root complex to memory or another PCIe device.",
+ "PublicDescription": "Counts read requests from PCIe devices under this PCIe root complex to memory or another PCIe device, where the target responds with data. Request size can be from 1 to 256 bytes. Filters: src_rp_mask selects the requesting root ports. Alternatively, src_bdf with src_bdf_en selects one requesting device (BDF); it cannot be combined with src_rp_mask and applies to all counters of this PMU. Destination filters select the memory type of the request address: dst_loc_cmem local CMEM, dst_loc_gmem local GMEM, dst_loc_pcie_p2p local PCIe peer addresses, dst_loc_pcie_cxl local CXL memory, dst_rem remote memory. This is the address's home type, not where the data currently resides; local or remote is determined by the home socket of the address. An unset source filter counts all root ports; an unset destination filter counts all destinations.",
+ "Unit": "nvidia_pcie_pmu_,rc_"
+ },
+ {
+ "EventCode": "0x3",
+ "EventName": "PCIE_WR_REQ",
+ "BriefDescription": "Counts write requests from PCIe devices under this PCIe root complex to memory or another PCIe device.",
+ "PublicDescription": "Counts write requests from PCIe devices under this PCIe root complex to memory or another PCIe device, where the PCIe device sends data. Request size can be from 1 to 256 bytes. Filters: src_rp_mask selects the requesting root ports. Alternatively, src_bdf with src_bdf_en selects one requesting device (BDF); it cannot be combined with src_rp_mask and applies to all counters of this PMU. Destination filters select the memory type of the request address: dst_loc_cmem local CMEM, dst_loc_gmem local GMEM, dst_loc_pcie_p2p local PCIe peer addresses, dst_loc_pcie_cxl local CXL memory, dst_rem remote memory. This is the address's home type, not where the data currently resides; local or remote is determined by the home socket of the address. An unset source filter counts all root ports; an unset destination filter counts all destinations.",
+ "Unit": "nvidia_pcie_pmu_,rc_"
+ },
+ {
+ "EventCode": "0x0",
+ "EventName": "PCIE_RD_BYTES",
+ "BriefDescription": "Counts bytes transferred by the read requests counted by PCIE_RD_REQ.",
+ "PublicDescription": "Counts bytes transferred by the read requests counted by PCIE_RD_REQ. Source and destination filters work as described for PCIE_RD_REQ.",
+ "Unit": "nvidia_pcie_pmu_,rc_"
+ },
+ {
+ "EventCode": "0x1",
+ "EventName": "PCIE_WR_BYTES",
+ "BriefDescription": "Counts bytes transferred by the write requests counted by PCIE_WR_REQ.",
+ "PublicDescription": "Counts bytes transferred by the write requests counted by PCIE_WR_REQ. Source and destination filters work as described for PCIE_WR_REQ.",
+ "Unit": "nvidia_pcie_pmu_,rc_"
+ },
+ {
+ "EventCode": "0x4",
+ "EventName": "PCIE_RD_CUM_OUTS",
+ "BriefDescription": "Accumulates the outstanding read requests counted by PCIE_RD_REQ each cycle at the PCIe interface.",
+ "PublicDescription": "Accumulates the outstanding read requests counted by PCIE_RD_REQ each cycle at the PCIe interface. Pair the two under the same filters for the average read latency. Source and destination filters work as described for PCIE_RD_REQ.",
+ "Unit": "nvidia_pcie_pmu_,rc_"
+ },
+ {
+ "MetricName": "pcie_freq",
+ "MetricGroup": "PCIE_Frequency;PCIE_Read_Latency",
+ "MetricConstraint": "NO_GROUP_EVENTS",
+ "MetricExpr": "(PCIE_CYCLES / aggr_nr(PCIE_CYCLES)) / 1e9 / duration_time",
+ "ScaleUnit": "1GHz",
+ "BriefDescription": "Frequency of the cycles at the PCIe interface to the Tegra SoC data fabric.",
+ "PublicDescription": "Average frequency of the cycles at the PCIe interface to the Tegra SoC data fabric over the measurement interval.",
+ "Unit": "nvidia_pcie_pmu_,rc_"
+ },
+ {
+ "MetricName": "pcie_avg_rd_bandwidth_to_all_dst",
+ "MetricGroup": "PCIE_Bandwidth;PCIE_To_All_Destinations",
+ "MetricExpr": "PCIE_RD_BYTES@dst_loc_cmem=1,dst_loc_gmem=1,dst_loc_pcie_p2p=1,dst_loc_pcie_cxl=1,dst_rem=1@ / 1e6 / duration_time",
+ "ScaleUnit": "1MB/s",
+ "BriefDescription": "Average read bandwidth from PCIe devices under this PCIe root complex to all destinations.",
+ "PublicDescription": "Average read bandwidth of requests from all PCIe devices under this PCIe root complex to all destinations: local CMEM, local GMEM, local PCIe peer addresses, local CXL memory and remote memory.",
+ "Unit": "nvidia_pcie_pmu_,rc_"
+ },
+ {
+ "MetricName": "pcie_avg_wr_bandwidth_to_all_dst",
+ "MetricGroup": "PCIE_Bandwidth;PCIE_To_All_Destinations",
+ "MetricExpr": "PCIE_WR_BYTES@dst_loc_cmem=1,dst_loc_gmem=1,dst_loc_pcie_p2p=1,dst_loc_pcie_cxl=1,dst_rem=1@ / 1e6 / duration_time",
+ "ScaleUnit": "1MB/s",
+ "BriefDescription": "Average write bandwidth from PCIe devices under this PCIe root complex to all destinations.",
+ "PublicDescription": "Average write bandwidth of requests from all PCIe devices under this PCIe root complex to all destinations: local CMEM, local GMEM, local PCIe peer addresses, local CXL memory and remote memory.",
+ "Unit": "nvidia_pcie_pmu_,rc_"
+ },
+ {
+ "MetricName": "pcie_avg_bandwidth_to_all_dst",
+ "MetricGroup": "PCIE_Bandwidth;PCIE_To_All_Destinations",
+ "MetricExpr": "pcie_avg_rd_bandwidth_to_all_dst + pcie_avg_wr_bandwidth_to_all_dst",
+ "ScaleUnit": "1MB/s",
+ "BriefDescription": "Average read and write bandwidth from PCIe devices under this PCIe root complex to all destinations.",
+ "PublicDescription": "Average read and write bandwidth of requests from all PCIe devices under this PCIe root complex to all destinations: local CMEM, local GMEM, local PCIe peer addresses, local CXL memory and remote memory.",
+ "Unit": "nvidia_pcie_pmu_,rc_"
+ },
+ {
+ "MetricName": "pcie_avg_rd_latency_to_all_dst",
+ "MetricGroup": "PCIE_Read_Latency;PCIE_To_All_Destinations",
+ "MetricConstraint": "NO_GROUP_EVENTS",
+ "MetricExpr": "(PCIE_RD_CUM_OUTS@dst_loc_cmem=1,dst_loc_gmem=1,dst_loc_pcie_p2p=1,dst_loc_pcie_cxl=1,dst_rem=1@ / PCIE_RD_REQ@dst_loc_cmem=1,dst_loc_gmem=1,dst_loc_pcie_p2p=1,dst_loc_pcie_cxl=1,dst_rem=1@) / pcie_freq",
+ "ScaleUnit": "1ns/request",
+ "BriefDescription": "Average read latency from PCIe devices under this PCIe root complex to all destinations.",
+ "PublicDescription": "Average latency of read requests from all PCIe devices under this PCIe root complex to all destinations: local CMEM, local GMEM, local PCIe peer addresses, local CXL memory and remote memory.",
+ "Unit": "nvidia_pcie_pmu_,rc_"
+ },
+ {
+ "MetricName": "pcie_avg_rd_bandwidth_to_local_dst",
+ "MetricGroup": "PCIE_Bandwidth;PCIE_To_Local_Destinations",
+ "MetricExpr": "pcie_avg_rd_bandwidth_to_local_cmem + pcie_avg_rd_bandwidth_to_local_gmem + pcie_avg_rd_bandwidth_to_local_pcie_peer + pcie_avg_rd_bandwidth_to_local_cxlmem",
+ "ScaleUnit": "1MB/s",
+ "BriefDescription": "Average read bandwidth from PCIe devices under this PCIe root complex to local destinations.",
+ "PublicDescription": "Average read bandwidth of requests from all PCIe devices under this PCIe root complex to local destinations: local CMEM, local GMEM, local PCIe peer addresses and local CXL memory.",
+ "Unit": "nvidia_pcie_pmu_,rc_"
+ },
+ {
+ "MetricName": "pcie_avg_wr_bandwidth_to_local_dst",
+ "MetricGroup": "PCIE_Bandwidth;PCIE_To_Local_Destinations",
+ "MetricExpr": "pcie_avg_wr_bandwidth_to_local_cmem + pcie_avg_wr_bandwidth_to_local_gmem + pcie_avg_wr_bandwidth_to_local_pcie_peer + pcie_avg_wr_bandwidth_to_local_cxlmem",
+ "ScaleUnit": "1MB/s",
+ "BriefDescription": "Average write bandwidth from PCIe devices under this PCIe root complex to local destinations.",
+ "PublicDescription": "Average write bandwidth of requests from all PCIe devices under this PCIe root complex to local destinations: local CMEM, local GMEM, local PCIe peer addresses and local CXL memory.",
+ "Unit": "nvidia_pcie_pmu_,rc_"
+ },
+ {
+ "MetricName": "pcie_avg_rd_bandwidth_to_local_cmem",
+ "MetricGroup": "PCIE_Bandwidth;PCIE_Read;PCIE_To_Local_CMEM",
+ "MetricExpr": "PCIE_RD_BYTES@dst_loc_cmem=1@ / 1e6 / duration_time",
+ "ScaleUnit": "1MB/s",
+ "BriefDescription": "Average read bandwidth from PCIe devices under this PCIe root complex to local CMEM.",
+ "PublicDescription": "Average read bandwidth of requests from all PCIe devices under this PCIe root complex to local CMEM.",
+ "Unit": "nvidia_pcie_pmu_,rc_"
+ },
+ {
+ "MetricName": "pcie_avg_wr_bandwidth_to_local_cmem",
+ "MetricGroup": "PCIE_Bandwidth;PCIE_Write;PCIE_To_Local_CMEM",
+ "MetricExpr": "PCIE_WR_BYTES@dst_loc_cmem=1@ / 1e6 / duration_time",
+ "ScaleUnit": "1MB/s",
+ "BriefDescription": "Average write bandwidth from PCIe devices under this PCIe root complex to local CMEM.",
+ "PublicDescription": "Average write bandwidth of requests from all PCIe devices under this PCIe root complex to local CMEM.",
+ "Unit": "nvidia_pcie_pmu_,rc_"
+ },
+ {
+ "MetricName": "pcie_avg_rd_latency_to_local_cmem",
+ "MetricGroup": "PCIE_Read_Latency;PCIE_Read;PCIE_To_Local_CMEM",
+ "MetricConstraint": "NO_GROUP_EVENTS",
+ "MetricExpr": "(PCIE_RD_CUM_OUTS@dst_loc_cmem=1@ / PCIE_RD_REQ@dst_loc_cmem=1@) / pcie_freq",
+ "ScaleUnit": "1ns/request",
+ "BriefDescription": "Average read latency from PCIe devices under this PCIe root complex to local CMEM.",
+ "PublicDescription": "Average latency of read requests from all PCIe devices under this PCIe root complex to local CMEM.",
+ "Unit": "nvidia_pcie_pmu_,rc_"
+ },
+ {
+ "MetricName": "pcie_avg_rd_bandwidth_to_local_gmem",
+ "MetricGroup": "PCIE_Bandwidth;PCIE_Read;PCIE_To_Local_GMEM",
+ "MetricExpr": "PCIE_RD_BYTES@dst_loc_gmem=1@ / 1e6 / duration_time",
+ "ScaleUnit": "1MB/s",
+ "BriefDescription": "Average read bandwidth from PCIe devices under this PCIe root complex to local GMEM.",
+ "PublicDescription": "Average read bandwidth of requests from all PCIe devices under this PCIe root complex to local GMEM.",
+ "Unit": "nvidia_pcie_pmu_,rc_"
+ },
+ {
+ "MetricName": "pcie_avg_wr_bandwidth_to_local_gmem",
+ "MetricGroup": "PCIE_Bandwidth;PCIE_Write;PCIE_To_Local_GMEM",
+ "MetricExpr": "PCIE_WR_BYTES@dst_loc_gmem=1@ / 1e6 / duration_time",
+ "ScaleUnit": "1MB/s",
+ "BriefDescription": "Average write bandwidth from PCIe devices under this PCIe root complex to local GMEM.",
+ "PublicDescription": "Average write bandwidth of requests from all PCIe devices under this PCIe root complex to local GMEM.",
+ "Unit": "nvidia_pcie_pmu_,rc_"
+ },
+ {
+ "MetricName": "pcie_avg_rd_latency_to_local_gmem",
+ "MetricGroup": "PCIE_Read_Latency;PCIE_Read;PCIE_To_Local_GMEM",
+ "MetricConstraint": "NO_GROUP_EVENTS",
+ "MetricExpr": "(PCIE_RD_CUM_OUTS@dst_loc_gmem=1@ / PCIE_RD_REQ@dst_loc_gmem=1@) / pcie_freq",
+ "ScaleUnit": "1ns/request",
+ "BriefDescription": "Average read latency from PCIe devices under this PCIe root complex to local GMEM.",
+ "PublicDescription": "Average latency of read requests from all PCIe devices under this PCIe root complex to local GMEM.",
+ "Unit": "nvidia_pcie_pmu_,rc_"
+ },
+ {
+ "MetricName": "pcie_avg_rd_bandwidth_to_local_cxlmem",
+ "MetricGroup": "PCIE_Bandwidth;PCIE_Read;PCIE_To_Local_CXLMEM",
+ "MetricExpr": "PCIE_RD_BYTES@dst_loc_pcie_cxl=1@ / 1e6 / duration_time",
+ "ScaleUnit": "1MB/s",
+ "BriefDescription": "Average read bandwidth from PCIe devices under this PCIe root complex to local CXL memory.",
+ "PublicDescription": "Average read bandwidth of requests from all PCIe devices under this PCIe root complex to local CXL memory.",
+ "Unit": "nvidia_pcie_pmu_,rc_"
+ },
+ {
+ "MetricName": "pcie_avg_wr_bandwidth_to_local_cxlmem",
+ "MetricGroup": "PCIE_Bandwidth;PCIE_Write;PCIE_To_Local_CXLMEM",
+ "MetricExpr": "PCIE_WR_BYTES@dst_loc_pcie_cxl=1@ / 1e6 / duration_time",
+ "ScaleUnit": "1MB/s",
+ "BriefDescription": "Average write bandwidth from PCIe devices under this PCIe root complex to local CXL memory.",
+ "PublicDescription": "Average write bandwidth of requests from all PCIe devices under this PCIe root complex to local CXL memory.",
+ "Unit": "nvidia_pcie_pmu_,rc_"
+ },
+ {
+ "MetricName": "pcie_avg_rd_latency_to_local_cxlmem",
+ "MetricGroup": "PCIE_Read_Latency;PCIE_Read;PCIE_To_Local_CXLMEM",
+ "MetricConstraint": "NO_GROUP_EVENTS",
+ "MetricExpr": "(PCIE_RD_CUM_OUTS@dst_loc_pcie_cxl=1@ / PCIE_RD_REQ@dst_loc_pcie_cxl=1@) / pcie_freq",
+ "ScaleUnit": "1ns/request",
+ "BriefDescription": "Average read latency from PCIe devices under this PCIe root complex to local CXL memory.",
+ "PublicDescription": "Average latency of read requests from all PCIe devices under this PCIe root complex to local CXL memory.",
+ "Unit": "nvidia_pcie_pmu_,rc_"
+ },
+ {
+ "MetricName": "pcie_avg_rd_bandwidth_to_remote_mem",
+ "MetricGroup": "PCIE_Bandwidth;PCIE_Read;PCIE_To_Remote_Memory",
+ "MetricExpr": "PCIE_RD_BYTES@dst_rem=1@ / 1e6 / duration_time",
+ "ScaleUnit": "1MB/s",
+ "BriefDescription": "Average read bandwidth from PCIe devices under this PCIe root complex to remote memory.",
+ "PublicDescription": "Average read bandwidth of requests from all PCIe devices under this PCIe root complex to remote memory.",
+ "Unit": "nvidia_pcie_pmu_,rc_"
+ },
+ {
+ "MetricName": "pcie_avg_wr_bandwidth_to_remote_mem",
+ "MetricGroup": "PCIE_Bandwidth;PCIE_Write;PCIE_To_Remote_Memory",
+ "MetricExpr": "PCIE_WR_BYTES@dst_rem=1@ / 1e6 / duration_time",
+ "ScaleUnit": "1MB/s",
+ "BriefDescription": "Average write bandwidth from PCIe devices under this PCIe root complex to remote memory.",
+ "PublicDescription": "Average write bandwidth of requests from all PCIe devices under this PCIe root complex to remote memory.",
+ "Unit": "nvidia_pcie_pmu_,rc_"
+ },
+ {
+ "MetricName": "pcie_avg_rd_latency_to_remote_mem",
+ "MetricGroup": "PCIE_Read_Latency;PCIE_Read;PCIE_To_Remote_Memory",
+ "MetricConstraint": "NO_GROUP_EVENTS",
+ "MetricExpr": "(PCIE_RD_CUM_OUTS@dst_rem=1@ / PCIE_RD_REQ@dst_rem=1@) / pcie_freq",
+ "ScaleUnit": "1ns/request",
+ "BriefDescription": "Average read latency from PCIe devices under this PCIe root complex to remote memory.",
+ "PublicDescription": "Average latency of read requests from all PCIe devices under this PCIe root complex to remote memory.",
+ "Unit": "nvidia_pcie_pmu_,rc_"
+ },
+ {
+ "MetricName": "pcie_avg_rd_bandwidth_to_local_pcie_peer",
+ "MetricGroup": "PCIE_Bandwidth;PCIE_Read;PCIE_To_Local_PCIE_Peer",
+ "MetricExpr": "PCIE_RD_BYTES@dst_loc_pcie_p2p=1@ / 1e6 / duration_time",
+ "ScaleUnit": "1MB/s",
+ "BriefDescription": "Average read bandwidth from PCIe devices under this PCIe root complex to local PCIe peer addresses.",
+ "PublicDescription": "Average read bandwidth of requests from all PCIe devices under this PCIe root complex to local PCIe peer addresses.",
+ "Unit": "nvidia_pcie_pmu_,rc_"
+ },
+ {
+ "MetricName": "pcie_avg_wr_bandwidth_to_local_pcie_peer",
+ "MetricGroup": "PCIE_Bandwidth;PCIE_Write;PCIE_To_Local_PCIE_Peer",
+ "MetricExpr": "PCIE_WR_BYTES@dst_loc_pcie_p2p=1@ / 1e6 / duration_time",
+ "ScaleUnit": "1MB/s",
+ "BriefDescription": "Average write bandwidth from PCIe devices under this PCIe root complex to local PCIe peer addresses.",
+ "PublicDescription": "Average write bandwidth of requests from all PCIe devices under this PCIe root complex to local PCIe peer addresses.",
+ "Unit": "nvidia_pcie_pmu_,rc_"
+ },
+ {
+ "MetricName": "pcie_avg_rd_latency_to_local_pcie_peer",
+ "MetricGroup": "PCIE_Read_Latency;PCIE_Read;PCIE_To_Local_PCIE_Peer",
+ "MetricConstraint": "NO_GROUP_EVENTS",
+ "MetricExpr": "(PCIE_RD_CUM_OUTS@dst_loc_pcie_p2p=1@ / PCIE_RD_REQ@dst_loc_pcie_p2p=1@) / pcie_freq",
+ "ScaleUnit": "1ns/request",
+ "BriefDescription": "Average read latency from PCIe devices under this PCIe root complex to local PCIe peer addresses.",
+ "PublicDescription": "Average latency of read requests from all PCIe devices under this PCIe root complex to local PCIe peer addresses.",
+ "Unit": "nvidia_pcie_pmu_,rc_"
+ }
+]
--
2.43.0
^ permalink raw reply [flat|nested] 12+ messages in thread* [PATCH v2 3/9] perf jevents: Add support for NVIDIA Tegra410 PCIE-TGT PMU aliasing
2026-10-30 17:48 [PATCH v2 0/9] perf: Add NVIDIA Tegra410 uncore PMU events and metrics Besar Wicaksono
2026-10-30 17:48 ` [PATCH v2 1/9] perf jevents: Add support for NVIDIA Tegra410 UCF PMU aliasing Besar Wicaksono
2026-10-30 17:48 ` [PATCH v2 2/9] perf jevents: Add support for NVIDIA Tegra410 PCIE " Besar Wicaksono
@ 2026-10-30 17:48 ` Besar Wicaksono
2026-10-30 17:48 ` [PATCH v2 4/9] perf jevents: Add support for NVIDIA Tegra410 CPU Memory Latency " Besar Wicaksono
` (6 subsequent siblings)
9 siblings, 0 replies; 12+ messages in thread
From: Besar Wicaksono @ 2026-10-30 17:48 UTC (permalink / raw)
To: acme, namhyung, irogers, ctshao
Cc: linux-tegra, linux-arm-kernel, linux-perf-users, linux-kernel,
vsethi, rwiley, skelley, mochs, rajjoshi, treding, jonathanh,
john.garry, will, james.clark, mike.leach, leo.yan, mark.rutland,
alexander.shishkin, jolsa, adrian.hunter, Besar Wicaksono
Add alias support for NVIDIA Tegra410 PCIE-TGT PMU events and metrics.
Signed-off-by: Besar Wicaksono <bwicaksono@nvidia.com>
---
.../arm64/nvidia/t410/uncore-pcie_tgt.json | 83 +++++++++++++++++++
1 file changed, 83 insertions(+)
create mode 100644 tools/perf/pmu-events/arch/arm64/nvidia/t410/uncore-pcie_tgt.json
diff --git a/tools/perf/pmu-events/arch/arm64/nvidia/t410/uncore-pcie_tgt.json b/tools/perf/pmu-events/arch/arm64/nvidia/t410/uncore-pcie_tgt.json
new file mode 100644
index 000000000000..0f4765042d1f
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/nvidia/t410/uncore-pcie_tgt.json
@@ -0,0 +1,83 @@
+[
+ {
+ "EventCode": "0x4",
+ "EventName": "PCIE_TGT_CYCLES",
+ "BriefDescription": "Counts cycles at the PCIe interface to the Tegra SoC data fabric.",
+ "PublicDescription": "Counts cycles at the PCIe interface to the Tegra SoC data fabric.",
+ "Unit": "nvidia_pcie_tgt_pmu_,rc_"
+ },
+ {
+ "EventCode": "0x2",
+ "EventName": "PCIE_TGT_RD_REQ",
+ "BriefDescription": "Counts read requests from any source to PCIe BAR or CXL HDM ranges under this PCIe root complex.",
+ "PublicDescription": "Counts read requests from any source to PCIe BAR or CXL HDM ranges under this PCIe root complex, where the target responds with data. Request size can be from 1 to 256 bytes. Filters: dst_rp_mask selects PCIe BAR traffic to root ports (bit n = root port n). dst_addr_en with dst_addr_base and dst_addr_mask selects PCIe BAR or CXL HDM addresses that equal the base in the mask's set bits. If both dst_rp_mask and the address filter are set, a request matching either is counted. With no filter, PCIe BAR traffic to all root ports is counted.",
+ "Unit": "nvidia_pcie_tgt_pmu_,rc_"
+ },
+ {
+ "EventCode": "0x3",
+ "EventName": "PCIE_TGT_WR_REQ",
+ "BriefDescription": "Counts write requests from any source to PCIe BAR or CXL HDM ranges under this PCIe root complex.",
+ "PublicDescription": "Counts write requests from any source to PCIe BAR or CXL HDM ranges under this PCIe root complex, where the source sends data. Request size can be from 1 to 256 bytes. Filters: dst_rp_mask selects PCIe BAR traffic to root ports (bit n = root port n). dst_addr_en with dst_addr_base and dst_addr_mask selects PCIe BAR or CXL HDM addresses that equal the base in the mask's set bits. If both dst_rp_mask and the address filter are set, a request matching either is counted. With no filter, PCIe BAR traffic to all root ports is counted.",
+ "Unit": "nvidia_pcie_tgt_pmu_,rc_"
+ },
+ {
+ "EventCode": "0x0",
+ "EventName": "PCIE_TGT_RD_BYTES",
+ "BriefDescription": "Counts bytes transferred by the read requests counted by PCIE_TGT_RD_REQ.",
+ "PublicDescription": "Counts bytes transferred by the read requests counted by PCIE_TGT_RD_REQ. Destination filters work as described for PCIE_TGT_RD_REQ.",
+ "Unit": "nvidia_pcie_tgt_pmu_,rc_"
+ },
+ {
+ "EventCode": "0x1",
+ "EventName": "PCIE_TGT_WR_BYTES",
+ "BriefDescription": "Counts bytes transferred by the write requests counted by PCIE_TGT_WR_REQ.",
+ "PublicDescription": "Counts bytes transferred by the write requests counted by PCIE_TGT_WR_REQ. Destination filters work as described for PCIE_TGT_WR_REQ.",
+ "Unit": "nvidia_pcie_tgt_pmu_,rc_"
+ },
+ {
+ "MetricName": "pcie_tgt_freq",
+ "MetricGroup": "PCIE_TGT_Frequency",
+ "MetricConstraint": "NO_GROUP_EVENTS",
+ "MetricExpr": "(PCIE_TGT_CYCLES / aggr_nr(PCIE_TGT_CYCLES)) / 1e9 / duration_time",
+ "ScaleUnit": "1GHz",
+ "BriefDescription": "Frequency of the cycles at the PCIe interface to the Tegra SoC data fabric.",
+ "PublicDescription": "Average frequency of the cycles at the PCIe interface to the Tegra SoC data fabric over the measurement interval.",
+ "Unit": "nvidia_pcie_tgt_pmu_,rc_"
+ },
+ {
+ "MetricName": "pcie_tgt_avg_rd_bandwidth_to_all_dst",
+ "MetricGroup": "PCIE_TGT_Bandwidth;PCIE_TGT_BW_PCIE_BAR_CXL_HDM",
+ "MetricExpr": "PCIE_TGT_RD_BYTES@dst_addr_en=1,dst_addr_base=0,dst_addr_mask=0@ / 1e6 / duration_time",
+ "ScaleUnit": "1MB/s",
+ "BriefDescription": "Average read bandwidth to all PCIe BAR and CXL HDM ranges under this PCIe root complex.",
+ "PublicDescription": "Average read bandwidth of requests from any source to all PCIe BAR and CXL HDM ranges under this PCIe root complex.",
+ "Unit": "nvidia_pcie_tgt_pmu_,rc_"
+ },
+ {
+ "MetricName": "pcie_tgt_avg_wr_bandwidth_to_all_dst",
+ "MetricGroup": "PCIE_TGT_Bandwidth;PCIE_TGT_BW_PCIE_BAR_CXL_HDM",
+ "MetricExpr": "PCIE_TGT_WR_BYTES@dst_addr_en=1,dst_addr_base=0,dst_addr_mask=0@ / 1e6 / duration_time",
+ "ScaleUnit": "1MB/s",
+ "BriefDescription": "Average write bandwidth to all PCIe BAR and CXL HDM ranges under this PCIe root complex.",
+ "PublicDescription": "Average write bandwidth of requests from any source to all PCIe BAR and CXL HDM ranges under this PCIe root complex.",
+ "Unit": "nvidia_pcie_tgt_pmu_,rc_"
+ },
+ {
+ "MetricName": "pcie_tgt_avg_rd_bandwidth_to_pcie_bar",
+ "MetricGroup": "PCIE_TGT_Bandwidth;PCIE_TGT_BW_PCIE_BAR",
+ "MetricExpr": "PCIE_TGT_RD_BYTES / 1e6 / duration_time",
+ "ScaleUnit": "1MB/s",
+ "BriefDescription": "Average read bandwidth of PCIe BAR traffic to all root ports under this PCIe root complex.",
+ "PublicDescription": "Average read bandwidth of PCIe BAR traffic from any source to all root ports under this PCIe root complex.",
+ "Unit": "nvidia_pcie_tgt_pmu_,rc_"
+ },
+ {
+ "MetricName": "pcie_tgt_avg_wr_bandwidth_to_pcie_bar",
+ "MetricGroup": "PCIE_TGT_Bandwidth;PCIE_TGT_BW_PCIE_BAR",
+ "MetricExpr": "PCIE_TGT_WR_BYTES / 1e6 / duration_time",
+ "ScaleUnit": "1MB/s",
+ "BriefDescription": "Average write bandwidth of PCIe BAR traffic to all root ports under this PCIe root complex.",
+ "PublicDescription": "Average write bandwidth of PCIe BAR traffic from any source to all root ports under this PCIe root complex.",
+ "Unit": "nvidia_pcie_tgt_pmu_,rc_"
+ }
+]
--
2.43.0
^ permalink raw reply [flat|nested] 12+ messages in thread* [PATCH v2 4/9] perf jevents: Add support for NVIDIA Tegra410 CPU Memory Latency PMU aliasing
2026-10-30 17:48 [PATCH v2 0/9] perf: Add NVIDIA Tegra410 uncore PMU events and metrics Besar Wicaksono
` (2 preceding siblings ...)
2026-10-30 17:48 ` [PATCH v2 3/9] perf jevents: Add support for NVIDIA Tegra410 PCIE-TGT " Besar Wicaksono
@ 2026-10-30 17:48 ` Besar Wicaksono
2026-10-30 17:48 ` [PATCH v2 5/9] perf jevents: Add support for NVIDIA Tegra410 C2C " Besar Wicaksono
` (5 subsequent siblings)
9 siblings, 0 replies; 12+ messages in thread
From: Besar Wicaksono @ 2026-10-30 17:48 UTC (permalink / raw)
To: acme, namhyung, irogers, ctshao
Cc: linux-tegra, linux-arm-kernel, linux-perf-users, linux-kernel,
vsethi, rwiley, skelley, mochs, rajjoshi, treding, jonathanh,
john.garry, will, james.clark, mike.leach, leo.yan, mark.rutland,
alexander.shishkin, jolsa, adrian.hunter, Besar Wicaksono
Add alias support for NVIDIA Tegra410 CPU Memory Latency PMU events.
Signed-off-by: Besar Wicaksono <bwicaksono@nvidia.com>
---
.../arm64/nvidia/t410/uncore-cpu_mem.json | 43 +++++++++++++++++++
1 file changed, 43 insertions(+)
create mode 100644 tools/perf/pmu-events/arch/arm64/nvidia/t410/uncore-cpu_mem.json
diff --git a/tools/perf/pmu-events/arch/arm64/nvidia/t410/uncore-cpu_mem.json b/tools/perf/pmu-events/arch/arm64/nvidia/t410/uncore-cpu_mem.json
new file mode 100644
index 000000000000..bb7907935d6b
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/nvidia/t410/uncore-cpu_mem.json
@@ -0,0 +1,43 @@
+[
+ {
+ "EventCode": "0x0",
+ "EventName": "CMEM_CYCLES",
+ "BriefDescription": "Counts elapsed MSN bridge cycles for the CMEM read-latency counters.",
+ "PublicDescription": "Counts elapsed Memory Switch Node (MSN) bridge cycles for the CMEM read-latency counters. All MSN instances share this clock, so the count is read from the first instance.",
+ "Unit": "nvidia_cmem_latency_pmu_"
+ },
+ {
+ "EventCode": "0x1",
+ "EventName": "CMEM_RD_REQ",
+ "BriefDescription": "Counts local CMEM read requests at the edge of the UCF (post SLC), in 32-byte units, from all requesters.",
+ "PublicDescription": "Counts read requests at the edge of the Unified Coherence Fabric (UCF), after the System Level Cache (SLC), to local CPU DRAM (CMEM), at 32-byte granularity. A read of up to 32 bytes adds one; a 64-byte read adds two. It counts reads from all requesters, local and remote, summed over all Memory Switch Node (MSN) instances and channels. There is no requester or security-state filtering.",
+ "Unit": "nvidia_cmem_latency_pmu_"
+ },
+ {
+ "EventCode": "0x2",
+ "EventName": "CMEM_RD_CUM_OUTS",
+ "BriefDescription": "Accumulates the in-flight read requests counted by CMEM_RD_REQ each MSN bridge cycle.",
+ "PublicDescription": "Accumulates the in-flight read requests counted by CMEM_RD_REQ each Memory Switch Node (MSN) bridge cycle. Pair the two for the average read latency.",
+ "Unit": "nvidia_cmem_latency_pmu_"
+ },
+ {
+ "MetricName": "cmem_freq",
+ "MetricGroup": "CMEM_Frequency;CMEM_Read_Latency",
+ "MetricConstraint": "NO_GROUP_EVENTS",
+ "MetricExpr": "(CMEM_CYCLES / aggr_nr(CMEM_CYCLES)) / 1e9 / duration_time",
+ "ScaleUnit": "1GHz",
+ "BriefDescription": "MSN bridge clock frequency of the CMEM read-latency counters.",
+ "PublicDescription": "Average Memory Switch Node (MSN) bridge clock frequency over the measurement interval. This is the clock of the CMEM read-latency counters.",
+ "Unit": "nvidia_cmem_latency_pmu_"
+ },
+ {
+ "MetricName": "cmem_avg_rd_latency",
+ "MetricGroup": "CMEM_Read_Latency",
+ "MetricConstraint": "NO_GROUP_EVENTS",
+ "MetricExpr": "(CMEM_RD_CUM_OUTS / CMEM_RD_REQ) / cmem_freq",
+ "ScaleUnit": "1ns/request",
+ "BriefDescription": "Average local CMEM read latency from the edge of the UCF (post SLC) to CPU DRAM, for all requesters.",
+ "PublicDescription": "Average latency of the read requests counted by CMEM_RD_REQ, from the edge of the Unified Coherence Fabric (UCF), after the System Level Cache (SLC), to local CPU DRAM (CMEM).",
+ "Unit": "nvidia_cmem_latency_pmu_"
+ }
+]
--
2.43.0
^ permalink raw reply [flat|nested] 12+ messages in thread* [PATCH v2 5/9] perf jevents: Add support for NVIDIA Tegra410 C2C PMU aliasing
2026-10-30 17:48 [PATCH v2 0/9] perf: Add NVIDIA Tegra410 uncore PMU events and metrics Besar Wicaksono
` (3 preceding siblings ...)
2026-10-30 17:48 ` [PATCH v2 4/9] perf jevents: Add support for NVIDIA Tegra410 CPU Memory Latency " Besar Wicaksono
@ 2026-10-30 17:48 ` Besar Wicaksono
2026-10-30 17:48 ` [PATCH v2 6/9] perf stat: Check merged PMU instance's cpumasks when skipping zero counts Besar Wicaksono
` (4 subsequent siblings)
9 siblings, 0 replies; 12+ messages in thread
From: Besar Wicaksono @ 2026-10-30 17:48 UTC (permalink / raw)
To: acme, namhyung, irogers, ctshao
Cc: linux-tegra, linux-arm-kernel, linux-perf-users, linux-kernel,
vsethi, rwiley, skelley, mochs, rajjoshi, treding, jonathanh,
john.garry, will, james.clark, mike.leach, leo.yan, mark.rutland,
alexander.shishkin, jolsa, adrian.hunter, Besar Wicaksono
Add alias support for NVIDIA Tegra410 C2C PMU events.
Signed-off-by: Besar Wicaksono <bwicaksono@nvidia.com>
---
.../arm64/nvidia/t410/uncore-nvclink.json | 67 ++++++++++
.../arm64/nvidia/t410/uncore-nvdlink.json | 43 +++++++
.../arm64/nvidia/t410/uncore-nvlink_c2c.json | 115 ++++++++++++++++++
3 files changed, 225 insertions(+)
create mode 100644 tools/perf/pmu-events/arch/arm64/nvidia/t410/uncore-nvclink.json
create mode 100644 tools/perf/pmu-events/arch/arm64/nvidia/t410/uncore-nvdlink.json
create mode 100644 tools/perf/pmu-events/arch/arm64/nvidia/t410/uncore-nvlink_c2c.json
diff --git a/tools/perf/pmu-events/arch/arm64/nvidia/t410/uncore-nvclink.json b/tools/perf/pmu-events/arch/arm64/nvidia/t410/uncore-nvclink.json
new file mode 100644
index 000000000000..1e7f8115ff9c
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/nvidia/t410/uncore-nvclink.json
@@ -0,0 +1,67 @@
+[
+ {
+ "EventCode": "0x0",
+ "EventName": "NVCLINK_CYCLES",
+ "BriefDescription": "Counts NV-CLink interface clock cycles.",
+ "PublicDescription": "Counts NV-CLink interface clock cycles. All NV-CLink instances share this clock, so the count is read from the first instance.",
+ "Unit": "nvidia_nvclink_pmu_"
+ },
+ {
+ "EventCode": "0x1",
+ "EventName": "NVCLINK_IN_RD_CUM_OUTS",
+ "BriefDescription": "Accumulates the outstanding incoming read requests counted by NVCLINK_IN_RD_REQ each NV-CLink interface cycle.",
+ "PublicDescription": "Accumulates the outstanding incoming read requests counted by NVCLINK_IN_RD_REQ each NV-CLink interface cycle. Pair the two for the average read latency.",
+ "Unit": "nvidia_nvclink_pmu_"
+ },
+ {
+ "EventCode": "0x2",
+ "EventName": "NVCLINK_IN_RD_REQ",
+ "BriefDescription": "Counts incoming read requests from the remote Tegra SoC at the NV-CLink interface.",
+ "PublicDescription": "Counts incoming read requests from the remote Tegra SoC at the NV-CLink interface, where local memory or a local device responds with data. Request size can be from 1 to 256 bytes. The count is summed over all NV-CLink instances.",
+ "Unit": "nvidia_nvclink_pmu_"
+ },
+ {
+ "EventCode": "0x5",
+ "EventName": "NVCLINK_OUT_RD_CUM_OUTS",
+ "BriefDescription": "Accumulates the outstanding outgoing read requests counted by NVCLINK_OUT_RD_REQ each NV-CLink interface cycle.",
+ "PublicDescription": "Accumulates the outstanding outgoing read requests counted by NVCLINK_OUT_RD_REQ each NV-CLink interface cycle. Pair the two for the average read latency.",
+ "Unit": "nvidia_nvclink_pmu_"
+ },
+ {
+ "EventCode": "0x6",
+ "EventName": "NVCLINK_OUT_RD_REQ",
+ "BriefDescription": "Counts outgoing read requests from the local Tegra SoC to the remote Tegra SoC at the NV-CLink interface.",
+ "PublicDescription": "Counts outgoing read requests from the local Tegra SoC to the remote Tegra SoC at the NV-CLink interface, where memory on the remote Tegra SoC responds with data. Request size can be from 1 to 256 bytes. The count is summed over all NV-CLink instances.",
+ "Unit": "nvidia_nvclink_pmu_"
+ },
+ {
+ "MetricName": "nvclink_freq",
+ "MetricGroup": "NVCLINK_Frequency;NVCLINK_Latency;NVCLINK_Read_Latency",
+ "MetricConstraint": "NO_GROUP_EVENTS",
+ "MetricExpr": "(NVCLINK_CYCLES / aggr_nr(NVCLINK_CYCLES)) / 1e9 / duration_time",
+ "ScaleUnit": "1GHz",
+ "BriefDescription": "NV-CLink interface clock frequency.",
+ "PublicDescription": "Average NV-CLink interface clock frequency over the measurement interval.",
+ "Unit": "nvidia_nvclink_pmu_"
+ },
+ {
+ "MetricName": "nvclink_in_avg_rd_latency",
+ "MetricGroup": "NVCLINK_Latency;NVCLINK_Read_Latency;NVCLINK_Incoming",
+ "MetricConstraint": "NO_GROUP_EVENTS",
+ "MetricExpr": "(NVCLINK_IN_RD_CUM_OUTS / NVCLINK_IN_RD_REQ) / nvclink_freq",
+ "ScaleUnit": "1ns/request",
+ "BriefDescription": "Average latency of incoming read requests from the remote Tegra SoC at the NV-CLink interface.",
+ "PublicDescription": "Average latency of the incoming read requests counted by NVCLINK_IN_RD_REQ, measured at the NV-CLink interface.",
+ "Unit": "nvidia_nvclink_pmu_"
+ },
+ {
+ "MetricName": "nvclink_out_avg_rd_latency",
+ "MetricGroup": "NVCLINK_Latency;NVCLINK_Read_Latency;NVCLINK_Outgoing",
+ "MetricConstraint": "NO_GROUP_EVENTS",
+ "MetricExpr": "(NVCLINK_OUT_RD_CUM_OUTS / NVCLINK_OUT_RD_REQ) / nvclink_freq",
+ "ScaleUnit": "1ns/request",
+ "BriefDescription": "Average latency of outgoing read requests sent by the local Tegra SoC to the remote Tegra SoC at the NV-CLink interface.",
+ "PublicDescription": "Average latency of the outgoing read requests counted by NVCLINK_OUT_RD_REQ, measured at the NV-CLink interface.",
+ "Unit": "nvidia_nvclink_pmu_"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/arm64/nvidia/t410/uncore-nvdlink.json b/tools/perf/pmu-events/arch/arm64/nvidia/t410/uncore-nvdlink.json
new file mode 100644
index 000000000000..7777add3741d
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/nvidia/t410/uncore-nvdlink.json
@@ -0,0 +1,43 @@
+[
+ {
+ "EventCode": "0x0",
+ "EventName": "NVDLINK_CYCLES",
+ "BriefDescription": "Counts NV-DLink interface clock cycles.",
+ "PublicDescription": "Counts NV-DLink interface clock cycles. All NV-DLink instances share this clock, so the count is read from the first instance.",
+ "Unit": "nvidia_nvdlink_pmu_"
+ },
+ {
+ "EventCode": "0x1",
+ "EventName": "NVDLINK_IN_RD_CUM_OUTS",
+ "BriefDescription": "Accumulates the outstanding read requests counted by NVDLINK_IN_RD_REQ each NV-DLink interface cycle.",
+ "PublicDescription": "Accumulates the outstanding read requests counted by NVDLINK_IN_RD_REQ each NV-DLink interface cycle. Pair the two for the average read latency.",
+ "Unit": "nvidia_nvdlink_pmu_"
+ },
+ {
+ "EventCode": "0x2",
+ "EventName": "NVDLINK_IN_RD_REQ",
+ "BriefDescription": "Counts read requests to local CXL memory at the NV-DLink interface.",
+ "PublicDescription": "Counts read requests to local CXL memory at the NV-DLink interface, from all requesters, local and remote. Request size can be from 1 to 256 bytes. The count is summed over all NV-DLink instances.",
+ "Unit": "nvidia_nvdlink_pmu_"
+ },
+ {
+ "MetricName": "nvdlink_freq",
+ "MetricGroup": "NVDLINK_Frequency;NVDLINK_Latency;NVDLINK_Read_Latency",
+ "MetricConstraint": "NO_GROUP_EVENTS",
+ "MetricExpr": "(NVDLINK_CYCLES / aggr_nr(NVDLINK_CYCLES)) / 1e9 / duration_time",
+ "ScaleUnit": "1GHz",
+ "BriefDescription": "NV-DLink interface clock frequency.",
+ "PublicDescription": "Average NV-DLink interface clock frequency over the measurement interval.",
+ "Unit": "nvidia_nvdlink_pmu_"
+ },
+ {
+ "MetricName": "nvdlink_in_avg_rd_latency",
+ "MetricGroup": "NVDLINK_Latency;NVDLINK_Read_Latency",
+ "MetricConstraint": "NO_GROUP_EVENTS",
+ "MetricExpr": "(NVDLINK_IN_RD_CUM_OUTS / NVDLINK_IN_RD_REQ) / nvdlink_freq",
+ "ScaleUnit": "1ns/request",
+ "BriefDescription": "Average latency of read requests to local CXL memory at the NV-DLink interface.",
+ "PublicDescription": "Average latency of the read requests counted by NVDLINK_IN_RD_REQ, measured at the NV-DLink interface.",
+ "Unit": "nvidia_nvdlink_pmu_"
+ }
+]
diff --git a/tools/perf/pmu-events/arch/arm64/nvidia/t410/uncore-nvlink_c2c.json b/tools/perf/pmu-events/arch/arm64/nvidia/t410/uncore-nvlink_c2c.json
new file mode 100644
index 000000000000..48a64caaba61
--- /dev/null
+++ b/tools/perf/pmu-events/arch/arm64/nvidia/t410/uncore-nvlink_c2c.json
@@ -0,0 +1,115 @@
+[
+ {
+ "EventCode": "0x0",
+ "EventName": "NVLINK_C2C_CYCLES",
+ "BriefDescription": "Counts NVLink-C2C interface clock cycles.",
+ "PublicDescription": "Counts NVLink-C2C interface clock cycles. All NVLink-C2C instances share this clock, so the count is read from the first instance.",
+ "Unit": "nvidia_nvlink_c2c_pmu_"
+ },
+ {
+ "EventCode": "0x1",
+ "EventName": "NVLINK_C2C_IN_RD_CUM_OUTS",
+ "BriefDescription": "Accumulates the outstanding incoming read requests counted by NVLINK_C2C_IN_RD_REQ each NVLink-C2C interface cycle.",
+ "PublicDescription": "Accumulates the outstanding incoming read requests counted by NVLINK_C2C_IN_RD_REQ each NVLink-C2C interface cycle. Pair the two for the average read latency. The gpu_mask filter works as described for NVLINK_C2C_IN_RD_REQ.",
+ "Unit": "nvidia_nvlink_c2c_pmu_"
+ },
+ {
+ "EventCode": "0x2",
+ "EventName": "NVLINK_C2C_IN_RD_REQ",
+ "BriefDescription": "Counts incoming read requests from connected GPUs or a remote Tegra SoC at the NVLink-C2C interface.",
+ "PublicDescription": "Counts incoming read requests sent by connected GPUs or a remote Tegra SoC to the local Tegra SoC at the NVLink-C2C interface, where the local Tegra SoC responds with data. Request size can be from 1 to 256 bytes. The count is summed over all NVLink-C2C instances. Filters: the gpu_mask filter selects GPUs by index, one bit per GPU. This filter is available only when GPUs are connected. An unset gpu_mask counts all GPUs.",
+ "Unit": "nvidia_nvlink_c2c_pmu_"
+ },
+ {
+ "EventCode": "0x3",
+ "EventName": "NVLINK_C2C_IN_WR_CUM_OUTS",
+ "BriefDescription": "Accumulates the outstanding incoming write requests counted by NVLINK_C2C_IN_WR_REQ each NVLink-C2C interface cycle.",
+ "PublicDescription": "Accumulates the outstanding incoming write requests counted by NVLINK_C2C_IN_WR_REQ each NVLink-C2C interface cycle. Available only when GPUs are connected. Pair the two for the average write latency. The gpu_mask filter works as described for NVLINK_C2C_IN_WR_REQ.",
+ "Unit": "nvidia_nvlink_c2c_pmu_"
+ },
+ {
+ "EventCode": "0x4",
+ "EventName": "NVLINK_C2C_IN_WR_REQ",
+ "BriefDescription": "Counts incoming write requests from connected GPUs to the local Tegra SoC at the NVLink-C2C interface.",
+ "PublicDescription": "Counts incoming write requests sent by connected GPUs to the local Tegra SoC at the NVLink-C2C interface, where the GPU sends the data. Request size can be from 1 to 256 bytes. Available only when GPUs are connected. The count is summed over all NVLink-C2C instances. Filters: the gpu_mask filter selects GPUs by index, one bit per GPU. An unset gpu_mask counts all GPUs.",
+ "Unit": "nvidia_nvlink_c2c_pmu_"
+ },
+ {
+ "EventCode": "0x5",
+ "EventName": "NVLINK_C2C_OUT_RD_CUM_OUTS",
+ "BriefDescription": "Accumulates the outstanding outgoing read requests counted by NVLINK_C2C_OUT_RD_REQ each NVLink-C2C interface cycle.",
+ "PublicDescription": "Accumulates the outstanding outgoing read requests counted by NVLINK_C2C_OUT_RD_REQ each NVLink-C2C interface cycle. Pair the two for the average read latency. The gpu_mask filter works as described for NVLINK_C2C_OUT_RD_REQ.",
+ "Unit": "nvidia_nvlink_c2c_pmu_"
+ },
+ {
+ "EventCode": "0x6",
+ "EventName": "NVLINK_C2C_OUT_RD_REQ",
+ "BriefDescription": "Counts outgoing read requests to connected GPUs or a remote Tegra SoC at the NVLink-C2C interface.",
+ "PublicDescription": "Counts outgoing read requests from all requesters to connected GPUs or a remote Tegra SoC at the NVLink-C2C interface, where the GPU or remote Tegra SoC responds with data. Request size can be from 1 to 256 bytes. The count is summed over all NVLink-C2C instances. Filters: the gpu_mask filter selects GPUs by index, one bit per GPU. This filter is available only when GPUs are connected. An unset gpu_mask counts all GPUs.",
+ "Unit": "nvidia_nvlink_c2c_pmu_"
+ },
+ {
+ "EventCode": "0x7",
+ "EventName": "NVLINK_C2C_OUT_WR_CUM_OUTS",
+ "BriefDescription": "Accumulates the outstanding outgoing write requests counted by NVLINK_C2C_OUT_WR_REQ each NVLink-C2C interface cycle.",
+ "PublicDescription": "Accumulates the outstanding outgoing write requests counted by NVLINK_C2C_OUT_WR_REQ each NVLink-C2C interface cycle. Available only when GPUs are connected. Pair the two for the average write latency. The gpu_mask filter works as described for NVLINK_C2C_OUT_WR_REQ.",
+ "Unit": "nvidia_nvlink_c2c_pmu_"
+ },
+ {
+ "EventCode": "0x8",
+ "EventName": "NVLINK_C2C_OUT_WR_REQ",
+ "BriefDescription": "Counts outgoing write requests to connected GPUs at the NVLink-C2C interface.",
+ "PublicDescription": "Counts outgoing write requests from all requesters to connected GPUs at the NVLink-C2C interface, where the requester sends the data. Request size can be from 1 to 256 bytes. Available only when GPUs are connected. The count is summed over all NVLink-C2C instances. Filters: the gpu_mask filter selects GPUs by index, one bit per GPU. An unset gpu_mask counts all GPUs.",
+ "Unit": "nvidia_nvlink_c2c_pmu_"
+ },
+ {
+ "MetricName": "nvlink_c2c_freq",
+ "MetricGroup": "NVLINK_C2C_Frequency;NVLINK_C2C_Latency;NVLINK_C2C_Read_Latency;NVLINK_C2C_Write_Latency",
+ "MetricConstraint": "NO_GROUP_EVENTS",
+ "MetricExpr": "(NVLINK_C2C_CYCLES / aggr_nr(NVLINK_C2C_CYCLES)) / 1e9 / duration_time",
+ "ScaleUnit": "1GHz",
+ "BriefDescription": "NVLink-C2C interface clock frequency.",
+ "PublicDescription": "Average NVLink-C2C interface clock frequency over the measurement interval.",
+ "Unit": "nvidia_nvlink_c2c_pmu_"
+ },
+ {
+ "MetricName": "nvlink_c2c_in_avg_rd_latency",
+ "MetricGroup": "NVLINK_C2C_Latency;NVLINK_C2C_Read_Latency;NVLINK_C2C_Incoming",
+ "MetricConstraint": "NO_GROUP_EVENTS",
+ "MetricExpr": "(NVLINK_C2C_IN_RD_CUM_OUTS / NVLINK_C2C_IN_RD_REQ) / nvlink_c2c_freq",
+ "ScaleUnit": "1ns/request",
+ "BriefDescription": "Average latency of incoming read requests at the NVLink-C2C interface.",
+ "PublicDescription": "Average latency of the incoming read requests counted by NVLINK_C2C_IN_RD_REQ, measured at the NVLink-C2C interface.",
+ "Unit": "nvidia_nvlink_c2c_pmu_"
+ },
+ {
+ "MetricName": "nvlink_c2c_in_avg_wr_latency",
+ "MetricGroup": "NVLINK_C2C_Latency;NVLINK_C2C_Write_Latency;NVLINK_C2C_Incoming",
+ "MetricConstraint": "NO_GROUP_EVENTS",
+ "MetricExpr": "(NVLINK_C2C_IN_WR_CUM_OUTS / NVLINK_C2C_IN_WR_REQ) / nvlink_c2c_freq",
+ "ScaleUnit": "1ns/request",
+ "BriefDescription": "Average latency of incoming write requests from connected GPUs at the NVLink-C2C interface.",
+ "PublicDescription": "Average latency of the incoming write requests counted by NVLINK_C2C_IN_WR_REQ, measured at the NVLink-C2C interface. Available only when GPUs are connected.",
+ "Unit": "nvidia_nvlink_c2c_pmu_"
+ },
+ {
+ "MetricName": "nvlink_c2c_out_avg_rd_latency",
+ "MetricGroup": "NVLINK_C2C_Latency;NVLINK_C2C_Read_Latency;NVLINK_C2C_Outgoing",
+ "MetricConstraint": "NO_GROUP_EVENTS",
+ "MetricExpr": "(NVLINK_C2C_OUT_RD_CUM_OUTS / NVLINK_C2C_OUT_RD_REQ) / nvlink_c2c_freq",
+ "ScaleUnit": "1ns/request",
+ "BriefDescription": "Average latency of outgoing read requests at the NVLink-C2C interface.",
+ "PublicDescription": "Average latency of the outgoing read requests counted by NVLINK_C2C_OUT_RD_REQ, measured at the NVLink-C2C interface.",
+ "Unit": "nvidia_nvlink_c2c_pmu_"
+ },
+ {
+ "MetricName": "nvlink_c2c_out_avg_wr_latency",
+ "MetricGroup": "NVLINK_C2C_Latency;NVLINK_C2C_Write_Latency;NVLINK_C2C_Outgoing",
+ "MetricConstraint": "NO_GROUP_EVENTS",
+ "MetricExpr": "(NVLINK_C2C_OUT_WR_CUM_OUTS / NVLINK_C2C_OUT_WR_REQ) / nvlink_c2c_freq",
+ "ScaleUnit": "1ns/request",
+ "BriefDescription": "Average latency of outgoing write requests to connected GPUs at the NVLink-C2C interface.",
+ "PublicDescription": "Average latency of the outgoing write requests counted by NVLINK_C2C_OUT_WR_REQ, measured at the NVLink-C2C interface. Available only when GPUs are connected.",
+ "Unit": "nvidia_nvlink_c2c_pmu_"
+ }
+]
--
2.43.0
^ permalink raw reply [flat|nested] 12+ messages in thread* [PATCH v2 6/9] perf stat: Check merged PMU instance's cpumasks when skipping zero counts
2026-10-30 17:48 [PATCH v2 0/9] perf: Add NVIDIA Tegra410 uncore PMU events and metrics Besar Wicaksono
` (4 preceding siblings ...)
2026-10-30 17:48 ` [PATCH v2 5/9] perf jevents: Add support for NVIDIA Tegra410 C2C " Besar Wicaksono
@ 2026-10-30 17:48 ` Besar Wicaksono
2026-10-30 17:48 ` [PATCH v2 7/9] perf pmu: Merge PMU instances that match the same comma-separated json Unit Besar Wicaksono
` (3 subsequent siblings)
9 siblings, 0 replies; 12+ messages in thread
From: Besar Wicaksono @ 2026-10-30 17:48 UTC (permalink / raw)
To: acme, namhyung, irogers, ctshao
Cc: linux-tegra, linux-arm-kernel, linux-perf-users, linux-kernel,
vsethi, rwiley, skelley, mochs, rajjoshi, treding, jonathanh,
john.garry, will, james.clark, mike.leach, leo.yan, mark.rutland,
alexander.shishkin, jolsa, adrian.hunter, Besar Wicaksono
Commit dd15480a3d67 ("perf stat: Hide invalid uncore event output for
aggr mode") hides a 0 count of an uncore event in an aggregation id
that the event is not counted in, using the event's cpumask. When an
uncore event has more than one PMU instance, the evsels of the other
instances are merged into the evsel of the first one, and only the
cpumask of the first instance is checked. A 0 count in an aggregation
id covered only by another instance is then hidden, while a non-zero
count in the same id is printed.
For example, on a dual-socket NVIDIA Tegra410 with one UCF PMU per
socket (nvidia_ucf_pmu_0 on CPU 0, nvidia_ucf_pmu_1 on CPU 88):
Before:
$ perf stat -a --per-socket -e UCF_SLC_ACCESS_ATOMIC,UCF_SLC_ACCESS_RD -- sleep 1
S268435456 1 0 UCF_SLC_ACCESS_ATOMIC
S268435456 1 3,407,373 UCF_SLC_ACCESS_RD
S285212672 1 2,086,640 UCF_SLC_ACCESS_RD
After:
$ perf stat -a --per-socket -e UCF_SLC_ACCESS_ATOMIC,UCF_SLC_ACCESS_RD -- sleep 1
S268435456 1 0 UCF_SLC_ACCESS_ATOMIC
S268435456 1 2,669,279 UCF_SLC_ACCESS_RD
S285212672 1 0 UCF_SLC_ACCESS_ATOMIC
S285212672 1 1,006,579 UCF_SLC_ACCESS_RD
Also check the cpumasks of the evsels merged into the counter. Zero
counts are still hidden in aggregation ids that none of the instances
count in, such as the other cores in --per-core mode. Core PMUs and
--no-aggr output are unchanged.
Fixes: dd15480a3d67 ("perf stat: Hide invalid uncore event output for aggr mode")
Signed-off-by: Besar Wicaksono <bwicaksono@nvidia.com>
---
tools/perf/util/stat-display.c | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/tools/perf/util/stat-display.c b/tools/perf/util/stat-display.c
index b337cc23f413..493ed6c88685 100644
--- a/tools/perf/util/stat-display.c
+++ b/tools/perf/util/stat-display.c
@@ -894,6 +894,7 @@ static bool should_skip_zero_counter(struct perf_stat_config *config,
struct evsel *counter,
const struct aggr_cpu_id *id)
{
+ struct evsel *alias;
struct perf_cpu cpu;
unsigned int idx;
@@ -946,6 +947,25 @@ static bool should_skip_zero_counter(struct perf_stat_config *config,
if (aggr_cpu_id__equal(id, &own_id))
return false;
}
+
+ if (config->aggr_mode == AGGR_NONE || !counter->pmu || counter->pmu->is_core)
+ return true;
+
+ /*
+ * A merged uncore counter also counts on the CPUs of the other PMU
+ * instances merged into it, for example on another socket.
+ */
+ evlist__for_each_entry(counter->evlist, alias) {
+ if (alias->first_wildcard_match != counter)
+ continue;
+
+ perf_cpu_map__for_each_cpu(cpu, idx, alias->core.cpus) {
+ struct aggr_cpu_id own_id = config->aggr_get_id(config, cpu);
+
+ if (aggr_cpu_id__equal(id, &own_id))
+ return false;
+ }
+ }
return true;
}
--
2.43.0
^ permalink raw reply [flat|nested] 12+ messages in thread* [PATCH v2 7/9] perf pmu: Merge PMU instances that match the same comma-separated json Unit
2026-10-30 17:48 [PATCH v2 0/9] perf: Add NVIDIA Tegra410 uncore PMU events and metrics Besar Wicaksono
` (5 preceding siblings ...)
2026-10-30 17:48 ` [PATCH v2 6/9] perf stat: Check merged PMU instance's cpumasks when skipping zero counts Besar Wicaksono
@ 2026-10-30 17:48 ` Besar Wicaksono
2026-10-30 17:48 ` [PATCH v2 8/9] perf evsel: Name a merged uncore counter after all of its PMUs Besar Wicaksono
` (2 subsequent siblings)
9 siblings, 0 replies; 12+ messages in thread
From: Besar Wicaksono @ 2026-10-30 17:48 UTC (permalink / raw)
To: acme, namhyung, irogers, ctshao
Cc: linux-tegra, linux-arm-kernel, linux-perf-users, linux-kernel,
vsethi, rwiley, skelley, mochs, rajjoshi, treding, jonathanh,
john.garry, will, james.clark, mike.leach, leo.yan, mark.rutland,
alexander.shishkin, jolsa, adrian.hunter, Besar Wicaksono
Since commit 730670b1d108 ("perf pmu: Support more complex PMU event
aliasing") a json event "Unit" with comma-separated parts matches PMU
names with an optional number after each part. For example, the NVIDIA
Tegra410 PCIe PMUs are named nvidia_pcie_pmu_<socket>_rc_<rc>, and the
Unit "nvidia_pcie_pmu_,rc_" of their json events matches all of them.
perf uses this match to attach json events and metrics to these PMUs.
But perf uses a different match to decide which PMUs to combine in the
counting result, and it only ignores the number at the end of the name.
So the RCs of the same socket are combined, but the two sockets are not:
nvidia_pcie_pmu_0_rc_<rc> and nvidia_pcie_pmu_1_rc_<rc> give two
results.
On a dual-socket system, this gives one line per socket under the same
name in the default output, and with --metric-only a metric column per
socket, a "none" value for the other socket and a duplicate metric key:
$ perf stat -a --per-socket -j --metric-only -M pcie_avg_wr_bandwidth_to_all_dst -- sleep 1
{"socket" : "S268435456", "counters" : 6, "MB/s pcie_avg_wr_bandwidth_to_all_dst" : "0.0", "MB/s pcie_avg_wr_bandwidth_to_all_dst" : "none"}
{"socket" : "S285212672", "counters" : 0, "MB/s pcie_avg_wr_bandwidth_to_all_dst" : "none", "MB/s pcie_avg_wr_bandwidth_to_all_dst" : "0.0"}
Keep the existing match, which ignores the number at the end of the
name, and add a match for uncore PMUs with a comma-separated Unit: two
such PMUs are instances of one PMU if both match the Unit of the first
PMU's json events.
After:
$ perf stat -a --per-socket -j --metric-only -M pcie_avg_wr_bandwidth_to_all_dst -- sleep 1
{"socket" : "S268435456", "counters" : 6, "MB/s pcie_avg_wr_bandwidth_to_all_dst" : "0.0"}
{"socket" : "S285212672", "counters" : 6, "MB/s pcie_avg_wr_bandwidth_to_all_dst" : "0.0"}
Signed-off-by: Besar Wicaksono <bwicaksono@nvidia.com>
---
tools/perf/tests/pmu.c | 72 ++++++++++++++++++++++++++++++++++
tools/perf/util/parse-events.c | 2 +-
tools/perf/util/pmu.c | 65 ++++++++++++++++++++++++++++++
tools/perf/util/pmu.h | 9 +++++
4 files changed, 147 insertions(+), 1 deletion(-)
diff --git a/tools/perf/tests/pmu.c b/tools/perf/tests/pmu.c
index 13e8d7fa80af..e722cd08e30a 100644
--- a/tools/perf/tests/pmu.c
+++ b/tools/perf/tests/pmu.c
@@ -629,6 +629,77 @@ static int test__pmu_match(struct test_suite *test __maybe_unused, int subtest _
return TEST_OK;
}
+static int test__pmu_instance_match(struct test_suite *test __maybe_unused,
+ int subtest __maybe_unused)
+{
+/*
+ * Check that perf_pmu__is_instance_of() returns expect for uncore PMU _name,
+ * whose json events have the comma-separated Unit _unit (NULL if none), and
+ * uncore PMU _other.
+ */
+#define TEST_INSTANCE(msg, _name, _unit, _other, expect) \
+ TEST_ASSERT_EQUAL(msg, perf_pmu__is_instance_of( \
+ &(struct perf_pmu){ .name = _name, .is_uncore = true, \
+ .json_unit = _unit, \
+ .json_unit_checked = true }, \
+ &(struct perf_pmu){ .name = _other, .is_uncore = true, \
+ .json_unit_checked = true }), \
+ expect)
+
+ /* No comma-separated Unit: only the suffix number is ignored. */
+ TEST_INSTANCE("Same PMU type: same name",
+ "nvidia_ucf_pmu_0", NULL, "nvidia_ucf_pmu_0", true);
+ TEST_INSTANCE("Same PMU type: differ only in suffix number",
+ "nvidia_ucf_pmu_0", NULL, "nvidia_ucf_pmu_1", true);
+ TEST_INSTANCE("Same PMU type: differ only in suffix number, with a number inside the name",
+ "nvidia_nvlink_c2c_pmu_0", NULL, "nvidia_nvlink_c2c_pmu_1", true);
+ TEST_INSTANCE("Same PMU type: differ only in suffix number, with a number in the middle",
+ "uncore_type_0_1", NULL, "uncore_type_0_2", true);
+ TEST_INSTANCE("Same PMU type: differ only in hex suffix digits",
+ "smmuv3_pmcg_fe0004030", NULL, "smmuv3_pmcg_fe0004620", true);
+ TEST_INSTANCE("Same PMU type: differ only in hex suffix, with letters",
+ "smmuv3_pmcg_fe0004030", NULL, "smmuv3_pmcg_fe00053a0", true);
+ TEST_INSTANCE("Different PMU types: differ before suffix number",
+ "nvidia_ucf_pmu_0", NULL, "nvidia_nvlink_c2c_pmu_0", false);
+ TEST_INSTANCE("Different PMU types: differ in the middle number",
+ "uncore_type_0_1", NULL, "uncore_type_1_1", false);
+ TEST_INSTANCE("Different PMU types: differ before hex suffix",
+ "smmuv3_pmcg_fe0004030", NULL, "arm_dmc620_fe0004030", false);
+
+ /* Comma-separated Unit: an optional number after each part. */
+ TEST_INSTANCE("Same PMU type: both match comma Unit, numbers after _",
+ "nvidia_pcie_pmu_0_rc_0", "nvidia_pcie_pmu_,rc_",
+ "nvidia_pcie_pmu_1_rc_5", true);
+ TEST_INSTANCE("Same PMU type: both match comma Unit, numbers after _, reversed",
+ "nvidia_pcie_pmu_1_rc_5", "nvidia_pcie_pmu_,rc_",
+ "nvidia_pcie_pmu_0_rc_0", true);
+ TEST_INSTANCE("Same PMU type: both match comma Unit, numbers without _",
+ "hisi_sccl1_ddrc0", "hisi_sccl,ddrc", "hisi_sccl3_ddrc2", true);
+ TEST_INSTANCE("Same PMU type: comma Unit, part without number",
+ "hisi_sccl1_ddrc", "hisi_sccl,ddrc", "hisi_sccl3_ddrc", true);
+ TEST_INSTANCE("Same PMU type: comma Unit, one vs two numbers",
+ "hisi_sccl1_ddrc", "hisi_sccl,ddrc", "hisi_sccl3_ddrc2", true);
+
+ /* Comma-separated Unit that doesn't match the other PMU. */
+ TEST_INSTANCE("Different PMU types: comma Unit of other type",
+ "nvidia_pcie_pmu_0_rc_0", "nvidia_pcie_pmu_,rc_",
+ "nvidia_pcie_tgt_pmu_1_rc_0", false);
+ TEST_INSTANCE("Different PMU types: comma Unit of other type, reversed",
+ "nvidia_pcie_tgt_pmu_1_rc_0", "nvidia_pcie_tgt_pmu_,rc_",
+ "nvidia_pcie_pmu_1_rc_5", false);
+ TEST_INSTANCE("Different PMU types: comma Unit part rc_ missing",
+ "nvidia_pcie_pmu_0_rc_0", "nvidia_pcie_pmu_,rc_",
+ "nvidia_pcie_pmu_0", false);
+ TEST_INSTANCE("Different PMU types: comma Unit part rc_ missing, reversed",
+ "nvidia_pcie_pmu_0", NULL, "nvidia_pcie_pmu_0_rc_0", false);
+ TEST_INSTANCE("Different PMU types: comma Unit vs suffix-only name",
+ "nvidia_pcie_pmu_0_rc_0", "nvidia_pcie_pmu_,rc_",
+ "nvidia_ucf_pmu_0", false);
+
+#undef TEST_INSTANCE
+ return TEST_OK;
+}
+
static struct test_case tests__pmu[] = {
TEST_CASE("Parsing with PMU format directory", pmu_format),
TEST_CASE("Parsing with PMU event", pmu_events),
@@ -636,6 +707,7 @@ static struct test_case tests__pmu[] = {
TEST_CASE("PMU name combining", name_len),
TEST_CASE("PMU name comparison", name_cmp),
TEST_CASE("PMU cmdline match", pmu_match),
+ TEST_CASE("PMU instance match", pmu_instance_match),
TEST_CASE("PMU config helpers", pmu_config_helpers),
{ .name = NULL, }
};
diff --git a/tools/perf/util/parse-events.c b/tools/perf/util/parse-events.c
index f3ba70d4f76b..9455a7679468 100644
--- a/tools/perf/util/parse-events.c
+++ b/tools/perf/util/parse-events.c
@@ -193,7 +193,7 @@ __add_event(struct list_head *list, int *idx,
first_wildcard_match = NULL;
list_for_each_entry_continue(pos, list, core.node) {
- if (perf_pmu__name_no_suffix_match(pos->pmu, pmu->name)) {
+ if (perf_pmu__is_instance_of(pos->pmu, pmu)) {
first_wildcard_match = pos;
break;
}
diff --git a/tools/perf/util/pmu.c b/tools/perf/util/pmu.c
index 01753d5c69d1..df2abdf23697 100644
--- a/tools/perf/util/pmu.c
+++ b/tools/perf/util/pmu.c
@@ -1120,6 +1120,13 @@ static int pmu_add_sys_aliases_iter_fn(const struct pmu_event *pe,
/*val_fd=*/ -1,
pe,
EVENT_SRC_SYS_JSON);
+
+ /*
+ * Sys json events are not in pmu->events_table, so store their
+ * comma-separated Unit here for perf_pmu__json_unit().
+ */
+ if (!pmu->json_unit && strchr(pe->pmu, ','))
+ pmu->json_unit = pe->pmu;
}
return 0;
}
@@ -2435,6 +2442,64 @@ bool perf_pmu__name_no_suffix_match(const struct perf_pmu *pmu, const char *to_m
return perf_pmu___name_match(pmu, to_match, /*wildcard=*/false);
}
+/* Look for a json Unit with comma-separated parts among the PMU's events. */
+static int pmu_json_unit_callback(const struct pmu_event *pe,
+ const struct pmu_events_table *table __maybe_unused,
+ void *vdata)
+{
+ const char **unit = vdata;
+
+ if (!pe->pmu || !strchr(pe->pmu, ','))
+ return 0;
+
+ *unit = pe->pmu;
+ return 1;
+}
+
+/*
+ * The json Unit with comma-separated parts matching the PMU, if any. Such a
+ * Unit, like "nvidia_pcie_pmu_,rc_", matches PMU names with an optional
+ * number after each part, like "nvidia_pcie_pmu_1_rc_3".
+ */
+static const char *perf_pmu__json_unit(struct perf_pmu *pmu)
+{
+ if (!pmu->json_unit_checked) {
+ pmu->json_unit_checked = true;
+ /* Not found in the sys json events: look in the CPU json events. */
+ if (!pmu->json_unit)
+ pmu_events_table__for_each_event(pmu->events_table, pmu,
+ pmu_json_unit_callback,
+ &pmu->json_unit);
+ }
+ return pmu->json_unit;
+}
+
+/**
+ * perf_pmu__is_instance_of - Check whether pmu and other are instances of
+ * the same PMU: either their names match
+ * ignoring any suffix, or both are uncore PMUs
+ * matching the json Unit of pmu with
+ * comma-separated parts.
+ * @pmu: The PMU whose name and json Unit to match.
+ * @other: The possible other instance.
+ *
+ * Only the json Unit of pmu is used. Instances of one PMU have the same
+ * json events, so the result doesn't depend on the order of the PMUs.
+ */
+bool perf_pmu__is_instance_of(struct perf_pmu *pmu, struct perf_pmu *other)
+{
+ const char *unit;
+
+ if (perf_pmu__name_no_suffix_match(pmu, other->name))
+ return true;
+
+ if (!pmu->is_uncore || !other->is_uncore)
+ return false;
+
+ unit = perf_pmu__json_unit(pmu);
+ return unit && perf_pmu__name_wildcard_match(other, unit);
+}
+
bool perf_pmu__is_software(const struct perf_pmu *pmu)
{
const char *known_sw_pmus[] = {
diff --git a/tools/perf/util/pmu.h b/tools/perf/util/pmu.h
index 2c8916ad073e..5263d97b8f20 100644
--- a/tools/perf/util/pmu.h
+++ b/tools/perf/util/pmu.h
@@ -148,6 +148,12 @@ struct perf_pmu {
* @events_table: The events table for json events in pmu-events.c.
*/
const struct pmu_events_table *events_table;
+ /**
+ * @json_unit: The json Unit with comma-separated parts of the events
+ * matching the PMU, NULL if none. Units without a comma are not
+ * stored. Found by perf_pmu__is_instance_of().
+ */
+ const char *json_unit;
/** @sysfs_aliases: Number of sysfs aliases loaded. */
uint32_t sysfs_aliases;
/** @cpu_json_aliases: Number of json event aliases loaded specific to the CPUID. */
@@ -166,6 +172,8 @@ struct perf_pmu {
* been added?
*/
bool cpu_aliases_added;
+ /** @json_unit_checked: Has json_unit been looked up? */
+ bool json_unit_checked;
/** @caps_initialized: Has the list caps been initialized? */
bool caps_initialized;
/** @nr_caps: The length of the list caps. */
@@ -300,6 +308,7 @@ int perf_pmu__for_each_event(struct perf_pmu *pmu, bool skip_duplicate_pmus,
void *state, pmu_event_callback cb);
bool perf_pmu__name_wildcard_match(const struct perf_pmu *pmu, const char *to_match);
bool perf_pmu__name_no_suffix_match(const struct perf_pmu *pmu, const char *to_match);
+bool perf_pmu__is_instance_of(struct perf_pmu *pmu, struct perf_pmu *other);
/**
* perf_pmu_is_software - is the PMU a software PMU as in it uses the
--
2.43.0
^ permalink raw reply [flat|nested] 12+ messages in thread* [PATCH v2 8/9] perf evsel: Name a merged uncore counter after all of its PMUs
2026-10-30 17:48 [PATCH v2 0/9] perf: Add NVIDIA Tegra410 uncore PMU events and metrics Besar Wicaksono
` (6 preceding siblings ...)
2026-10-30 17:48 ` [PATCH v2 7/9] perf pmu: Merge PMU instances that match the same comma-separated json Unit Besar Wicaksono
@ 2026-10-30 17:48 ` Besar Wicaksono
2026-10-30 17:48 ` [PATCH v2 9/9] perf Documentation: Describe PMU names numbered in more than one place Besar Wicaksono
2026-10-30 18:07 ` [PATCH v2 0/9] perf: Add NVIDIA Tegra410 uncore PMU events and metrics Ian Rogers
9 siblings, 0 replies; 12+ messages in thread
From: Besar Wicaksono @ 2026-10-30 17:48 UTC (permalink / raw)
To: acme, namhyung, irogers, ctshao
Cc: linux-tegra, linux-arm-kernel, linux-perf-users, linux-kernel,
vsethi, rwiley, skelley, mochs, rajjoshi, treding, jonathanh,
john.garry, will, james.clark, mike.leach, leo.yan, mark.rutland,
alexander.shishkin, jolsa, adrian.hunter, Besar Wicaksono
When an uncore event is opened on several instances of a PMU, perf stat
merges the counts of the other instances into the evsel of the first
one. If the event name has to be made unique, for example because the
event matches more than one PMU type, the name of the first instance is
put in front of it, although the count is the sum of all instances.
For example, on a dual-socket NVIDIA Tegra410 with six PCIe root
complexes per socket, the socket 1 rows count nvidia_pcie_pmu_1_rc_<rc>
but are labelled with nvidia_pcie_pmu_0_rc_0:
Before:
$ perf stat -a --per-socket -e 'nvidia_pcie_*rc*/rd_req/' -- sleep 1
S268435456 6 235,037 nvidia_pcie_pmu_0_rc_0/nvidia_pcie_*rc*,rd_req/
S268435456 6 665,297 nvidia_pcie_tgt_pmu_0_rc_0/nvidia_pcie_*rc*,rd_req/
S285212672 6 3,967 nvidia_pcie_pmu_0_rc_0/nvidia_pcie_*rc*,rd_req/
S285212672 6 45 nvidia_pcie_tgt_pmu_0_rc_0/nvidia_pcie_*rc*,rd_req/
Name a merged uncore counter after all of its PMUs instead. If the PMU
names differ only in the suffix, use the name without the suffix, like
nvidia_ucf_pmu. Otherwise, replace each number that differs with '*',
like nvidia_pcie_pmu_*_rc_*.
After:
$ perf stat -a --per-socket -e 'nvidia_pcie_*rc*/rd_req/' -- sleep 1
S268435456 6 234,973 nvidia_pcie_pmu_*_rc_*/nvidia_pcie_*rc*,rd_req/
S268435456 6 666,448 nvidia_pcie_tgt_pmu_*_rc_*/nvidia_pcie_*rc*,rd_req/
S285212672 6 3,184 nvidia_pcie_pmu_*_rc_*/nvidia_pcie_*rc*,rd_req/
S285212672 6 31 nvidia_pcie_tgt_pmu_*_rc_*/nvidia_pcie_*rc*,rd_req/
Output with --no-aggr, where the counters are not merged, is unchanged.
Signed-off-by: Besar Wicaksono <bwicaksono@nvidia.com>
---
tools/perf/tests/pmu.c | 62 ++++++++++++++++++++++++++++++
tools/perf/util/evlist.c | 2 +-
tools/perf/util/evsel.c | 83 ++++++++++++++++++++++++++++++++++++++--
tools/perf/util/evsel.h | 2 +-
tools/perf/util/pmus.c | 47 +++++++++++++++++++++++
tools/perf/util/pmus.h | 1 +
6 files changed, 192 insertions(+), 5 deletions(-)
diff --git a/tools/perf/tests/pmu.c b/tools/perf/tests/pmu.c
index e722cd08e30a..e31fdc25aa4c 100644
--- a/tools/perf/tests/pmu.c
+++ b/tools/perf/tests/pmu.c
@@ -547,6 +547,67 @@ static int test__name_cmp(struct test_suite *test __maybe_unused, int subtest __
return TEST_OK;
}
+static int test__name_mask_numbers(struct test_suite *test __maybe_unused,
+ int subtest __maybe_unused)
+{
+/*
+ * Check that pmu_name_mask_numbers() turns _pattern into expect after
+ * matching _name, or fails if expect is NULL.
+ */
+#define TEST_MASK(msg, _pattern, _name, _expect) \
+ do { \
+ const char *expect = _expect; \
+ char buf[64]; \
+ bool ok; \
+ \
+ snprintf(buf, sizeof(buf), "%s", _pattern); \
+ ok = pmu_name_mask_numbers(buf, _name); \
+ TEST_ASSERT_VAL(msg, expect ? ok && !strcmp(buf, expect) : !ok); \
+ } while (0)
+
+ TEST_MASK("Same name", "nvidia_ucf_pmu_0", "nvidia_ucf_pmu_0",
+ "nvidia_ucf_pmu_0");
+ TEST_MASK("Differ in suffix number", "nvidia_ucf_pmu_0", "nvidia_ucf_pmu_1",
+ "nvidia_ucf_pmu_*");
+ TEST_MASK("Differ in suffix number, with a number inside the name",
+ "nvidia_nvlink_c2c_pmu_0", "nvidia_nvlink_c2c_pmu_1",
+ "nvidia_nvlink_c2c_pmu_*");
+ TEST_MASK("Differ in both numbers", "nvidia_pcie_pmu_0_rc_0",
+ "nvidia_pcie_pmu_1_rc_5", "nvidia_pcie_pmu_*_rc_*");
+ TEST_MASK("Differ in last number only", "nvidia_pcie_pmu_0_rc_0",
+ "nvidia_pcie_pmu_0_rc_5", "nvidia_pcie_pmu_0_rc_*");
+ TEST_MASK("Differ in first number only", "nvidia_pcie_pmu_0_rc_0",
+ "nvidia_pcie_pmu_1_rc_0", "nvidia_pcie_pmu_*_rc_0");
+ TEST_MASK("Same number length, different number", "nvidia_pcie_pmu_0_rc_10",
+ "nvidia_pcie_pmu_0_rc_12", "nvidia_pcie_pmu_0_rc_*");
+ TEST_MASK("Longer last number in name", "nvidia_pcie_pmu_0_rc_0",
+ "nvidia_pcie_pmu_0_rc_12", "nvidia_pcie_pmu_0_rc_*");
+ TEST_MASK("Longer first number in name", "nvidia_pcie_pmu_0_rc_0",
+ "nvidia_pcie_pmu_10_rc_0", "nvidia_pcie_pmu_*_rc_0");
+ TEST_MASK("Longer first number in pattern", "nvidia_pcie_pmu_10_rc_0",
+ "nvidia_pcie_pmu_0_rc_0", "nvidia_pcie_pmu_*_rc_0");
+ TEST_MASK("Same longer number after a masked one", "nvidia_pcie_pmu_10_rc_12",
+ "nvidia_pcie_pmu_0_rc_12", "nvidia_pcie_pmu_*_rc_12");
+ TEST_MASK("Number is a prefix of the other", "nvidia_pcie_pmu_0_rc_1",
+ "nvidia_pcie_pmu_0_rc_10", "nvidia_pcie_pmu_0_rc_*");
+ TEST_MASK("'*' matches any number", "nvidia_pcie_pmu_*_rc_*",
+ "nvidia_pcie_pmu_1_rc_10", "nvidia_pcie_pmu_*_rc_*");
+ TEST_MASK("Numbers without _", "hisi_sccl1_ddrc0", "hisi_sccl3_ddrc0",
+ "hisi_sccl*_ddrc0");
+ TEST_MASK("Hex suffix, differ in digits", "smmuv3_pmcg_fe0004030",
+ "smmuv3_pmcg_fe0004620", "smmuv3_pmcg_fe*");
+ TEST_MASK("Hex suffix, differ in a letter", "smmuv3_pmcg_fe0004030",
+ "smmuv3_pmcg_fe00053a0", NULL);
+ TEST_MASK("Differ before the numbers", "nvidia_pcie_pmu_0_rc_0",
+ "nvidia_pcie_tgt_pmu_0_rc_0", NULL);
+ TEST_MASK("Name ends early", "nvidia_pcie_pmu_0_rc_0", "nvidia_pcie_pmu_0",
+ NULL);
+ TEST_MASK("Name is longer", "nvidia_pcie_pmu_0", "nvidia_pcie_pmu_0_rc_0",
+ NULL);
+#undef TEST_MASK
+ return TEST_OK;
+}
+
/**
* Test perf_pmu__wildcard_match() that's used to search for a PMU given a name passed
* on the command line. The name that's passed may also be a filename type glob
@@ -706,6 +767,7 @@ static struct test_case tests__pmu[] = {
TEST_CASE("PMU event names", pmu_event_names),
TEST_CASE("PMU name combining", name_len),
TEST_CASE("PMU name comparison", name_cmp),
+ TEST_CASE("PMU name number masking", name_mask_numbers),
TEST_CASE("PMU cmdline match", pmu_match),
TEST_CASE("PMU instance match", pmu_instance_match),
TEST_CASE("PMU config helpers", pmu_config_helpers),
diff --git a/tools/perf/util/evlist.c b/tools/perf/util/evlist.c
index c2402e4791b6..6ece8fb78a2f 100644
--- a/tools/perf/util/evlist.c
+++ b/tools/perf/util/evlist.c
@@ -2977,7 +2977,7 @@ void evlist__uniquify_evsel_names(struct evlist *evlist, const struct perf_stat_
struct evsel *pos;
evlist__for_each_entry(evlist, pos)
- evsel__uniquify_counter(pos);
+ evsel__uniquify_counter(pos, config->aggr_mode != AGGR_NONE);
}
}
diff --git a/tools/perf/util/evsel.c b/tools/perf/util/evsel.c
index d060fca8090f..7256a315e7df 100644
--- a/tools/perf/util/evsel.c
+++ b/tools/perf/util/evsel.c
@@ -4911,10 +4911,84 @@ bool evsel__set_needs_uniquify(struct evsel *counter, const struct perf_stat_con
return false;
}
-void evsel__uniquify_counter(struct evsel *counter)
+/*
+ * Check whether the PMUs merged into an uncore counter differ from its PMU
+ * only in the suffix, like nvidia_ucf_pmu_0 and nvidia_ucf_pmu_1. Set merged
+ * if any PMU is merged.
+ */
+static bool evsel__merged_pmus_suffix_only(struct evsel *counter, bool *merged)
+{
+ struct evsel *alias;
+
+ *merged = false;
+ evlist__for_each_entry(counter->evlist, alias) {
+ if (alias->first_wildcard_match != counter)
+ continue;
+
+ *merged = true;
+ if (!perf_pmu__name_no_suffix_match(alias->pmu, counter->pmu->name))
+ return false;
+ }
+
+ return true;
+}
+
+/*
+ * The PMU name of an uncore counter with each number that differs in the
+ * PMUs merged into it replaced by '*', like nvidia_pcie_pmu_*_rc_*, or NULL
+ * if the names differ in anything but numbers.
+ */
+static char *evsel__merged_pmus_mask_numbers(struct evsel *counter)
+{
+ struct evsel *alias;
+ char *name;
+
+ name = strdup(counter->pmu->name);
+ if (!name)
+ return NULL;
+
+ evlist__for_each_entry(counter->evlist, alias) {
+ if (alias->first_wildcard_match != counter)
+ continue;
+
+ if (!pmu_name_mask_numbers(name, alias->pmu->name)) {
+ free(name);
+ return NULL;
+ }
+ }
+
+ return name;
+}
+
+/*
+ * The name of the PMUs whose counts are merged into an uncore counter, or
+ * NULL if none are. It is the PMU name without the suffix if the PMUs
+ * differ only in the suffix, like nvidia_ucf_pmu, otherwise the PMU name
+ * with each number that differs replaced by '*', like
+ * nvidia_pcie_pmu_*_rc_*.
+ */
+static char *evsel__merged_pmu_name(struct evsel *counter)
+{
+ const char *pmu_name = counter->pmu->name;
+ bool merged;
+
+ if (counter->pmu->is_core)
+ return NULL;
+
+ if (evsel__merged_pmus_suffix_only(counter, &merged)) {
+ if (!merged)
+ return NULL;
+
+ return strndup(pmu_name, pmu_name_len_no_suffix(pmu_name));
+ }
+
+ return evsel__merged_pmus_mask_numbers(counter);
+}
+
+void evsel__uniquify_counter(struct evsel *counter, bool merged)
{
const char *name, *pmu_name, *config;
- char *new_name;
+ char *new_name, *merged_pmu_name;
int len, ret;
/* No uniquification necessary. */
@@ -4930,7 +5004,8 @@ void evsel__uniquify_counter(struct evsel *counter)
name = evsel__name(counter);
config = strchr(name, '/');
- pmu_name = counter->pmu->name;
+ merged_pmu_name = merged ? evsel__merged_pmu_name(counter) : NULL;
+ pmu_name = merged_pmu_name ?: counter->pmu->name;
/* Already prefixed by the PMU name? */
len = pmu_name_len_no_suffix(pmu_name);
@@ -4965,6 +5040,8 @@ void evsel__uniquify_counter(struct evsel *counter)
ret = asprintf(&new_name, "%s/%s/", pmu_name, name);
}
}
+ free(merged_pmu_name);
+
if (ret > 0) {
free(counter->name);
counter->name = new_name;
diff --git a/tools/perf/util/evsel.h b/tools/perf/util/evsel.h
index 53f3641b66e1..0c46b95ab777 100644
--- a/tools/perf/util/evsel.h
+++ b/tools/perf/util/evsel.h
@@ -615,7 +615,7 @@ void evsel__remove_from_group(struct evsel *evsel, struct evsel *leader);
bool arch_evsel__must_be_in_group(const struct evsel *evsel);
bool evsel__set_needs_uniquify(struct evsel *counter, const struct perf_stat_config *config);
-void evsel__uniquify_counter(struct evsel *counter);
+void evsel__uniquify_counter(struct evsel *counter, bool merged);
/*
* Macro to swap the bit-field postition and size.
diff --git a/tools/perf/util/pmus.c b/tools/perf/util/pmus.c
index 1355b317f3ed..f80ba16a5007 100644
--- a/tools/perf/util/pmus.c
+++ b/tools/perf/util/pmus.c
@@ -90,6 +90,53 @@ size_t pmu_name_len_no_suffix(const char *str)
return orig_len;
}
+/*
+ * Replace each number in pattern that differs from the number in the same
+ * place in name with '*'. A '*' already in pattern matches any number.
+ * Return false, with pattern partly changed, if the names differ in
+ * anything but numbers.
+ */
+bool pmu_name_mask_numbers(char *pattern, const char *name)
+{
+ const char *p = pattern;
+ /* Masking never lengthens pattern, so write the result in place. */
+ char *out = pattern;
+
+ while (*p || *name) {
+ size_t p_len, name_len;
+
+ /* Unless both names have a number here, the characters must match. */
+ if (!(isdigit(*p) || *p == '*') || !isdigit(*name)) {
+ if (*p != *name)
+ return false;
+
+ *out++ = *p++;
+ name++;
+ continue;
+ }
+
+ /*
+ * Both names have a number here. A '*' in pattern is a number
+ * that differed in an earlier name, so it stays '*'.
+ */
+ p_len = *p == '*' ? 1 : strspn(p, "0123456789");
+ name_len = strspn(name, "0123456789");
+
+ /* Keep the number if it is the same in both names, else mask it. */
+ if (*p != '*' && p_len == name_len && !strncmp(p, name, p_len)) {
+ for (size_t i = 0; i < p_len; i++)
+ *out++ = *p++;
+ } else {
+ *out++ = '*';
+ p += p_len;
+ }
+ name += name_len;
+ }
+
+ *out = '\0';
+ return true;
+}
+
int pmu_name_cmp(const char *lhs_pmu_name, const char *rhs_pmu_name)
{
unsigned long long lhs_num = 0, rhs_num = 0;
diff --git a/tools/perf/util/pmus.h b/tools/perf/util/pmus.h
index 0d55edb3f2fc..535b79b1c750 100644
--- a/tools/perf/util/pmus.h
+++ b/tools/perf/util/pmus.h
@@ -10,6 +10,7 @@ struct perf_pmu;
struct print_callbacks;
size_t pmu_name_len_no_suffix(const char *str);
+bool pmu_name_mask_numbers(char *pattern, const char *name);
/* Exposed for testing only. */
int pmu_name_cmp(const char *lhs_pmu_name, const char *rhs_pmu_name);
--
2.43.0
^ permalink raw reply [flat|nested] 12+ messages in thread* [PATCH v2 9/9] perf Documentation: Describe PMU names numbered in more than one place
2026-10-30 17:48 [PATCH v2 0/9] perf: Add NVIDIA Tegra410 uncore PMU events and metrics Besar Wicaksono
` (7 preceding siblings ...)
2026-10-30 17:48 ` [PATCH v2 8/9] perf evsel: Name a merged uncore counter after all of its PMUs Besar Wicaksono
@ 2026-10-30 17:48 ` Besar Wicaksono
2026-10-30 18:07 ` [PATCH v2 0/9] perf: Add NVIDIA Tegra410 uncore PMU events and metrics Ian Rogers
9 siblings, 0 replies; 12+ messages in thread
From: Besar Wicaksono @ 2026-10-30 17:48 UTC (permalink / raw)
To: acme, namhyung, irogers, ctshao
Cc: linux-tegra, linux-arm-kernel, linux-perf-users, linux-kernel,
vsethi, rwiley, skelley, mochs, rajjoshi, treding, jonathanh,
john.garry, will, james.clark, mike.leach, leo.yan, mark.rutland,
alexander.shishkin, jolsa, adrian.hunter, Besar Wicaksono
The PMU naming convention describes an optional numeric suffix that tools
ignore to treat PMUs as instances of one PMU. Some PMU names contain more
than one number to identify an instance, such as the NVIDIA PCIe PMU
nvidia_pcie_pmu_<socket>_rc_<rc>. Since commit 730670b1d108 ("perf pmu:
Support more complex PMU event aliasing"), the perf tool matches such
names with json event Units with comma-separated parts, like
"nvidia_pcie_pmu_,rc_".
Describe these names and how tools can tell that all their numbers
identify an instance of the same PMU.
Signed-off-by: Besar Wicaksono <bwicaksono@nvidia.com>
---
.../ABI/testing/sysfs-bus-event_source-devices | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/Documentation/ABI/testing/sysfs-bus-event_source-devices b/Documentation/ABI/testing/sysfs-bus-event_source-devices
index 79b268319df1..7610aa46cd50 100644
--- a/Documentation/ABI/testing/sysfs-bus-event_source-devices
+++ b/Documentation/ABI/testing/sysfs-bus-event_source-devices
@@ -22,3 +22,17 @@ Description: Performance Monitoring Unit (<pmu>)
uncore_imc_free_running should be treated as opening
the data_read event on PMU uncore_imc_free_running_0
and PMU uncore_imc_free_running_1.
+
+ Some PMU names contain more than one number to
+ identify an instance. For example, the NVIDIA PCIe PMU
+ of root complex <rc> on socket <socket> is named
+ nvidia_pcie_pmu_<socket>_rc_<rc>. The name alone does
+ not show that both numbers identify an instance of the
+ same PMU; in other names, an earlier number can select
+ a different PMU. Tools can treat such PMUs as
+ instances of the same PMU when they have a description
+ of the name parts, like the perf tool's json event
+ "Unit" with comma-separated parts,
+ "nvidia_pcie_pmu_,rc_", which matches PMU names with
+ an optional number after each part, like
+ nvidia_pcie_pmu_1_rc_3.
--
2.43.0
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH v2 0/9] perf: Add NVIDIA Tegra410 uncore PMU events and metrics
2026-10-30 17:48 [PATCH v2 0/9] perf: Add NVIDIA Tegra410 uncore PMU events and metrics Besar Wicaksono
` (8 preceding siblings ...)
2026-10-30 17:48 ` [PATCH v2 9/9] perf Documentation: Describe PMU names numbered in more than one place Besar Wicaksono
@ 2026-10-30 18:07 ` Ian Rogers
2026-10-30 22:18 ` Besar Wicaksono
9 siblings, 1 reply; 12+ messages in thread
From: Ian Rogers @ 2026-10-30 18:07 UTC (permalink / raw)
To: Besar Wicaksono
Cc: acme, namhyung, ctshao, linux-tegra, linux-arm-kernel,
linux-perf-users, linux-kernel, vsethi, rwiley, skelley, mochs,
rajjoshi, treding, jonathanh, john.garry, will, james.clark,
mike.leach, leo.yan, mark.rutland, alexander.shishkin, jolsa,
adrian.hunter
On Fri, Oct 30, 2026 at 10:49 AM Besar Wicaksono <bwicaksono@nvidia.com> wrote:
>
> Add event aliases and derived metrics for the NVIDIA Tegra410 uncore
> PMUs, and fix perf's aggregation of PMU instances that are numbered in
> more than one parts in their name.
>
> The series covers the UCF, PCIe, PCIe target, CPU memory latency, and
> chip-to-chip interconnect PMUs. It provides symbolic names for the raw
> event encodings and metrics for bandwidth, frequency, and average read
> latency.
>
> The PCIe and PCIe target PMUs are named nvidia_pcie_pmu_<socket>_rc_<rc>
> and nvidia_pcie_tgt_pmu_<socket>_rc_<rc>. Their json Unit uses the
> existing comma-separated form ("nvidia_pcie_pmu_,rc_"), but perf only
> merged instances that differ in the trailing number, so these events and
> metrics gave one result per socket and were reported incorrectly (e.g.
> with --metric-only), as discussed in v1. Patches 6-9 fix this:
>
> - Patch 6 adds a check of the cpumasks of all merged PMU instances to the
> zero-count skip in perf stat, so a socket that counts nothing shows 0
> instead of having its row hidden.
> - Patch 7 merges PMU instances that match the same comma-separated json
> Unit. This also applies to the HiSilicon hisi_sccl PMUs, which use the
> same json form; not tested on HiSilicon hardware.
> - Patch 8 labels a merged uncore counter after all of its PMUs, e.g.
> nvidia_pcie_pmu_*_rc_*/cycles/ or nvidia_ucf_pmu/cycles/, instead of
> after the first instance, such as nvidia_pcie_pmu_0_rc_0/cycles/.
> Output with --no-aggr is unchanged.
> - Patch 9 describes these PMU names in the ABI document.
>
> Changes in v2:
> - Move the uncore JSON out of the sys directory and remove the
> "Compat" fields. Thanks to Ian Rogers for the feedback.
> - Drop "perf jevents: Process model files before sys subdirectories",
> which this series no longer needs.
> - Add UCF SLC and memory bandwidth metrics from all sources to local
> CMEM (read, write and read+write) and from local sources to local
> CMEM and to remote memory, PCIe bandwidth metrics to local
> destinations, and read+write bandwidth metrics for UCF SLC, UCF
> memory and PCIe. Thanks to Chun-Tse Shao for the suggestion.
> - Add patches 6-9 to fix the PCIe instance aggregation. Thanks to Ian
> Rogers and Chun-Tse Shao for the pointers.
>
> v1: https://lore.kernel.org/all/20261019164241.403644-1-bwicaksono@nvidia.com/
Why don't we look to fix code in drivers/perf? This series introduces
PMU instances, overloads the meaning of aliases, and a bunch of other
silly complexity due to poor reviews and maintenance of drivers/perf -
specifically by not pointing out the ABI issues. Isn't this a
straightforward, whoops we did a bad suffix and here's the patch to
rename our PMU in the driver? Throwing more complexity at the problem
doesn't feel like the right fix.
Thanks,
Ian
> Besar Wicaksono (9):
> perf jevents: Add support for NVIDIA Tegra410 UCF PMU aliasing
> perf jevents: Add support for NVIDIA Tegra410 PCIE PMU aliasing
> perf jevents: Add support for NVIDIA Tegra410 PCIE-TGT PMU aliasing
> perf jevents: Add support for NVIDIA Tegra410 CPU Memory Latency PMU
> aliasing
> perf jevents: Add support for NVIDIA Tegra410 C2C PMU aliasing
> perf stat: Check merged PMU instance's cpumasks when skipping zero
> counts
> perf pmu: Merge PMU instances that match the same comma-separated json
> Unit
> perf evsel: Name a merged uncore counter after all of its PMUs
> perf Documentation: Describe PMU names numbered in more than one place
>
> .../testing/sysfs-bus-event_source-devices | 14 +
> .../arm64/nvidia/t410/uncore-cpu_mem.json | 43 +
> .../arm64/nvidia/t410/uncore-nvclink.json | 67 ++
> .../arm64/nvidia/t410/uncore-nvdlink.json | 43 +
> .../arm64/nvidia/t410/uncore-nvlink_c2c.json | 115 +++
> .../arch/arm64/nvidia/t410/uncore-pcie.json | 249 ++++++
> .../arm64/nvidia/t410/uncore-pcie_tgt.json | 83 ++
> .../arch/arm64/nvidia/t410/uncore-ucf.json | 764 ++++++++++++++++++
> tools/perf/tests/pmu.c | 134 +++
> tools/perf/util/evlist.c | 2 +-
> tools/perf/util/evsel.c | 83 +-
> tools/perf/util/evsel.h | 2 +-
> tools/perf/util/parse-events.c | 2 +-
> tools/perf/util/pmu.c | 65 ++
> tools/perf/util/pmu.h | 9 +
> tools/perf/util/pmus.c | 47 ++
> tools/perf/util/pmus.h | 1 +
> tools/perf/util/stat-display.c | 20 +
> 18 files changed, 1737 insertions(+), 6 deletions(-)
> create mode 100644 tools/perf/pmu-events/arch/arm64/nvidia/t410/uncore-cpu_mem.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/nvidia/t410/uncore-nvclink.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/nvidia/t410/uncore-nvdlink.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/nvidia/t410/uncore-nvlink_c2c.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/nvidia/t410/uncore-pcie.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/nvidia/t410/uncore-pcie_tgt.json
> create mode 100644 tools/perf/pmu-events/arch/arm64/nvidia/t410/uncore-ucf.json
>
> --
> 2.43.0
>
^ permalink raw reply [flat|nested] 12+ messages in thread* RE: [PATCH v2 0/9] perf: Add NVIDIA Tegra410 uncore PMU events and metrics
2026-10-30 18:07 ` [PATCH v2 0/9] perf: Add NVIDIA Tegra410 uncore PMU events and metrics Ian Rogers
@ 2026-10-30 22:18 ` Besar Wicaksono
0 siblings, 0 replies; 12+ messages in thread
From: Besar Wicaksono @ 2026-10-30 22:18 UTC (permalink / raw)
To: Ian Rogers, Will Deacon
Cc: acme, namhyung, ctshao, linux-tegra, linux-arm-kernel,
linux-perf-users, linux-kernel, Vikram Sethi, Rich Wiley,
Sean Kelley, Matt Ochs, Raj Joshi, Thierry Reding, Jon Hunter,
john.garry, will, james.clark, mike.leach, leo.yan, mark.rutland,
alexander.shishkin, jolsa, adrian.hunter
> -----Original Message-----
> From: Ian Rogers <irogers@google.com>
> Sent: Friday, October 30, 2026 6:07 PM
> To: Besar Wicaksono <bwicaksono@nvidia.com>
> Cc: acme@kernel.org; namhyung@kernel.org; ctshao@google.com; linux-
> tegra@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux-perf-
> users@vger.kernel.org; linux-kernel@vger.kernel.org; Vikram Sethi
> <vsethi@nvidia.com>; Rich Wiley <rwiley@nvidia.com>; Sean Kelley
> <skelley@nvidia.com>; Matt Ochs <mochs@nvidia.com>; Raj Joshi
> <rajjoshi@nvidia.com>; Thierry Reding <treding@nvidia.com>; Jon Hunter
> <jonathanh@nvidia.com>; john.garry@linux.dev; will@kernel.org;
> james.clark@linaro.org; mike.leach@arm.com; leo.yan@linux.dev;
> mark.rutland@arm.com; alexander.shishkin@linux.intel.com;
> jolsa@kernel.org; adrian.hunter@intel.com
> Subject: Re: [PATCH v2 0/9] perf: Add NVIDIA Tegra410 uncore PMU events
> and metrics
>
> External email: Use caution opening links or attachments
>
>
> On Fri, Oct 30, 2026 at 10:49 AM Besar Wicaksono
> <bwicaksono@nvidia.com> wrote:
> >
> > Add event aliases and derived metrics for the NVIDIA Tegra410 uncore
> > PMUs, and fix perf's aggregation of PMU instances that are numbered in
> > more than one parts in their name.
> >
> > The series covers the UCF, PCIe, PCIe target, CPU memory latency, and
> > chip-to-chip interconnect PMUs. It provides symbolic names for the raw
> > event encodings and metrics for bandwidth, frequency, and average read
> > latency.
> >
> > The PCIe and PCIe target PMUs are named
> nvidia_pcie_pmu_<socket>_rc_<rc>
> > and nvidia_pcie_tgt_pmu_<socket>_rc_<rc>. Their json Unit uses the
> > existing comma-separated form ("nvidia_pcie_pmu_,rc_"), but perf only
> > merged instances that differ in the trailing number, so these events and
> > metrics gave one result per socket and were reported incorrectly (e.g.
> > with --metric-only), as discussed in v1. Patches 6-9 fix this:
> >
> > - Patch 6 adds a check of the cpumasks of all merged PMU instances to the
> > zero-count skip in perf stat, so a socket that counts nothing shows 0
> > instead of having its row hidden.
> > - Patch 7 merges PMU instances that match the same comma-separated
> json
> > Unit. This also applies to the HiSilicon hisi_sccl PMUs, which use the
> > same json form; not tested on HiSilicon hardware.
> > - Patch 8 labels a merged uncore counter after all of its PMUs, e.g.
> > nvidia_pcie_pmu_*_rc_*/cycles/ or nvidia_ucf_pmu/cycles/, instead of
> > after the first instance, such as nvidia_pcie_pmu_0_rc_0/cycles/.
> > Output with --no-aggr is unchanged.
> > - Patch 9 describes these PMU names in the ABI document.
> >
> > Changes in v2:
> > - Move the uncore JSON out of the sys directory and remove the
> > "Compat" fields. Thanks to Ian Rogers for the feedback.
> > - Drop "perf jevents: Process model files before sys subdirectories",
> > which this series no longer needs.
> > - Add UCF SLC and memory bandwidth metrics from all sources to local
> > CMEM (read, write and read+write) and from local sources to local
> > CMEM and to remote memory, PCIe bandwidth metrics to local
> > destinations, and read+write bandwidth metrics for UCF SLC, UCF
> > memory and PCIe. Thanks to Chun-Tse Shao for the suggestion.
> > - Add patches 6-9 to fix the PCIe instance aggregation. Thanks to Ian
> > Rogers and Chun-Tse Shao for the pointers.
> >
> > v1: https://lore.kernel.org/all/20261019164241.403644-1-
> bwicaksono@nvidia.com/
>
> Why don't we look to fix code in drivers/perf? This series introduces
> PMU instances, overloads the meaning of aliases, and a bunch of other
> silly complexity due to poor reviews and maintenance of drivers/perf -
> specifically by not pointing out the ABI issues. Isn't this a
> straightforward, whoops we did a bad suffix and here's the patch to
> rename our PMU in the driver? Throwing more complexity at the problem
> doesn't feel like the right fix.
Hi Ian,
My apologies for the names not following perf's PMU naming convention.
I will be more careful about this in future.
These names (nvidia_pcie_pmu_<socket>_rc_<root complex> and
nvidia_pcie_tgt_pmu_<socket>_rc_<root complex>) have been upstream
since v7.1, and several customers already rely on them. Renaming them in
the driver would break their use case.
Given that, what would you suggest as the next step? Would handling these
names in perf, as in patch 7 and 8, be reasonable, or do you have another
approach in mind?
Will, do you have any comment on this?
Thanks,
Besar
>
> Thanks,
> Ian
>
> > Besar Wicaksono (9):
> > perf jevents: Add support for NVIDIA Tegra410 UCF PMU aliasing
> > perf jevents: Add support for NVIDIA Tegra410 PCIE PMU aliasing
> > perf jevents: Add support for NVIDIA Tegra410 PCIE-TGT PMU aliasing
> > perf jevents: Add support for NVIDIA Tegra410 CPU Memory Latency
> PMU
> > aliasing
> > perf jevents: Add support for NVIDIA Tegra410 C2C PMU aliasing
> > perf stat: Check merged PMU instance's cpumasks when skipping zero
> > counts
> > perf pmu: Merge PMU instances that match the same comma-separated
> json
> > Unit
> > perf evsel: Name a merged uncore counter after all of its PMUs
> > perf Documentation: Describe PMU names numbered in more than one
> place
> >
> > .../testing/sysfs-bus-event_source-devices | 14 +
> > .../arm64/nvidia/t410/uncore-cpu_mem.json | 43 +
> > .../arm64/nvidia/t410/uncore-nvclink.json | 67 ++
> > .../arm64/nvidia/t410/uncore-nvdlink.json | 43 +
> > .../arm64/nvidia/t410/uncore-nvlink_c2c.json | 115 +++
> > .../arch/arm64/nvidia/t410/uncore-pcie.json | 249 ++++++
> > .../arm64/nvidia/t410/uncore-pcie_tgt.json | 83 ++
> > .../arch/arm64/nvidia/t410/uncore-ucf.json | 764
> ++++++++++++++++++
> > tools/perf/tests/pmu.c | 134 +++
> > tools/perf/util/evlist.c | 2 +-
> > tools/perf/util/evsel.c | 83 +-
> > tools/perf/util/evsel.h | 2 +-
> > tools/perf/util/parse-events.c | 2 +-
> > tools/perf/util/pmu.c | 65 ++
> > tools/perf/util/pmu.h | 9 +
> > tools/perf/util/pmus.c | 47 ++
> > tools/perf/util/pmus.h | 1 +
> > tools/perf/util/stat-display.c | 20 +
> > 18 files changed, 1737 insertions(+), 6 deletions(-)
> > create mode 100644 tools/perf/pmu-
> events/arch/arm64/nvidia/t410/uncore-cpu_mem.json
> > create mode 100644 tools/perf/pmu-
> events/arch/arm64/nvidia/t410/uncore-nvclink.json
> > create mode 100644 tools/perf/pmu-
> events/arch/arm64/nvidia/t410/uncore-nvdlink.json
> > create mode 100644 tools/perf/pmu-
> events/arch/arm64/nvidia/t410/uncore-nvlink_c2c.json
> > create mode 100644 tools/perf/pmu-
> events/arch/arm64/nvidia/t410/uncore-pcie.json
> > create mode 100644 tools/perf/pmu-
> events/arch/arm64/nvidia/t410/uncore-pcie_tgt.json
> > create mode 100644 tools/perf/pmu-
> events/arch/arm64/nvidia/t410/uncore-ucf.json
> >
> > --
> > 2.43.0
> >
^ permalink raw reply [flat|nested] 12+ messages in thread