[PATCH v2 0/5] drm/panel: Use mipi_dsi_*_multi() in feiyang and rm68200

[PATCH v2 0/5] drm/panel: Use mipi_dsi_*_multi() in feiyang and rm68200

[Hsieh Hung-En]

Hi,

This series converts the Feiyang FY07024DI26A30-D and Raydium RM68200
panel drivers to the MIPI DSI multi-context helpers, as suggested in
Documentation/gpu/todo.rst.

The first two patches fix pre-existing prepare() error paths that leave
regulators enabled on failure. The following two patches convert the
DCS helpers and initialization sequences, with command failures
propagated through the cleanup paths. The final patch normalizes the
RM68200 hexadecimal literals.

In RM68200, initialization errors were previously only logged, allowing
prepare() to succeed despite incomplete initialization. The conversion
now stops subsequent DCS transfers and returns the first error.
Thanks to Doug Anderson for reviewing v1 and confirming that this
fail-fast behavior is appropriate.

This series is independent of Osama Abdelkader's
"drm/panel: Use managed helpers in DSI panels" v7 series, which modifies
probe() and remove() rather than the panel callbacks and initialization
sequences.

Neither panel has been tested on hardware.

Changes in v2:
- 1/5 (new): Fix Feiyang prepare() error cleanup, as pointed out by Doug.
- 2/5 (new): Fix RM68200 prepare() error cleanup, addressing findings
  from Sashiko and Doug.
- 3/5 (v1 1/3): Replace the Feiyang initialization table with seven
  direct DCS _multi() calls and use the new error cleanup path.
- 4/5 (v1 2/3 + 3/3): Merge the RM68200 conversions, as suggested by
  Doug, and propagate initialization errors through prepare().
- 5/5 (new): Convert RM68200 hexadecimal literals to lowercase,
  following Doug's suggestion.

Validation:
- Each of the five commits was built individually on arm64 with W=1,
  without compiler warnings or errors.
- Checkpatch passed, except for the expected msleep(10)
  warning in the Feiyang error cleanup patch.
- Mechanically compared all 58 RM68200 initialization calls against
  v1, confirming unchanged command addresses, payloads, and ordering.
- Verified identical compiled code and data sections before and
  after the hexadecimal formatting change in patch 5/5.

v1: https://lore.kernel.org/all/20261014135028.1438841-1-hungen3108@gmail.com/

Hsieh Hung-En (5):
  drm/panel: feiyang-fy07024di26a30d: Fix prepare error cleanup
  drm/panel: raydium-rm68200: Fix prepare error cleanup
  drm/panel: feiyang-fy07024di26a30d: Use mipi_dsi_*_multi() functions
  drm/panel: raydium-rm68200: Use mipi_dsi_*_multi() functions
  drm/panel: raydium-rm68200: Use lowercase hex literals

 .../drm/panel/panel-feiyang-fy07024di26a30d.c |  81 ++---
 drivers/gpu/drm/panel/panel-raydium-rm68200.c | 285 ++++++++----------
 2 files changed, 179 insertions(+), 187 deletions(-)


base-commit: a1e63ab695ad76850ab9787b9eb6aab695dc2965
-- 
2.43.0

[PATCH v2 1/5] drm/panel: feiyang-fy07024di26a30d: Fix prepare error cleanup

[Hsieh Hung-En]

feiyang_prepare() returns without disabling previously enabled
regulators if enabling AVDD or writing DCS commands fails. Since
drm_panel_prepare() does not mark the panel as prepared on failure,
drm_panel_unprepare() does not call the driver's unprepare() callback,
leaving regulator enable counts elevated even after subsequent
successful prepare/unprepare cycles.

Disable DVDD if enabling AVDD fails. On a DCS write failure, restore
the reset GPIO to its unprepared state and disable both regulators,
preserving the existing 10 ms power-off interval between AVDD and DVDD.

Fixes: 69dc678abc2b ("drm/panel: Add Feiyang FY07024DI26A30-D MIPI-DSI LCD panel")
Reported-by: Douglas Anderson <dianders@chromium.org>
Closes: https://lore.kernel.org/r/CAD=FV=Xm48DUT==8HuuGCSFZtLTEk-W2Q6UTfqt-MnM4nULzTw@mail.gmail.com
Signed-off-by: Hsieh Hung-En <hungen3108@gmail.com>
---

Notes:
    Power sequencing note:
    
    The error path retains the 10 ms AVDD-to-DVDD shutdown interval
    used by unprepare().
    
    The FY07024DI26A30-D datasheet, Section 7.3 (Power, Signal sequence),
    specifies T10 > 0 between AVDD/VGL reaching GND and DVDD starting
    to fall. The delay allows time for AVDD to discharge before disabling
    DVDD, but compliance with T10 has not been verified on hardware.
    
    The existing unprepare() comment associates the delay with T11,
    which actually specifies the DVDD fall time (0 < T11 <= 10 ms).
    That comment can be corrected separately.
    
    The msleep(10) checkpatch warning is expected. T10 has no specified
    upper bound, so a longer sleep does not violate that timing constraint.
    msleep() is retained to match the existing unprepare() sequence.
    
    Datasheet:
    https://files.pine64.org/doc/datasheet/pine64/FY07024DI26A30-D_feiyang_LCD_panel.pdf

 .../gpu/drm/panel/panel-feiyang-fy07024di26a30d.c | 15 +++++++++++++--
 1 file changed, 13 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/panel/panel-feiyang-fy07024di26a30d.c b/drivers/gpu/drm/panel/panel-feiyang-fy07024di26a30d.c
index c1d8ca5ca6e1..bb4cc1ea2ece 100644
--- a/drivers/gpu/drm/panel/panel-feiyang-fy07024di26a30d.c
+++ b/drivers/gpu/drm/panel/panel-feiyang-fy07024di26a30d.c
@@ -59,7 +59,7 @@ static int feiyang_prepare(struct drm_panel *panel)
 
 	ret = regulator_enable(ctx->avdd);
 	if (ret)
-		return ret;
+		goto disable_dvdd;
 
 	/* T3 (dvdd rise + avdd start + avdd rise) T3 >= 20ms */
 	msleep(20);
@@ -84,10 +84,21 @@ static int feiyang_prepare(struct drm_panel *panel)
 		ret = mipi_dsi_dcs_write_buffer(dsi, cmd->data,
 						FEIYANG_INIT_CMD_LEN);
 		if (ret < 0)
-			return ret;
+			goto assert_reset;
 	}
 
 	return 0;
+
+assert_reset:
+	gpiod_set_value(ctx->reset, 0);
+	regulator_disable(ctx->avdd);
+
+	/* Preserve the AVDD-to-DVDD shutdown delay from unprepare(). */
+	msleep(10);
+
+disable_dvdd:
+	regulator_disable(ctx->dvdd);
+	return ret;
 }
 
 static int feiyang_enable(struct drm_panel *panel)
-- 
2.43.0

[PATCH v2 2/5] drm/panel: raydium-rm68200: Fix prepare error cleanup

[Hsieh Hung-En]

rm68200_prepare() returns without disabling the supply regulator if
EXIT_SLEEP_MODE or SET_DISPLAY_ON fails. Since drm_panel_prepare() does
not mark the panel as prepared on failure, drm_panel_unprepare() does
not call the driver's unprepare() callback, leaving the regulator
enable count elevated even after subsequent successful
prepare/unprepare cycles.

On failure, restore the reset GPIO to its unprepared state, following
the existing reset sequence in unprepare(), and disable the supply
regulator before returning the original error.

Fixes: 2b7ed18bed1a ("drm/panel: Add support for Raydium RM68200 panel driver")
Reported-by: Sashiko <sashiko-bot@kernel.org>
Closes: https://lore.kernel.org/r/sashiko-outbox-171393@kernel.org
Signed-off-by: Hsieh Hung-En <hungen3108@gmail.com>
---

Notes:
    In this patch, rm68200_init_sequence() still returns void and only
    logs DCS write failures. These failures do not cause prepare() to
    return early. A later patch in this series will propagate
    initialization errors through prepare(), where this cleanup path
    will also handle them.
    
    The error path does not send SET_DISPLAY_OFF or ENTER_SLEEP_MODE,
    as DCS communication may already have failed. Instead, it follows
    the existing reset and regulator shutdown sequence in unprepare().

 drivers/gpu/drm/panel/panel-raydium-rm68200.c | 13 +++++++++++--
 1 file changed, 11 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/panel/panel-raydium-rm68200.c b/drivers/gpu/drm/panel/panel-raydium-rm68200.c
index c535dc931903..3a59eb00274d 100644
--- a/drivers/gpu/drm/panel/panel-raydium-rm68200.c
+++ b/drivers/gpu/drm/panel/panel-raydium-rm68200.c
@@ -277,17 +277,26 @@ static int rm68200_prepare(struct drm_panel *panel)
 
 	ret = mipi_dsi_dcs_exit_sleep_mode(dsi);
 	if (ret)
-		return ret;
+		goto assert_reset;
 
 	msleep(125);
 
 	ret = mipi_dsi_dcs_set_display_on(dsi);
 	if (ret)
-		return ret;
+		goto assert_reset;
 
 	msleep(20);
 
 	return 0;
+
+assert_reset:
+	if (ctx->reset_gpio) {
+		gpiod_set_value_cansleep(ctx->reset_gpio, 1);
+		msleep(20);
+	}
+	/* Balance the regulator enable count on prepare failure. */
+	regulator_disable(ctx->supply);
+	return ret;
 }
 
 static int rm68200_get_modes(struct drm_panel *panel,
-- 
2.43.0

[PATCH v2 3/5] drm/panel: feiyang-fy07024di26a30d: Use mipi_dsi_*_multi() functions

[Hsieh Hung-En]

Replace the deprecated MIPI DSI DCS helpers with their _multi variants,
as suggested in Documentation/gpu/todo.rst.

Replace the initialization command table and loop with seven direct
mipi_dsi_dcs_write_seq_multi() calls. Preserve the original command
order and values, using lowercase hexadecimal literals.

In prepare(), the first failed DCS write prevents subsequent transfers
and its error is propagated through the cleanup path added by the
preceding patch. The helpers also log command failures.

In unprepare(), clear accum_err between commands so that ENTER_SLEEP_MODE
is still attempted if SET_DISPLAY_OFF fails, preserving the original
error handling behavior.

In disable(), ignore SET_DISPLAY_OFF errors to allow drm_panel_disable()
to clear panel->enabled, avoiding a stale enabled state after the panel
is powered off. This follows commit 00efe8a68565 ("drm/panel:
ronbo-rb070d30: Ignore DCS errors in disable()"). Command failures
remain logged by the helper.

Signed-off-by: Hsieh Hung-En <hungen3108@gmail.com>
---

Notes:
    Changes in v2:
    - Replace the initialization command table with direct
      mipi_dsi_dcs_write_seq_multi() calls, as suggested by Doug.
    - Route initialization errors through the cleanup path added in 1/5.
    - Convert initialization command values to lowercase hex.
    - Drop the previous Reviewed-by tag due to the initialization rework.
    
    The seven initialization commands were checked against the original
    table; their order and values are unchanged.

 .../drm/panel/panel-feiyang-fy07024di26a30d.c | 68 +++++++++----------
 1 file changed, 33 insertions(+), 35 deletions(-)

diff --git a/drivers/gpu/drm/panel/panel-feiyang-fy07024di26a30d.c b/drivers/gpu/drm/panel/panel-feiyang-fy07024di26a30d.c
index bb4cc1ea2ece..fa304eb7453b 100644
--- a/drivers/gpu/drm/panel/panel-feiyang-fy07024di26a30d.c
+++ b/drivers/gpu/drm/panel/panel-feiyang-fy07024di26a30d.c
@@ -13,8 +13,6 @@
 #include <linux/module.h>
 #include <linux/regulator/consumer.h>
 
-#define FEIYANG_INIT_CMD_LEN	2
-
 struct feiyang {
 	struct drm_panel	panel;
 	struct mipi_dsi_device	*dsi;
@@ -29,25 +27,21 @@ static inline struct feiyang *panel_to_feiyang(struct drm_panel *panel)
 	return container_of(panel, struct feiyang, panel);
 }
 
-struct feiyang_init_cmd {
-	u8 data[FEIYANG_INIT_CMD_LEN];
-};
-
-static const struct feiyang_init_cmd feiyang_init_cmds[] = {
-	{ .data = { 0x80, 0x58 } },
-	{ .data = { 0x81, 0x47 } },
-	{ .data = { 0x82, 0xD4 } },
-	{ .data = { 0x83, 0x88 } },
-	{ .data = { 0x84, 0xA9 } },
-	{ .data = { 0x85, 0xC3 } },
-	{ .data = { 0x86, 0x82 } },
-};
+static void feiyang_init(struct mipi_dsi_multi_context *dsi_ctx)
+{
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x80, 0x58);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x81, 0x47);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x82, 0xd4);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x83, 0x88);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x84, 0xa9);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x85, 0xc3);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x86, 0x82);
+}
 
 static int feiyang_prepare(struct drm_panel *panel)
 {
 	struct feiyang *ctx = panel_to_feiyang(panel);
-	struct mipi_dsi_device *dsi = ctx->dsi;
-	unsigned int i;
+	struct mipi_dsi_multi_context dsi_ctx = { .dsi = ctx->dsi };
 	int ret;
 
 	ret = regulator_enable(ctx->dvdd);
@@ -77,15 +71,10 @@ static int feiyang_prepare(struct drm_panel *panel)
 	/* T12 (video & logic signal rise + backlight rise) T12 >= 200ms */
 	msleep(200);
 
-	for (i = 0; i < ARRAY_SIZE(feiyang_init_cmds); i++) {
-		const struct feiyang_init_cmd *cmd =
-						&feiyang_init_cmds[i];
-
-		ret = mipi_dsi_dcs_write_buffer(dsi, cmd->data,
-						FEIYANG_INIT_CMD_LEN);
-		if (ret < 0)
-			goto assert_reset;
-	}
+	feiyang_init(&dsi_ctx);
+	ret = dsi_ctx.accum_err;
+	if (ret < 0)
+		goto assert_reset;
 
 	return 0;
 
@@ -104,32 +93,41 @@ static int feiyang_prepare(struct drm_panel *panel)
 static int feiyang_enable(struct drm_panel *panel)
 {
 	struct feiyang *ctx = panel_to_feiyang(panel);
+	struct mipi_dsi_multi_context dsi_ctx = { .dsi = ctx->dsi };
 
 	/* T12 (video & logic signal rise + backlight rise) T12 >= 200ms */
 	msleep(200);
 
-	return mipi_dsi_dcs_set_display_on(ctx->dsi);
+	mipi_dsi_dcs_set_display_on_multi(&dsi_ctx);
+
+	return dsi_ctx.accum_err;
 }
 
 static int feiyang_disable(struct drm_panel *panel)
 {
 	struct feiyang *ctx = panel_to_feiyang(panel);
+	struct mipi_dsi_multi_context dsi_ctx = { .dsi = ctx->dsi };
+
+	mipi_dsi_dcs_set_display_off_multi(&dsi_ctx);
 
-	return mipi_dsi_dcs_set_display_off(ctx->dsi);
+	/*
+	 * Returning an error would leave panel->enabled set, causing the
+	 * next enable to be skipped even after unprepare powers off the panel.
+	 * The helper above already logs any command failure.
+	 */
+	return 0;
 }
 
 static int feiyang_unprepare(struct drm_panel *panel)
 {
 	struct feiyang *ctx = panel_to_feiyang(panel);
-	int ret;
+	struct mipi_dsi_multi_context dsi_ctx = { .dsi = ctx->dsi };
 
-	ret = mipi_dsi_dcs_set_display_off(ctx->dsi);
-	if (ret < 0)
-		dev_err(panel->dev, "failed to set display off: %d\n", ret);
+	mipi_dsi_dcs_set_display_off_multi(&dsi_ctx);
 
-	ret = mipi_dsi_dcs_enter_sleep_mode(ctx->dsi);
-	if (ret < 0)
-		dev_err(panel->dev, "failed to enter sleep mode: %d\n", ret);
+	/* Attempt to enter sleep mode even if display off failed. */
+	dsi_ctx.accum_err = 0;
+	mipi_dsi_dcs_enter_sleep_mode_multi(&dsi_ctx);
 
 	/* T13 (backlight fall + video & logic signal fall) T13 >= 200ms */
 	msleep(200);
-- 
2.43.0

[PATCH v2 4/5] drm/panel: raydium-rm68200: Use mipi_dsi_*_multi() functions

[Hsieh Hung-En]

Replace the deprecated MIPI DSI DCS helpers and custom DCS write
wrappers with their multi-context equivalents.

Preserve individual DCS transactions for registers that do not support
auto-increment. Share the multi-context with rm68200_init_sequence()
so that initialization failures stop subsequent DCS transfers and
cause prepare() to fail instead of only being logged. Errors are
handled by the cleanup path in prepare().

Use mipi_dsi_msleep() to skip delays after a failed command. In
unprepare(), clear accum_err between commands so that ENTER_SLEEP_MODE
is still attempted if SET_DISPLAY_OFF fails.

The new helpers log failures at error level. Initialization write
errors are no longer rate-limited.

Signed-off-by: Hsieh Hung-En <hungen3108@gmail.com>
---

Notes:
    Changes in v2:
    - Merge v1 patches 2/3 and 3/3, as suggested by Doug.
    - Route initialization and DCS command failures through the prepare()
      error cleanup path introduced earlier in this series.
    - Drop Doug's Reviewed-by tag from v1 3/3 because the patches were
      merged and the error handling was reworked.
    
    Validation:
    - Mechanically compared all 58 initialization calls against v1.
      Command addresses, payloads, and ordering are unchanged.
    - Verified the expansion of dcs_write_cmd_seq() in v1 using
      preprocessed output, confirming that each register address is
      written in a separate DCS transaction. The macro is unchanged
      from v1.
    
    The uppercase hexadecimal literals are retained in this patch.
    Their formatting will be addressed separately in the next patch.

 drivers/gpu/drm/panel/panel-raydium-rm68200.c | 208 ++++++++----------
 1 file changed, 91 insertions(+), 117 deletions(-)

diff --git a/drivers/gpu/drm/panel/panel-raydium-rm68200.c b/drivers/gpu/drm/panel/panel-raydium-rm68200.c
index 3a59eb00274d..8ce89f09540c 100644
--- a/drivers/gpu/drm/panel/panel-raydium-rm68200.c
+++ b/drivers/gpu/drm/panel/panel-raydium-rm68200.c
@@ -98,149 +98,123 @@ static inline struct rm68200 *panel_to_rm68200(struct drm_panel *panel)
 	return container_of(panel, struct rm68200, panel);
 }
 
-static void rm68200_dcs_write_buf(struct rm68200 *ctx, const void *data,
-				  size_t len)
-{
-	struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
-	int err;
-
-	err = mipi_dsi_dcs_write_buffer(dsi, data, len);
-	if (err < 0)
-		dev_err_ratelimited(ctx->dev, "MIPI DSI DCS write buffer failed: %d\n", err);
-}
-
-static void rm68200_dcs_write_cmd(struct rm68200 *ctx, u8 cmd, u8 value)
-{
-	struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
-	int err;
-
-	err = mipi_dsi_dcs_write(dsi, cmd, &value, 1);
-	if (err < 0)
-		dev_err_ratelimited(ctx->dev, "MIPI DSI DCS write failed: %d\n", err);
-}
-
-#define dcs_write_seq(ctx, seq...)				\
-({								\
-	static const u8 d[] = { seq };				\
-								\
-	rm68200_dcs_write_buf(ctx, d, ARRAY_SIZE(d));		\
-})
-
 /*
  * This panel is not able to auto-increment all cmd addresses so for some of
  * them, we need to send them one by one...
+ *
+ * Use arr instead of d to avoid shadowing the local d[] declared by
+ * mipi_dsi_dcs_write_var_seq_multi().
  */
-#define dcs_write_cmd_seq(ctx, cmd, seq...)			\
-({								\
-	static const u8 d[] = { seq };				\
-	unsigned int i;						\
-								\
-	for (i = 0; i < ARRAY_SIZE(d) ; i++)			\
-		rm68200_dcs_write_cmd(ctx, cmd + i, d[i]);	\
-})
-
-static void rm68200_init_sequence(struct rm68200 *ctx)
+#define dcs_write_cmd_seq(dsi_ctx, cmd, seq...)			\
+	do {								\
+		static const u8 arr[] = { seq };			\
+		unsigned int i;						\
+									\
+		for (i = 0; i < ARRAY_SIZE(arr); i++)		\
+			mipi_dsi_dcs_write_var_seq_multi(dsi_ctx,	\
+							(cmd) + i, arr[i]); \
+	} while (0)
+
+static void rm68200_init_sequence(struct mipi_dsi_multi_context *dsi_ctx)
 {
 	/* Enter CMD2 with page 0 */
-	dcs_write_seq(ctx, MCS_CMD_MODE_SW, MCS_CMD2_P0);
-	dcs_write_cmd_seq(ctx, MCS_EXT_PWR_IC, 0xC0, 0x53, 0x00);
-	dcs_write_seq(ctx, MCS_BT2CTR, 0xE5);
-	dcs_write_seq(ctx, MCS_SETAVDD, 0x0A);
-	dcs_write_seq(ctx, MCS_SETAVEE, 0x0A);
-	dcs_write_seq(ctx, MCS_SGOPCTR, 0x52);
-	dcs_write_seq(ctx, MCS_BT3CTR, 0x53);
-	dcs_write_seq(ctx, MCS_BT4CTR, 0x5A);
-	dcs_write_seq(ctx, MCS_INVCTR, 0x00);
-	dcs_write_seq(ctx, MCS_STBCTR, 0x0A);
-	dcs_write_seq(ctx, MCS_SDCTR, 0x06);
-	dcs_write_seq(ctx, MCS_VCMCTR, 0x56);
-	dcs_write_seq(ctx, MCS_SETVGN, 0xA0, 0x00);
-	dcs_write_seq(ctx, MCS_SETVGP, 0xA0, 0x00);
-	dcs_write_seq(ctx, MCS_SW_CTRL, 0x11); /* 2 data lanes, see doc */
-
-	dcs_write_seq(ctx, MCS_CMD_MODE_SW, MCS_CMD2_P2);
-	dcs_write_seq(ctx, GOA_VSTV1, 0x05);
-	dcs_write_seq(ctx, 0x02, 0x0B);
-	dcs_write_seq(ctx, 0x03, 0x0F);
-	dcs_write_seq(ctx, 0x04, 0x7D, 0x00, 0x50);
-	dcs_write_cmd_seq(ctx, GOA_VSTV2, 0x05, 0x16, 0x0D, 0x11, 0x7D, 0x00,
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_CMD_MODE_SW, MCS_CMD2_P0);
+	dcs_write_cmd_seq(dsi_ctx, MCS_EXT_PWR_IC, 0xC0, 0x53, 0x00);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_BT2CTR, 0xE5);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_SETAVDD, 0x0A);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_SETAVEE, 0x0A);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_SGOPCTR, 0x52);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_BT3CTR, 0x53);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_BT4CTR, 0x5A);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_INVCTR, 0x00);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_STBCTR, 0x0A);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_SDCTR, 0x06);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_VCMCTR, 0x56);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_SETVGN, 0xA0, 0x00);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_SETVGP, 0xA0, 0x00);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_SW_CTRL, 0x11); /* 2 data lanes, see doc */
+
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_CMD_MODE_SW, MCS_CMD2_P2);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, GOA_VSTV1, 0x05);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x02, 0x0B);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x03, 0x0F);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x04, 0x7D, 0x00, 0x50);
+	dcs_write_cmd_seq(dsi_ctx, GOA_VSTV2, 0x05, 0x16, 0x0D, 0x11, 0x7D, 0x00,
 			  0x50);
-	dcs_write_cmd_seq(ctx, GOA_VCLK1, 0x07, 0x08, 0x01, 0x02, 0x00, 0x7D,
+	dcs_write_cmd_seq(dsi_ctx, GOA_VCLK1, 0x07, 0x08, 0x01, 0x02, 0x00, 0x7D,
 			  0x00, 0x85, 0x08);
-	dcs_write_cmd_seq(ctx, GOA_VCLK2, 0x03, 0x04, 0x05, 0x06, 0x00, 0x7D,
+	dcs_write_cmd_seq(dsi_ctx, GOA_VCLK2, 0x03, 0x04, 0x05, 0x06, 0x00, 0x7D,
 			  0x00, 0x85, 0x08);
-	dcs_write_seq(ctx, GOA_VCLK_OPT1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		      0x00, 0x00, 0x00, 0x00);
-	dcs_write_cmd_seq(ctx, GOA_BICLK1, 0x07, 0x08);
-	dcs_write_seq(ctx, 0x2D, 0x01);
-	dcs_write_seq(ctx, 0x2F, 0x02, 0x00, 0x40, 0x05, 0x08, 0x54, 0x7D,
-		      0x00);
-	dcs_write_cmd_seq(ctx, GOA_BICLK2, 0x03, 0x04, 0x05, 0x06, 0x00);
-	dcs_write_seq(ctx, 0x3D, 0x40);
-	dcs_write_seq(ctx, 0x3F, 0x05, 0x08, 0x54, 0x7D, 0x00);
-	dcs_write_seq(ctx, GOA_BICLK3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		      0x00, 0x00, 0x00, 0x00, 0x00);
-	dcs_write_seq(ctx, GOA_BICLK4, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		      0x00, 0x00);
-	dcs_write_seq(ctx, 0x58, 0x00, 0x00, 0x00);
-	dcs_write_seq(ctx, GOA_BICLK_OPT1, 0x00, 0x00, 0x00, 0x00, 0x00);
-	dcs_write_seq(ctx, GOA_BICLK_OPT2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-		      0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00);
-	dcs_write_seq(ctx, MCS_GOA_GPO1, 0x00, 0x00, 0x00, 0x00);
-	dcs_write_seq(ctx, MCS_GOA_GPO2, 0x00, 0x20, 0x00);
-	dcs_write_seq(ctx, MCS_GOA_EQ, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08,
-		      0x00, 0x00);
-	dcs_write_seq(ctx, MCS_GOA_CLK_GALLON, 0x00, 0x00);
-	dcs_write_cmd_seq(ctx, MCS_GOA_FS_SEL0, 0xBF, 0x02, 0x06, 0x14, 0x10,
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, GOA_VCLK_OPT1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+				     0x00, 0x00, 0x00, 0x00);
+	dcs_write_cmd_seq(dsi_ctx, GOA_BICLK1, 0x07, 0x08);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x2D, 0x01);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x2F, 0x02, 0x00, 0x40, 0x05, 0x08, 0x54, 0x7D,
+				     0x00);
+	dcs_write_cmd_seq(dsi_ctx, GOA_BICLK2, 0x03, 0x04, 0x05, 0x06, 0x00);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x3D, 0x40);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x3F, 0x05, 0x08, 0x54, 0x7D, 0x00);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, GOA_BICLK3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+				     0x00, 0x00, 0x00, 0x00, 0x00);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, GOA_BICLK4, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+				     0x00, 0x00);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x58, 0x00, 0x00, 0x00);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, GOA_BICLK_OPT1, 0x00, 0x00, 0x00, 0x00, 0x00);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, GOA_BICLK_OPT2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+				     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_GOA_GPO1, 0x00, 0x00, 0x00, 0x00);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_GOA_GPO2, 0x00, 0x20, 0x00);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_GOA_EQ, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08,
+				     0x00, 0x00);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_GOA_CLK_GALLON, 0x00, 0x00);
+	dcs_write_cmd_seq(dsi_ctx, MCS_GOA_FS_SEL0, 0xBF, 0x02, 0x06, 0x14, 0x10,
 			  0x16, 0x12, 0x08, 0x3F);
-	dcs_write_cmd_seq(ctx, MCS_GOA_FS_SEL1, 0x3F, 0x3F, 0x3F, 0x3F, 0x0C,
+	dcs_write_cmd_seq(dsi_ctx, MCS_GOA_FS_SEL1, 0x3F, 0x3F, 0x3F, 0x3F, 0x0C,
 			  0x0A, 0x0E, 0x3F, 0x3F, 0x00);
-	dcs_write_cmd_seq(ctx, MCS_GOA_FS_SEL2, 0x04, 0x3F, 0x3F, 0x3F, 0x3F,
+	dcs_write_cmd_seq(dsi_ctx, MCS_GOA_FS_SEL2, 0x04, 0x3F, 0x3F, 0x3F, 0x3F,
 			  0x05, 0x01, 0x3F, 0x3F, 0x0F);
-	dcs_write_cmd_seq(ctx, MCS_GOA_FS_SEL3, 0x0B, 0x0D, 0x3F, 0x3F, 0x3F,
+	dcs_write_cmd_seq(dsi_ctx, MCS_GOA_FS_SEL3, 0x0B, 0x0D, 0x3F, 0x3F, 0x3F,
 			  0x3F);
-	dcs_write_cmd_seq(ctx, 0xA2, 0x3F, 0x09, 0x13, 0x17, 0x11, 0x15);
-	dcs_write_cmd_seq(ctx, 0xA9, 0x07, 0x03, 0x3F);
-	dcs_write_cmd_seq(ctx, MCS_GOA_BS_SEL0, 0x3F, 0x05, 0x01, 0x17, 0x13,
+	dcs_write_cmd_seq(dsi_ctx, 0xA2, 0x3F, 0x09, 0x13, 0x17, 0x11, 0x15);
+	dcs_write_cmd_seq(dsi_ctx, 0xA9, 0x07, 0x03, 0x3F);
+	dcs_write_cmd_seq(dsi_ctx, MCS_GOA_BS_SEL0, 0x3F, 0x05, 0x01, 0x17, 0x13,
 			  0x15, 0x11, 0x0F, 0x3F);
-	dcs_write_cmd_seq(ctx, MCS_GOA_BS_SEL1, 0x3F, 0x3F, 0x3F, 0x3F, 0x0B,
+	dcs_write_cmd_seq(dsi_ctx, MCS_GOA_BS_SEL1, 0x3F, 0x3F, 0x3F, 0x3F, 0x0B,
 			  0x0D, 0x09, 0x3F, 0x3F, 0x07);
-	dcs_write_cmd_seq(ctx, MCS_GOA_BS_SEL2, 0x03, 0x3F, 0x3F, 0x3F, 0x3F,
+	dcs_write_cmd_seq(dsi_ctx, MCS_GOA_BS_SEL2, 0x03, 0x3F, 0x3F, 0x3F, 0x3F,
 			  0x02, 0x06, 0x3F, 0x3F, 0x08);
-	dcs_write_cmd_seq(ctx, MCS_GOA_BS_SEL3, 0x0C, 0x0A, 0x3F, 0x3F, 0x3F,
+	dcs_write_cmd_seq(dsi_ctx, MCS_GOA_BS_SEL3, 0x0C, 0x0A, 0x3F, 0x3F, 0x3F,
 			  0x3F, 0x3F, 0x0E, 0x10, 0x14);
-	dcs_write_cmd_seq(ctx, MCS_GOA_BS_SEL4, 0x12, 0x16, 0x00, 0x04, 0x3F);
-	dcs_write_seq(ctx, 0xDC, 0x02);
-	dcs_write_seq(ctx, 0xDE, 0x12);
+	dcs_write_cmd_seq(dsi_ctx, MCS_GOA_BS_SEL4, 0x12, 0x16, 0x00, 0x04, 0x3F);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xDC, 0x02);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xDE, 0x12);
 
-	dcs_write_seq(ctx, MCS_CMD_MODE_SW, 0x0E); /* No documentation */
-	dcs_write_seq(ctx, 0x01, 0x75);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_CMD_MODE_SW, 0x0E); /* No documentation */
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x01, 0x75);
 
-	dcs_write_seq(ctx, MCS_CMD_MODE_SW, MCS_CMD2_P3);
-	dcs_write_cmd_seq(ctx, MCS_GAMMA_VP, 0x00, 0x0C, 0x12, 0x0E, 0x06,
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_CMD_MODE_SW, MCS_CMD2_P3);
+	dcs_write_cmd_seq(dsi_ctx, MCS_GAMMA_VP, 0x00, 0x0C, 0x12, 0x0E, 0x06,
 			  0x12, 0x0E, 0x0B, 0x15, 0x0B, 0x10, 0x07, 0x0F,
 			  0x12, 0x0C, 0x00);
-	dcs_write_cmd_seq(ctx, MCS_GAMMA_VN, 0x00, 0x0C, 0x12, 0x0E, 0x06,
+	dcs_write_cmd_seq(dsi_ctx, MCS_GAMMA_VN, 0x00, 0x0C, 0x12, 0x0E, 0x06,
 			  0x12, 0x0E, 0x0B, 0x15, 0x0B, 0x10, 0x07, 0x0F,
 			  0x12, 0x0C, 0x00);
 
 	/* Exit CMD2 */
-	dcs_write_seq(ctx, MCS_CMD_MODE_SW, MCS_CMD1_UCS);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_CMD_MODE_SW, MCS_CMD1_UCS);
 }
 
 static int rm68200_unprepare(struct drm_panel *panel)
 {
 	struct rm68200 *ctx = panel_to_rm68200(panel);
 	struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
-	int ret;
+	struct mipi_dsi_multi_context dsi_ctx = { .dsi = dsi };
 
-	ret = mipi_dsi_dcs_set_display_off(dsi);
-	if (ret)
-		dev_warn(panel->dev, "failed to set display off: %d\n", ret);
+	mipi_dsi_dcs_set_display_off_multi(&dsi_ctx);
 
-	ret = mipi_dsi_dcs_enter_sleep_mode(dsi);
-	if (ret)
-		dev_warn(panel->dev, "failed to enter sleep mode: %d\n", ret);
+	/* Attempt to enter sleep mode even if display off failed. */
+	dsi_ctx.accum_err = 0;
+	mipi_dsi_dcs_enter_sleep_mode_multi(&dsi_ctx);
 
 	msleep(120);
 
@@ -258,6 +232,7 @@ static int rm68200_prepare(struct drm_panel *panel)
 {
 	struct rm68200 *ctx = panel_to_rm68200(panel);
 	struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
+	struct mipi_dsi_multi_context dsi_ctx = { .dsi = dsi };
 	int ret;
 
 	ret = regulator_enable(ctx->supply);
@@ -273,19 +248,18 @@ static int rm68200_prepare(struct drm_panel *panel)
 		msleep(100);
 	}
 
-	rm68200_init_sequence(ctx);
+	rm68200_init_sequence(&dsi_ctx);
 
-	ret = mipi_dsi_dcs_exit_sleep_mode(dsi);
-	if (ret)
-		goto assert_reset;
+	mipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx);
 
-	msleep(125);
+	mipi_dsi_msleep(&dsi_ctx, 125);
 
-	ret = mipi_dsi_dcs_set_display_on(dsi);
+	mipi_dsi_dcs_set_display_on_multi(&dsi_ctx);
+	ret = dsi_ctx.accum_err;
 	if (ret)
 		goto assert_reset;
 
-	msleep(20);
+	mipi_dsi_msleep(&dsi_ctx, 20);
 
 	return 0;
 
-- 
2.43.0

[PATCH v2 5/5] drm/panel: raydium-rm68200: Use lowercase hex literals

[Hsieh Hung-En]

Convert hexadecimal literals in the RM68200 register definitions and
initialization sequence to lowercase for consistency with the
preferred formatting convention.

This is a formatting-only change. Register addresses and command
data remain unchanged.

Suggested-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Hsieh Hung-En <hungen3108@gmail.com>
---

Notes:
    Changes in v2:
    - Add a separate patch to convert hexadecimal literals to lowercase,
      as suggested by Doug, keeping the _multi() conversion focused on
      functional changes.
    
    Validation:
    - Compared all 65 modified source lines after normalizing only the
      hexadecimal digits in literals. No other differences were found.
    - Confirmed that no uppercase hexadecimal literals remain.
    - Built the driver before and after the change using the same
      configuration. The .text, .rodata, .rodata.str1.8 and .data sections
      were byte-for-byte identical.
    - The build completed with W=1 and no warnings or errors.
      checkpatch reported no issues.

 drivers/gpu/drm/panel/panel-raydium-rm68200.c | 132 +++++++++---------
 1 file changed, 66 insertions(+), 66 deletions(-)

diff --git a/drivers/gpu/drm/panel/panel-raydium-rm68200.c b/drivers/gpu/drm/panel/panel-raydium-rm68200.c
index 8ce89f09540c..df99b6837057 100644
--- a/drivers/gpu/drm/panel/panel-raydium-rm68200.c
+++ b/drivers/gpu/drm/panel/panel-raydium-rm68200.c
@@ -18,7 +18,7 @@
 #include <drm/drm_panel.h>
 
 /*** Manufacturer Command Set ***/
-#define MCS_CMD_MODE_SW		0xFE /* CMD Mode Switch */
+#define MCS_CMD_MODE_SW		0xfe /* CMD Mode Switch */
 #define MCS_CMD1_UCS		0x00 /* User Command Set (UCS = CMD1) */
 #define MCS_CMD2_P0		0x01 /* Manufacture Command Set Page0 (CMD2 P0) */
 #define MCS_CMD2_P1		0x02 /* Manufacture Command Set Page1 (CMD2 P1) */
@@ -28,44 +28,44 @@
 /* CMD2 P0 commands (Display Options and Power) */
 #define MCS_STBCTR		0x12 /* TE1 Output Setting Zig-Zag Connection */
 #define MCS_SGOPCTR		0x16 /* Source Bias Current */
-#define MCS_SDCTR		0x1A /* Source Output Delay Time */
-#define MCS_INVCTR		0x1B /* Inversion Type */
+#define MCS_SDCTR		0x1a /* Source Output Delay Time */
+#define MCS_INVCTR		0x1b /* Inversion Type */
 #define MCS_EXT_PWR_IC		0x24 /* External PWR IC Control */
 #define MCS_SETAVDD		0x27 /* PFM Control for AVDD Output */
 #define MCS_SETAVEE		0x29 /* PFM Control for AVEE Output */
-#define MCS_BT2CTR		0x2B /* DDVDL Charge Pump Control */
-#define MCS_BT3CTR		0x2F /* VGH Charge Pump Control */
+#define MCS_BT2CTR		0x2b /* DDVDL Charge Pump Control */
+#define MCS_BT3CTR		0x2f /* VGH Charge Pump Control */
 #define MCS_BT4CTR		0x34 /* VGL Charge Pump Control */
 #define MCS_VCMCTR		0x46 /* VCOM Output Level Control */
 #define MCS_SETVGN		0x52 /* VG M/S N Control */
 #define MCS_SETVGP		0x54 /* VG M/S P Control */
-#define MCS_SW_CTRL		0x5F /* Interface Control for PFM and MIPI */
+#define MCS_SW_CTRL		0x5f /* Interface Control for PFM and MIPI */
 
 /* CMD2 P2 commands (GOA Timing Control) - no description in datasheet */
 #define GOA_VSTV1		0x00
 #define GOA_VSTV2		0x07
-#define GOA_VCLK1		0x0E
+#define GOA_VCLK1		0x0e
 #define GOA_VCLK2		0x17
 #define GOA_VCLK_OPT1		0x20
-#define GOA_BICLK1		0x2A
+#define GOA_BICLK1		0x2a
 #define GOA_BICLK2		0x37
 #define GOA_BICLK3		0x44
-#define GOA_BICLK4		0x4F
-#define GOA_BICLK_OPT1		0x5B
+#define GOA_BICLK4		0x4f
+#define GOA_BICLK_OPT1		0x5b
 #define GOA_BICLK_OPT2		0x60
-#define MCS_GOA_GPO1		0x6D
+#define MCS_GOA_GPO1		0x6d
 #define MCS_GOA_GPO2		0x71
 #define MCS_GOA_EQ		0x74
-#define MCS_GOA_CLK_GALLON	0x7C
-#define MCS_GOA_FS_SEL0		0x7E
+#define MCS_GOA_CLK_GALLON	0x7c
+#define MCS_GOA_FS_SEL0		0x7e
 #define MCS_GOA_FS_SEL1		0x87
 #define MCS_GOA_FS_SEL2		0x91
-#define MCS_GOA_FS_SEL3		0x9B
-#define MCS_GOA_BS_SEL0		0xAC
-#define MCS_GOA_BS_SEL1		0xB5
-#define MCS_GOA_BS_SEL2		0xBF
-#define MCS_GOA_BS_SEL3		0xC9
-#define MCS_GOA_BS_SEL4		0xD3
+#define MCS_GOA_FS_SEL3		0x9b
+#define MCS_GOA_BS_SEL0		0xac
+#define MCS_GOA_BS_SEL1		0xb5
+#define MCS_GOA_BS_SEL2		0xbf
+#define MCS_GOA_BS_SEL3		0xc9
+#define MCS_GOA_BS_SEL4		0xd3
 
 /* CMD2 P3 commands (Gamma) */
 #define MCS_GAMMA_VP		0x60 /* Gamma VP1~VP16 */
@@ -119,41 +119,41 @@ static void rm68200_init_sequence(struct mipi_dsi_multi_context *dsi_ctx)
 {
 	/* Enter CMD2 with page 0 */
 	mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_CMD_MODE_SW, MCS_CMD2_P0);
-	dcs_write_cmd_seq(dsi_ctx, MCS_EXT_PWR_IC, 0xC0, 0x53, 0x00);
-	mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_BT2CTR, 0xE5);
-	mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_SETAVDD, 0x0A);
-	mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_SETAVEE, 0x0A);
+	dcs_write_cmd_seq(dsi_ctx, MCS_EXT_PWR_IC, 0xc0, 0x53, 0x00);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_BT2CTR, 0xe5);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_SETAVDD, 0x0a);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_SETAVEE, 0x0a);
 	mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_SGOPCTR, 0x52);
 	mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_BT3CTR, 0x53);
-	mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_BT4CTR, 0x5A);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_BT4CTR, 0x5a);
 	mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_INVCTR, 0x00);
-	mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_STBCTR, 0x0A);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_STBCTR, 0x0a);
 	mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_SDCTR, 0x06);
 	mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_VCMCTR, 0x56);
-	mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_SETVGN, 0xA0, 0x00);
-	mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_SETVGP, 0xA0, 0x00);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_SETVGN, 0xa0, 0x00);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_SETVGP, 0xa0, 0x00);
 	mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_SW_CTRL, 0x11); /* 2 data lanes, see doc */
 
 	mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_CMD_MODE_SW, MCS_CMD2_P2);
 	mipi_dsi_dcs_write_seq_multi(dsi_ctx, GOA_VSTV1, 0x05);
-	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x02, 0x0B);
-	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x03, 0x0F);
-	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x04, 0x7D, 0x00, 0x50);
-	dcs_write_cmd_seq(dsi_ctx, GOA_VSTV2, 0x05, 0x16, 0x0D, 0x11, 0x7D, 0x00,
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x02, 0x0b);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x03, 0x0f);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x04, 0x7d, 0x00, 0x50);
+	dcs_write_cmd_seq(dsi_ctx, GOA_VSTV2, 0x05, 0x16, 0x0d, 0x11, 0x7d, 0x00,
 			  0x50);
-	dcs_write_cmd_seq(dsi_ctx, GOA_VCLK1, 0x07, 0x08, 0x01, 0x02, 0x00, 0x7D,
+	dcs_write_cmd_seq(dsi_ctx, GOA_VCLK1, 0x07, 0x08, 0x01, 0x02, 0x00, 0x7d,
 			  0x00, 0x85, 0x08);
-	dcs_write_cmd_seq(dsi_ctx, GOA_VCLK2, 0x03, 0x04, 0x05, 0x06, 0x00, 0x7D,
+	dcs_write_cmd_seq(dsi_ctx, GOA_VCLK2, 0x03, 0x04, 0x05, 0x06, 0x00, 0x7d,
 			  0x00, 0x85, 0x08);
 	mipi_dsi_dcs_write_seq_multi(dsi_ctx, GOA_VCLK_OPT1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 				     0x00, 0x00, 0x00, 0x00);
 	dcs_write_cmd_seq(dsi_ctx, GOA_BICLK1, 0x07, 0x08);
-	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x2D, 0x01);
-	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x2F, 0x02, 0x00, 0x40, 0x05, 0x08, 0x54, 0x7D,
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x2d, 0x01);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x2f, 0x02, 0x00, 0x40, 0x05, 0x08, 0x54, 0x7d,
 				     0x00);
 	dcs_write_cmd_seq(dsi_ctx, GOA_BICLK2, 0x03, 0x04, 0x05, 0x06, 0x00);
-	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x3D, 0x40);
-	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x3F, 0x05, 0x08, 0x54, 0x7D, 0x00);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x3d, 0x40);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x3f, 0x05, 0x08, 0x54, 0x7d, 0x00);
 	mipi_dsi_dcs_write_seq_multi(dsi_ctx, GOA_BICLK3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
 				     0x00, 0x00, 0x00, 0x00, 0x00);
 	mipi_dsi_dcs_write_seq_multi(dsi_ctx, GOA_BICLK4, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -167,38 +167,38 @@ static void rm68200_init_sequence(struct mipi_dsi_multi_context *dsi_ctx)
 	mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_GOA_EQ, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08,
 				     0x00, 0x00);
 	mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_GOA_CLK_GALLON, 0x00, 0x00);
-	dcs_write_cmd_seq(dsi_ctx, MCS_GOA_FS_SEL0, 0xBF, 0x02, 0x06, 0x14, 0x10,
-			  0x16, 0x12, 0x08, 0x3F);
-	dcs_write_cmd_seq(dsi_ctx, MCS_GOA_FS_SEL1, 0x3F, 0x3F, 0x3F, 0x3F, 0x0C,
-			  0x0A, 0x0E, 0x3F, 0x3F, 0x00);
-	dcs_write_cmd_seq(dsi_ctx, MCS_GOA_FS_SEL2, 0x04, 0x3F, 0x3F, 0x3F, 0x3F,
-			  0x05, 0x01, 0x3F, 0x3F, 0x0F);
-	dcs_write_cmd_seq(dsi_ctx, MCS_GOA_FS_SEL3, 0x0B, 0x0D, 0x3F, 0x3F, 0x3F,
-			  0x3F);
-	dcs_write_cmd_seq(dsi_ctx, 0xA2, 0x3F, 0x09, 0x13, 0x17, 0x11, 0x15);
-	dcs_write_cmd_seq(dsi_ctx, 0xA9, 0x07, 0x03, 0x3F);
-	dcs_write_cmd_seq(dsi_ctx, MCS_GOA_BS_SEL0, 0x3F, 0x05, 0x01, 0x17, 0x13,
-			  0x15, 0x11, 0x0F, 0x3F);
-	dcs_write_cmd_seq(dsi_ctx, MCS_GOA_BS_SEL1, 0x3F, 0x3F, 0x3F, 0x3F, 0x0B,
-			  0x0D, 0x09, 0x3F, 0x3F, 0x07);
-	dcs_write_cmd_seq(dsi_ctx, MCS_GOA_BS_SEL2, 0x03, 0x3F, 0x3F, 0x3F, 0x3F,
-			  0x02, 0x06, 0x3F, 0x3F, 0x08);
-	dcs_write_cmd_seq(dsi_ctx, MCS_GOA_BS_SEL3, 0x0C, 0x0A, 0x3F, 0x3F, 0x3F,
-			  0x3F, 0x3F, 0x0E, 0x10, 0x14);
-	dcs_write_cmd_seq(dsi_ctx, MCS_GOA_BS_SEL4, 0x12, 0x16, 0x00, 0x04, 0x3F);
-	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xDC, 0x02);
-	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xDE, 0x12);
-
-	mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_CMD_MODE_SW, 0x0E); /* No documentation */
+	dcs_write_cmd_seq(dsi_ctx, MCS_GOA_FS_SEL0, 0xbf, 0x02, 0x06, 0x14, 0x10,
+			  0x16, 0x12, 0x08, 0x3f);
+	dcs_write_cmd_seq(dsi_ctx, MCS_GOA_FS_SEL1, 0x3f, 0x3f, 0x3f, 0x3f, 0x0c,
+			  0x0a, 0x0e, 0x3f, 0x3f, 0x00);
+	dcs_write_cmd_seq(dsi_ctx, MCS_GOA_FS_SEL2, 0x04, 0x3f, 0x3f, 0x3f, 0x3f,
+			  0x05, 0x01, 0x3f, 0x3f, 0x0f);
+	dcs_write_cmd_seq(dsi_ctx, MCS_GOA_FS_SEL3, 0x0b, 0x0d, 0x3f, 0x3f, 0x3f,
+			  0x3f);
+	dcs_write_cmd_seq(dsi_ctx, 0xa2, 0x3f, 0x09, 0x13, 0x17, 0x11, 0x15);
+	dcs_write_cmd_seq(dsi_ctx, 0xa9, 0x07, 0x03, 0x3f);
+	dcs_write_cmd_seq(dsi_ctx, MCS_GOA_BS_SEL0, 0x3f, 0x05, 0x01, 0x17, 0x13,
+			  0x15, 0x11, 0x0f, 0x3f);
+	dcs_write_cmd_seq(dsi_ctx, MCS_GOA_BS_SEL1, 0x3f, 0x3f, 0x3f, 0x3f, 0x0b,
+			  0x0d, 0x09, 0x3f, 0x3f, 0x07);
+	dcs_write_cmd_seq(dsi_ctx, MCS_GOA_BS_SEL2, 0x03, 0x3f, 0x3f, 0x3f, 0x3f,
+			  0x02, 0x06, 0x3f, 0x3f, 0x08);
+	dcs_write_cmd_seq(dsi_ctx, MCS_GOA_BS_SEL3, 0x0c, 0x0a, 0x3f, 0x3f, 0x3f,
+			  0x3f, 0x3f, 0x0e, 0x10, 0x14);
+	dcs_write_cmd_seq(dsi_ctx, MCS_GOA_BS_SEL4, 0x12, 0x16, 0x00, 0x04, 0x3f);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xdc, 0x02);
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xde, 0x12);
+
+	mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_CMD_MODE_SW, 0x0e); /* No documentation */
 	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x01, 0x75);
 
 	mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_CMD_MODE_SW, MCS_CMD2_P3);
-	dcs_write_cmd_seq(dsi_ctx, MCS_GAMMA_VP, 0x00, 0x0C, 0x12, 0x0E, 0x06,
-			  0x12, 0x0E, 0x0B, 0x15, 0x0B, 0x10, 0x07, 0x0F,
-			  0x12, 0x0C, 0x00);
-	dcs_write_cmd_seq(dsi_ctx, MCS_GAMMA_VN, 0x00, 0x0C, 0x12, 0x0E, 0x06,
-			  0x12, 0x0E, 0x0B, 0x15, 0x0B, 0x10, 0x07, 0x0F,
-			  0x12, 0x0C, 0x00);
+	dcs_write_cmd_seq(dsi_ctx, MCS_GAMMA_VP, 0x00, 0x0c, 0x12, 0x0e, 0x06,
+			  0x12, 0x0e, 0x0b, 0x15, 0x0b, 0x10, 0x07, 0x0f,
+			  0x12, 0x0c, 0x00);
+	dcs_write_cmd_seq(dsi_ctx, MCS_GAMMA_VN, 0x00, 0x0c, 0x12, 0x0e, 0x06,
+			  0x12, 0x0e, 0x0b, 0x15, 0x0b, 0x10, 0x07, 0x0f,
+			  0x12, 0x0c, 0x00);
 
 	/* Exit CMD2 */
 	mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_CMD_MODE_SW, MCS_CMD1_UCS);
-- 
2.43.0

Re: [PATCH v2 1/5] drm/panel: feiyang-fy07024di26a30d: Fix prepare error cleanup

[neil.armstrong]

On 11/2/26 05:32, Hsieh Hung-En wrote:
> feiyang_prepare() returns without disabling previously enabled
> regulators if enabling AVDD or writing DCS commands fails. Since
> drm_panel_prepare() does not mark the panel as prepared on failure,
> drm_panel_unprepare() does not call the driver's unprepare() callback,
> leaving regulator enable counts elevated even after subsequent
> successful prepare/unprepare cycles.
> 
> Disable DVDD if enabling AVDD fails. On a DCS write failure, restore
> the reset GPIO to its unprepared state and disable both regulators,
> preserving the existing 10 ms power-off interval between AVDD and DVDD.
> 
> Fixes: 69dc678abc2b ("drm/panel: Add Feiyang FY07024DI26A30-D MIPI-DSI LCD panel")
> Reported-by: Douglas Anderson <dianders@chromium.org>
> Closes: https://lore.kernel.org/r/CAD=FV=Xm48DUT==8HuuGCSFZtLTEk-W2Q6UTfqt-MnM4nULzTw@mail.gmail.com
> Signed-off-by: Hsieh Hung-En <hungen3108@gmail.com>
> ---
> 
> Notes:
>      Power sequencing note:
>      
>      The error path retains the 10 ms AVDD-to-DVDD shutdown interval
>      used by unprepare().
>      
>      The FY07024DI26A30-D datasheet, Section 7.3 (Power, Signal sequence),
>      specifies T10 > 0 between AVDD/VGL reaching GND and DVDD starting
>      to fall. The delay allows time for AVDD to discharge before disabling
>      DVDD, but compliance with T10 has not been verified on hardware.
>      
>      The existing unprepare() comment associates the delay with T11,
>      which actually specifies the DVDD fall time (0 < T11 <= 10 ms).
>      That comment can be corrected separately.
>      
>      The msleep(10) checkpatch warning is expected. T10 has no specified
>      upper bound, so a longer sleep does not violate that timing constraint.
>      msleep() is retained to match the existing unprepare() sequence.
>      
>      Datasheet:
>      https://files.pine64.org/doc/datasheet/pine64/FY07024DI26A30-D_feiyang_LCD_panel.pdf
> 
>   .../gpu/drm/panel/panel-feiyang-fy07024di26a30d.c | 15 +++++++++++++--
>   1 file changed, 13 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/panel/panel-feiyang-fy07024di26a30d.c b/drivers/gpu/drm/panel/panel-feiyang-fy07024di26a30d.c
> index c1d8ca5ca6e1..bb4cc1ea2ece 100644
> --- a/drivers/gpu/drm/panel/panel-feiyang-fy07024di26a30d.c
> +++ b/drivers/gpu/drm/panel/panel-feiyang-fy07024di26a30d.c
> @@ -59,7 +59,7 @@ static int feiyang_prepare(struct drm_panel *panel)
>   
>   	ret = regulator_enable(ctx->avdd);
>   	if (ret)
> -		return ret;
> +		goto disable_dvdd;
>   
>   	/* T3 (dvdd rise + avdd start + avdd rise) T3 >= 20ms */
>   	msleep(20);
> @@ -84,10 +84,21 @@ static int feiyang_prepare(struct drm_panel *panel)
>   		ret = mipi_dsi_dcs_write_buffer(dsi, cmd->data,
>   						FEIYANG_INIT_CMD_LEN);
>   		if (ret < 0)
> -			return ret;
> +			goto assert_reset;
>   	}
>   
>   	return 0;
> +
> +assert_reset:
> +	gpiod_set_value(ctx->reset, 0);
> +	regulator_disable(ctx->avdd);
> +
> +	/* Preserve the AVDD-to-DVDD shutdown delay from unprepare(). */
> +	msleep(10);
> +
> +disable_dvdd:
> +	regulator_disable(ctx->dvdd);
> +	return ret;
>   }
>   
>   static int feiyang_enable(struct drm_panel *panel)

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>

Thanks,
Neil

Re: [PATCH v2 2/5] drm/panel: raydium-rm68200: Fix prepare error cleanup

[neil.armstrong]

On 11/2/26 05:32, Hsieh Hung-En wrote:
> rm68200_prepare() returns without disabling the supply regulator if
> EXIT_SLEEP_MODE or SET_DISPLAY_ON fails. Since drm_panel_prepare() does
> not mark the panel as prepared on failure, drm_panel_unprepare() does
> not call the driver's unprepare() callback, leaving the regulator
> enable count elevated even after subsequent successful
> prepare/unprepare cycles.
> 
> On failure, restore the reset GPIO to its unprepared state, following
> the existing reset sequence in unprepare(), and disable the supply
> regulator before returning the original error.
> 
> Fixes: 2b7ed18bed1a ("drm/panel: Add support for Raydium RM68200 panel driver")
> Reported-by: Sashiko <sashiko-bot@kernel.org>
> Closes: https://lore.kernel.org/r/sashiko-outbox-171393@kernel.org
> Signed-off-by: Hsieh Hung-En <hungen3108@gmail.com>
> ---
> 
> Notes:
>      In this patch, rm68200_init_sequence() still returns void and only
>      logs DCS write failures. These failures do not cause prepare() to
>      return early. A later patch in this series will propagate
>      initialization errors through prepare(), where this cleanup path
>      will also handle them.
>      
>      The error path does not send SET_DISPLAY_OFF or ENTER_SLEEP_MODE,
>      as DCS communication may already have failed. Instead, it follows
>      the existing reset and regulator shutdown sequence in unprepare().
> 
>   drivers/gpu/drm/panel/panel-raydium-rm68200.c | 13 +++++++++++--
>   1 file changed, 11 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/panel/panel-raydium-rm68200.c b/drivers/gpu/drm/panel/panel-raydium-rm68200.c
> index c535dc931903..3a59eb00274d 100644
> --- a/drivers/gpu/drm/panel/panel-raydium-rm68200.c
> +++ b/drivers/gpu/drm/panel/panel-raydium-rm68200.c
> @@ -277,17 +277,26 @@ static int rm68200_prepare(struct drm_panel *panel)
>   
>   	ret = mipi_dsi_dcs_exit_sleep_mode(dsi);
>   	if (ret)
> -		return ret;
> +		goto assert_reset;
>   
>   	msleep(125);
>   
>   	ret = mipi_dsi_dcs_set_display_on(dsi);
>   	if (ret)
> -		return ret;
> +		goto assert_reset;
>   
>   	msleep(20);
>   
>   	return 0;
> +
> +assert_reset:
> +	if (ctx->reset_gpio) {
> +		gpiod_set_value_cansleep(ctx->reset_gpio, 1);
> +		msleep(20);
> +	}
> +	/* Balance the regulator enable count on prepare failure. */
> +	regulator_disable(ctx->supply);
> +	return ret;
>   }
>   
>   static int rm68200_get_modes(struct drm_panel *panel,

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>

Thanks,
Neil

Re: [PATCH v2 3/5] drm/panel: feiyang-fy07024di26a30d: Use mipi_dsi_*_multi() functions

[neil.armstrong]

On 11/2/26 05:32, Hsieh Hung-En wrote:
> Replace the deprecated MIPI DSI DCS helpers with their _multi variants,
> as suggested in Documentation/gpu/todo.rst.
> 
> Replace the initialization command table and loop with seven direct
> mipi_dsi_dcs_write_seq_multi() calls. Preserve the original command
> order and values, using lowercase hexadecimal literals.
> 
> In prepare(), the first failed DCS write prevents subsequent transfers
> and its error is propagated through the cleanup path added by the
> preceding patch. The helpers also log command failures.
> 
> In unprepare(), clear accum_err between commands so that ENTER_SLEEP_MODE
> is still attempted if SET_DISPLAY_OFF fails, preserving the original
> error handling behavior.
> 
> In disable(), ignore SET_DISPLAY_OFF errors to allow drm_panel_disable()
> to clear panel->enabled, avoiding a stale enabled state after the panel
> is powered off. This follows commit 00efe8a68565 ("drm/panel:
> ronbo-rb070d30: Ignore DCS errors in disable()"). Command failures
> remain logged by the helper.
> 
> Signed-off-by: Hsieh Hung-En <hungen3108@gmail.com>
> ---
> 
> Notes:
>      Changes in v2:
>      - Replace the initialization command table with direct
>        mipi_dsi_dcs_write_seq_multi() calls, as suggested by Doug.
>      - Route initialization errors through the cleanup path added in 1/5.
>      - Convert initialization command values to lowercase hex.
>      - Drop the previous Reviewed-by tag due to the initialization rework.
>      
>      The seven initialization commands were checked against the original
>      table; their order and values are unchanged.
> 
>   .../drm/panel/panel-feiyang-fy07024di26a30d.c | 68 +++++++++----------
>   1 file changed, 33 insertions(+), 35 deletions(-)
> 
> diff --git a/drivers/gpu/drm/panel/panel-feiyang-fy07024di26a30d.c b/drivers/gpu/drm/panel/panel-feiyang-fy07024di26a30d.c
> index bb4cc1ea2ece..fa304eb7453b 100644
> --- a/drivers/gpu/drm/panel/panel-feiyang-fy07024di26a30d.c
> +++ b/drivers/gpu/drm/panel/panel-feiyang-fy07024di26a30d.c
> @@ -13,8 +13,6 @@
>   #include <linux/module.h>
>   #include <linux/regulator/consumer.h>
>   
> -#define FEIYANG_INIT_CMD_LEN	2
> -
>   struct feiyang {
>   	struct drm_panel	panel;
>   	struct mipi_dsi_device	*dsi;
> @@ -29,25 +27,21 @@ static inline struct feiyang *panel_to_feiyang(struct drm_panel *panel)
>   	return container_of(panel, struct feiyang, panel);
>   }
>   
> -struct feiyang_init_cmd {
> -	u8 data[FEIYANG_INIT_CMD_LEN];
> -};
> -
> -static const struct feiyang_init_cmd feiyang_init_cmds[] = {
> -	{ .data = { 0x80, 0x58 } },
> -	{ .data = { 0x81, 0x47 } },
> -	{ .data = { 0x82, 0xD4 } },
> -	{ .data = { 0x83, 0x88 } },
> -	{ .data = { 0x84, 0xA9 } },
> -	{ .data = { 0x85, 0xC3 } },
> -	{ .data = { 0x86, 0x82 } },
> -};
> +static void feiyang_init(struct mipi_dsi_multi_context *dsi_ctx)
> +{
> +	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x80, 0x58);
> +	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x81, 0x47);
> +	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x82, 0xd4);
> +	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x83, 0x88);
> +	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x84, 0xa9);
> +	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x85, 0xc3);
> +	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x86, 0x82);
> +}
>   
>   static int feiyang_prepare(struct drm_panel *panel)
>   {
>   	struct feiyang *ctx = panel_to_feiyang(panel);
> -	struct mipi_dsi_device *dsi = ctx->dsi;
> -	unsigned int i;
> +	struct mipi_dsi_multi_context dsi_ctx = { .dsi = ctx->dsi };
>   	int ret;
>   
>   	ret = regulator_enable(ctx->dvdd);
> @@ -77,15 +71,10 @@ static int feiyang_prepare(struct drm_panel *panel)
>   	/* T12 (video & logic signal rise + backlight rise) T12 >= 200ms */
>   	msleep(200);
>   
> -	for (i = 0; i < ARRAY_SIZE(feiyang_init_cmds); i++) {
> -		const struct feiyang_init_cmd *cmd =
> -						&feiyang_init_cmds[i];
> -
> -		ret = mipi_dsi_dcs_write_buffer(dsi, cmd->data,
> -						FEIYANG_INIT_CMD_LEN);
> -		if (ret < 0)
> -			goto assert_reset;
> -	}
> +	feiyang_init(&dsi_ctx);
> +	ret = dsi_ctx.accum_err;
> +	if (ret < 0)
> +		goto assert_reset;
>   
>   	return 0;
>   
> @@ -104,32 +93,41 @@ static int feiyang_prepare(struct drm_panel *panel)
>   static int feiyang_enable(struct drm_panel *panel)
>   {
>   	struct feiyang *ctx = panel_to_feiyang(panel);
> +	struct mipi_dsi_multi_context dsi_ctx = { .dsi = ctx->dsi };
>   
>   	/* T12 (video & logic signal rise + backlight rise) T12 >= 200ms */
>   	msleep(200);
>   
> -	return mipi_dsi_dcs_set_display_on(ctx->dsi);
> +	mipi_dsi_dcs_set_display_on_multi(&dsi_ctx);
> +
> +	return dsi_ctx.accum_err;
>   }
>   
>   static int feiyang_disable(struct drm_panel *panel)
>   {
>   	struct feiyang *ctx = panel_to_feiyang(panel);
> +	struct mipi_dsi_multi_context dsi_ctx = { .dsi = ctx->dsi };
> +
> +	mipi_dsi_dcs_set_display_off_multi(&dsi_ctx);
>   
> -	return mipi_dsi_dcs_set_display_off(ctx->dsi);
> +	/*
> +	 * Returning an error would leave panel->enabled set, causing the
> +	 * next enable to be skipped even after unprepare powers off the panel.
> +	 * The helper above already logs any command failure.
> +	 */
> +	return 0;
>   }
>   
>   static int feiyang_unprepare(struct drm_panel *panel)
>   {
>   	struct feiyang *ctx = panel_to_feiyang(panel);
> -	int ret;
> +	struct mipi_dsi_multi_context dsi_ctx = { .dsi = ctx->dsi };
>   
> -	ret = mipi_dsi_dcs_set_display_off(ctx->dsi);
> -	if (ret < 0)
> -		dev_err(panel->dev, "failed to set display off: %d\n", ret);
> +	mipi_dsi_dcs_set_display_off_multi(&dsi_ctx);
>   
> -	ret = mipi_dsi_dcs_enter_sleep_mode(ctx->dsi);
> -	if (ret < 0)
> -		dev_err(panel->dev, "failed to enter sleep mode: %d\n", ret);
> +	/* Attempt to enter sleep mode even if display off failed. */
> +	dsi_ctx.accum_err = 0;
> +	mipi_dsi_dcs_enter_sleep_mode_multi(&dsi_ctx);
>   
>   	/* T13 (backlight fall + video & logic signal fall) T13 >= 200ms */
>   	msleep(200);

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>

Thanks,
Neil

Re: [PATCH v2 4/5] drm/panel: raydium-rm68200: Use mipi_dsi_*_multi() functions

[neil.armstrong]

On 11/2/26 05:32, Hsieh Hung-En wrote:
> Replace the deprecated MIPI DSI DCS helpers and custom DCS write
> wrappers with their multi-context equivalents.
> 
> Preserve individual DCS transactions for registers that do not support
> auto-increment. Share the multi-context with rm68200_init_sequence()
> so that initialization failures stop subsequent DCS transfers and
> cause prepare() to fail instead of only being logged. Errors are
> handled by the cleanup path in prepare().
> 
> Use mipi_dsi_msleep() to skip delays after a failed command. In
> unprepare(), clear accum_err between commands so that ENTER_SLEEP_MODE
> is still attempted if SET_DISPLAY_OFF fails.
> 
> The new helpers log failures at error level. Initialization write
> errors are no longer rate-limited.
> 
> Signed-off-by: Hsieh Hung-En <hungen3108@gmail.com>
> ---
> 
> Notes:
>      Changes in v2:
>      - Merge v1 patches 2/3 and 3/3, as suggested by Doug.
>      - Route initialization and DCS command failures through the prepare()
>        error cleanup path introduced earlier in this series.
>      - Drop Doug's Reviewed-by tag from v1 3/3 because the patches were
>        merged and the error handling was reworked.
>      
>      Validation:
>      - Mechanically compared all 58 initialization calls against v1.
>        Command addresses, payloads, and ordering are unchanged.
>      - Verified the expansion of dcs_write_cmd_seq() in v1 using
>        preprocessed output, confirming that each register address is
>        written in a separate DCS transaction. The macro is unchanged
>        from v1.
>      
>      The uppercase hexadecimal literals are retained in this patch.
>      Their formatting will be addressed separately in the next patch.
> 
>   drivers/gpu/drm/panel/panel-raydium-rm68200.c | 208 ++++++++----------
>   1 file changed, 91 insertions(+), 117 deletions(-)
> 
> diff --git a/drivers/gpu/drm/panel/panel-raydium-rm68200.c b/drivers/gpu/drm/panel/panel-raydium-rm68200.c
> index 3a59eb00274d..8ce89f09540c 100644
> --- a/drivers/gpu/drm/panel/panel-raydium-rm68200.c
> +++ b/drivers/gpu/drm/panel/panel-raydium-rm68200.c
> @@ -98,149 +98,123 @@ static inline struct rm68200 *panel_to_rm68200(struct drm_panel *panel)
>   	return container_of(panel, struct rm68200, panel);
>   }
>   
> -static void rm68200_dcs_write_buf(struct rm68200 *ctx, const void *data,
> -				  size_t len)
> -{
> -	struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
> -	int err;
> -
> -	err = mipi_dsi_dcs_write_buffer(dsi, data, len);
> -	if (err < 0)
> -		dev_err_ratelimited(ctx->dev, "MIPI DSI DCS write buffer failed: %d\n", err);
> -}
> -
> -static void rm68200_dcs_write_cmd(struct rm68200 *ctx, u8 cmd, u8 value)
> -{
> -	struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
> -	int err;
> -
> -	err = mipi_dsi_dcs_write(dsi, cmd, &value, 1);
> -	if (err < 0)
> -		dev_err_ratelimited(ctx->dev, "MIPI DSI DCS write failed: %d\n", err);
> -}
> -
> -#define dcs_write_seq(ctx, seq...)				\
> -({								\
> -	static const u8 d[] = { seq };				\
> -								\
> -	rm68200_dcs_write_buf(ctx, d, ARRAY_SIZE(d));		\
> -})
> -
>   /*
>    * This panel is not able to auto-increment all cmd addresses so for some of
>    * them, we need to send them one by one...
> + *
> + * Use arr instead of d to avoid shadowing the local d[] declared by
> + * mipi_dsi_dcs_write_var_seq_multi().
>    */
> -#define dcs_write_cmd_seq(ctx, cmd, seq...)			\
> -({								\
> -	static const u8 d[] = { seq };				\
> -	unsigned int i;						\
> -								\
> -	for (i = 0; i < ARRAY_SIZE(d) ; i++)			\
> -		rm68200_dcs_write_cmd(ctx, cmd + i, d[i]);	\
> -})
> -
> -static void rm68200_init_sequence(struct rm68200 *ctx)
> +#define dcs_write_cmd_seq(dsi_ctx, cmd, seq...)			\
> +	do {								\
> +		static const u8 arr[] = { seq };			\
> +		unsigned int i;						\
> +									\
> +		for (i = 0; i < ARRAY_SIZE(arr); i++)		\
> +			mipi_dsi_dcs_write_var_seq_multi(dsi_ctx,	\
> +							(cmd) + i, arr[i]); \
> +	} while (0)
> +
> +static void rm68200_init_sequence(struct mipi_dsi_multi_context *dsi_ctx)
>   {
>   	/* Enter CMD2 with page 0 */
> -	dcs_write_seq(ctx, MCS_CMD_MODE_SW, MCS_CMD2_P0);
> -	dcs_write_cmd_seq(ctx, MCS_EXT_PWR_IC, 0xC0, 0x53, 0x00);
> -	dcs_write_seq(ctx, MCS_BT2CTR, 0xE5);
> -	dcs_write_seq(ctx, MCS_SETAVDD, 0x0A);
> -	dcs_write_seq(ctx, MCS_SETAVEE, 0x0A);
> -	dcs_write_seq(ctx, MCS_SGOPCTR, 0x52);
> -	dcs_write_seq(ctx, MCS_BT3CTR, 0x53);
> -	dcs_write_seq(ctx, MCS_BT4CTR, 0x5A);
> -	dcs_write_seq(ctx, MCS_INVCTR, 0x00);
> -	dcs_write_seq(ctx, MCS_STBCTR, 0x0A);
> -	dcs_write_seq(ctx, MCS_SDCTR, 0x06);
> -	dcs_write_seq(ctx, MCS_VCMCTR, 0x56);
> -	dcs_write_seq(ctx, MCS_SETVGN, 0xA0, 0x00);
> -	dcs_write_seq(ctx, MCS_SETVGP, 0xA0, 0x00);
> -	dcs_write_seq(ctx, MCS_SW_CTRL, 0x11); /* 2 data lanes, see doc */
> -
> -	dcs_write_seq(ctx, MCS_CMD_MODE_SW, MCS_CMD2_P2);
> -	dcs_write_seq(ctx, GOA_VSTV1, 0x05);
> -	dcs_write_seq(ctx, 0x02, 0x0B);
> -	dcs_write_seq(ctx, 0x03, 0x0F);
> -	dcs_write_seq(ctx, 0x04, 0x7D, 0x00, 0x50);
> -	dcs_write_cmd_seq(ctx, GOA_VSTV2, 0x05, 0x16, 0x0D, 0x11, 0x7D, 0x00,
> +	mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_CMD_MODE_SW, MCS_CMD2_P0);
> +	dcs_write_cmd_seq(dsi_ctx, MCS_EXT_PWR_IC, 0xC0, 0x53, 0x00);
> +	mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_BT2CTR, 0xE5);
> +	mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_SETAVDD, 0x0A);
> +	mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_SETAVEE, 0x0A);
> +	mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_SGOPCTR, 0x52);
> +	mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_BT3CTR, 0x53);
> +	mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_BT4CTR, 0x5A);
> +	mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_INVCTR, 0x00);
> +	mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_STBCTR, 0x0A);
> +	mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_SDCTR, 0x06);
> +	mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_VCMCTR, 0x56);
> +	mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_SETVGN, 0xA0, 0x00);
> +	mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_SETVGP, 0xA0, 0x00);
> +	mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_SW_CTRL, 0x11); /* 2 data lanes, see doc */
> +
> +	mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_CMD_MODE_SW, MCS_CMD2_P2);
> +	mipi_dsi_dcs_write_seq_multi(dsi_ctx, GOA_VSTV1, 0x05);
> +	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x02, 0x0B);
> +	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x03, 0x0F);
> +	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x04, 0x7D, 0x00, 0x50);
> +	dcs_write_cmd_seq(dsi_ctx, GOA_VSTV2, 0x05, 0x16, 0x0D, 0x11, 0x7D, 0x00,
>   			  0x50);
> -	dcs_write_cmd_seq(ctx, GOA_VCLK1, 0x07, 0x08, 0x01, 0x02, 0x00, 0x7D,
> +	dcs_write_cmd_seq(dsi_ctx, GOA_VCLK1, 0x07, 0x08, 0x01, 0x02, 0x00, 0x7D,
>   			  0x00, 0x85, 0x08);
> -	dcs_write_cmd_seq(ctx, GOA_VCLK2, 0x03, 0x04, 0x05, 0x06, 0x00, 0x7D,
> +	dcs_write_cmd_seq(dsi_ctx, GOA_VCLK2, 0x03, 0x04, 0x05, 0x06, 0x00, 0x7D,
>   			  0x00, 0x85, 0x08);
> -	dcs_write_seq(ctx, GOA_VCLK_OPT1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> -		      0x00, 0x00, 0x00, 0x00);
> -	dcs_write_cmd_seq(ctx, GOA_BICLK1, 0x07, 0x08);
> -	dcs_write_seq(ctx, 0x2D, 0x01);
> -	dcs_write_seq(ctx, 0x2F, 0x02, 0x00, 0x40, 0x05, 0x08, 0x54, 0x7D,
> -		      0x00);
> -	dcs_write_cmd_seq(ctx, GOA_BICLK2, 0x03, 0x04, 0x05, 0x06, 0x00);
> -	dcs_write_seq(ctx, 0x3D, 0x40);
> -	dcs_write_seq(ctx, 0x3F, 0x05, 0x08, 0x54, 0x7D, 0x00);
> -	dcs_write_seq(ctx, GOA_BICLK3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> -		      0x00, 0x00, 0x00, 0x00, 0x00);
> -	dcs_write_seq(ctx, GOA_BICLK4, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> -		      0x00, 0x00);
> -	dcs_write_seq(ctx, 0x58, 0x00, 0x00, 0x00);
> -	dcs_write_seq(ctx, GOA_BICLK_OPT1, 0x00, 0x00, 0x00, 0x00, 0x00);
> -	dcs_write_seq(ctx, GOA_BICLK_OPT2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> -		      0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00);
> -	dcs_write_seq(ctx, MCS_GOA_GPO1, 0x00, 0x00, 0x00, 0x00);
> -	dcs_write_seq(ctx, MCS_GOA_GPO2, 0x00, 0x20, 0x00);
> -	dcs_write_seq(ctx, MCS_GOA_EQ, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08,
> -		      0x00, 0x00);
> -	dcs_write_seq(ctx, MCS_GOA_CLK_GALLON, 0x00, 0x00);
> -	dcs_write_cmd_seq(ctx, MCS_GOA_FS_SEL0, 0xBF, 0x02, 0x06, 0x14, 0x10,
> +	mipi_dsi_dcs_write_seq_multi(dsi_ctx, GOA_VCLK_OPT1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> +				     0x00, 0x00, 0x00, 0x00);
> +	dcs_write_cmd_seq(dsi_ctx, GOA_BICLK1, 0x07, 0x08);
> +	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x2D, 0x01);
> +	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x2F, 0x02, 0x00, 0x40, 0x05, 0x08, 0x54, 0x7D,
> +				     0x00);
> +	dcs_write_cmd_seq(dsi_ctx, GOA_BICLK2, 0x03, 0x04, 0x05, 0x06, 0x00);
> +	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x3D, 0x40);
> +	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x3F, 0x05, 0x08, 0x54, 0x7D, 0x00);
> +	mipi_dsi_dcs_write_seq_multi(dsi_ctx, GOA_BICLK3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> +				     0x00, 0x00, 0x00, 0x00, 0x00);
> +	mipi_dsi_dcs_write_seq_multi(dsi_ctx, GOA_BICLK4, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> +				     0x00, 0x00);
> +	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x58, 0x00, 0x00, 0x00);
> +	mipi_dsi_dcs_write_seq_multi(dsi_ctx, GOA_BICLK_OPT1, 0x00, 0x00, 0x00, 0x00, 0x00);
> +	mipi_dsi_dcs_write_seq_multi(dsi_ctx, GOA_BICLK_OPT2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> +				     0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00);
> +	mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_GOA_GPO1, 0x00, 0x00, 0x00, 0x00);
> +	mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_GOA_GPO2, 0x00, 0x20, 0x00);
> +	mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_GOA_EQ, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08,
> +				     0x00, 0x00);
> +	mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_GOA_CLK_GALLON, 0x00, 0x00);
> +	dcs_write_cmd_seq(dsi_ctx, MCS_GOA_FS_SEL0, 0xBF, 0x02, 0x06, 0x14, 0x10,
>   			  0x16, 0x12, 0x08, 0x3F);
> -	dcs_write_cmd_seq(ctx, MCS_GOA_FS_SEL1, 0x3F, 0x3F, 0x3F, 0x3F, 0x0C,
> +	dcs_write_cmd_seq(dsi_ctx, MCS_GOA_FS_SEL1, 0x3F, 0x3F, 0x3F, 0x3F, 0x0C,
>   			  0x0A, 0x0E, 0x3F, 0x3F, 0x00);
> -	dcs_write_cmd_seq(ctx, MCS_GOA_FS_SEL2, 0x04, 0x3F, 0x3F, 0x3F, 0x3F,
> +	dcs_write_cmd_seq(dsi_ctx, MCS_GOA_FS_SEL2, 0x04, 0x3F, 0x3F, 0x3F, 0x3F,
>   			  0x05, 0x01, 0x3F, 0x3F, 0x0F);
> -	dcs_write_cmd_seq(ctx, MCS_GOA_FS_SEL3, 0x0B, 0x0D, 0x3F, 0x3F, 0x3F,
> +	dcs_write_cmd_seq(dsi_ctx, MCS_GOA_FS_SEL3, 0x0B, 0x0D, 0x3F, 0x3F, 0x3F,
>   			  0x3F);
> -	dcs_write_cmd_seq(ctx, 0xA2, 0x3F, 0x09, 0x13, 0x17, 0x11, 0x15);
> -	dcs_write_cmd_seq(ctx, 0xA9, 0x07, 0x03, 0x3F);
> -	dcs_write_cmd_seq(ctx, MCS_GOA_BS_SEL0, 0x3F, 0x05, 0x01, 0x17, 0x13,
> +	dcs_write_cmd_seq(dsi_ctx, 0xA2, 0x3F, 0x09, 0x13, 0x17, 0x11, 0x15);
> +	dcs_write_cmd_seq(dsi_ctx, 0xA9, 0x07, 0x03, 0x3F);
> +	dcs_write_cmd_seq(dsi_ctx, MCS_GOA_BS_SEL0, 0x3F, 0x05, 0x01, 0x17, 0x13,
>   			  0x15, 0x11, 0x0F, 0x3F);
> -	dcs_write_cmd_seq(ctx, MCS_GOA_BS_SEL1, 0x3F, 0x3F, 0x3F, 0x3F, 0x0B,
> +	dcs_write_cmd_seq(dsi_ctx, MCS_GOA_BS_SEL1, 0x3F, 0x3F, 0x3F, 0x3F, 0x0B,
>   			  0x0D, 0x09, 0x3F, 0x3F, 0x07);
> -	dcs_write_cmd_seq(ctx, MCS_GOA_BS_SEL2, 0x03, 0x3F, 0x3F, 0x3F, 0x3F,
> +	dcs_write_cmd_seq(dsi_ctx, MCS_GOA_BS_SEL2, 0x03, 0x3F, 0x3F, 0x3F, 0x3F,
>   			  0x02, 0x06, 0x3F, 0x3F, 0x08);
> -	dcs_write_cmd_seq(ctx, MCS_GOA_BS_SEL3, 0x0C, 0x0A, 0x3F, 0x3F, 0x3F,
> +	dcs_write_cmd_seq(dsi_ctx, MCS_GOA_BS_SEL3, 0x0C, 0x0A, 0x3F, 0x3F, 0x3F,
>   			  0x3F, 0x3F, 0x0E, 0x10, 0x14);
> -	dcs_write_cmd_seq(ctx, MCS_GOA_BS_SEL4, 0x12, 0x16, 0x00, 0x04, 0x3F);
> -	dcs_write_seq(ctx, 0xDC, 0x02);
> -	dcs_write_seq(ctx, 0xDE, 0x12);
> +	dcs_write_cmd_seq(dsi_ctx, MCS_GOA_BS_SEL4, 0x12, 0x16, 0x00, 0x04, 0x3F);
> +	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xDC, 0x02);
> +	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xDE, 0x12);
>   
> -	dcs_write_seq(ctx, MCS_CMD_MODE_SW, 0x0E); /* No documentation */
> -	dcs_write_seq(ctx, 0x01, 0x75);
> +	mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_CMD_MODE_SW, 0x0E); /* No documentation */
> +	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x01, 0x75);
>   
> -	dcs_write_seq(ctx, MCS_CMD_MODE_SW, MCS_CMD2_P3);
> -	dcs_write_cmd_seq(ctx, MCS_GAMMA_VP, 0x00, 0x0C, 0x12, 0x0E, 0x06,
> +	mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_CMD_MODE_SW, MCS_CMD2_P3);
> +	dcs_write_cmd_seq(dsi_ctx, MCS_GAMMA_VP, 0x00, 0x0C, 0x12, 0x0E, 0x06,
>   			  0x12, 0x0E, 0x0B, 0x15, 0x0B, 0x10, 0x07, 0x0F,
>   			  0x12, 0x0C, 0x00);
> -	dcs_write_cmd_seq(ctx, MCS_GAMMA_VN, 0x00, 0x0C, 0x12, 0x0E, 0x06,
> +	dcs_write_cmd_seq(dsi_ctx, MCS_GAMMA_VN, 0x00, 0x0C, 0x12, 0x0E, 0x06,
>   			  0x12, 0x0E, 0x0B, 0x15, 0x0B, 0x10, 0x07, 0x0F,
>   			  0x12, 0x0C, 0x00);
>   
>   	/* Exit CMD2 */
> -	dcs_write_seq(ctx, MCS_CMD_MODE_SW, MCS_CMD1_UCS);
> +	mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_CMD_MODE_SW, MCS_CMD1_UCS);
>   }
>   
>   static int rm68200_unprepare(struct drm_panel *panel)
>   {
>   	struct rm68200 *ctx = panel_to_rm68200(panel);
>   	struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
> -	int ret;
> +	struct mipi_dsi_multi_context dsi_ctx = { .dsi = dsi };
>   
> -	ret = mipi_dsi_dcs_set_display_off(dsi);
> -	if (ret)
> -		dev_warn(panel->dev, "failed to set display off: %d\n", ret);
> +	mipi_dsi_dcs_set_display_off_multi(&dsi_ctx);
>   
> -	ret = mipi_dsi_dcs_enter_sleep_mode(dsi);
> -	if (ret)
> -		dev_warn(panel->dev, "failed to enter sleep mode: %d\n", ret);
> +	/* Attempt to enter sleep mode even if display off failed. */
> +	dsi_ctx.accum_err = 0;
> +	mipi_dsi_dcs_enter_sleep_mode_multi(&dsi_ctx);
>   
>   	msleep(120);
>   
> @@ -258,6 +232,7 @@ static int rm68200_prepare(struct drm_panel *panel)
>   {
>   	struct rm68200 *ctx = panel_to_rm68200(panel);
>   	struct mipi_dsi_device *dsi = to_mipi_dsi_device(ctx->dev);
> +	struct mipi_dsi_multi_context dsi_ctx = { .dsi = dsi };
>   	int ret;
>   
>   	ret = regulator_enable(ctx->supply);
> @@ -273,19 +248,18 @@ static int rm68200_prepare(struct drm_panel *panel)
>   		msleep(100);
>   	}
>   
> -	rm68200_init_sequence(ctx);
> +	rm68200_init_sequence(&dsi_ctx);
>   
> -	ret = mipi_dsi_dcs_exit_sleep_mode(dsi);
> -	if (ret)
> -		goto assert_reset;
> +	mipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx);
>   
> -	msleep(125);
> +	mipi_dsi_msleep(&dsi_ctx, 125);
>   
> -	ret = mipi_dsi_dcs_set_display_on(dsi);
> +	mipi_dsi_dcs_set_display_on_multi(&dsi_ctx);
> +	ret = dsi_ctx.accum_err;
>   	if (ret)
>   		goto assert_reset;
>   
> -	msleep(20);
> +	mipi_dsi_msleep(&dsi_ctx, 20);
>   
>   	return 0;
>   

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>

Thanks,
Neil

Re: [PATCH v2 5/5] drm/panel: raydium-rm68200: Use lowercase hex literals

[neil.armstrong]

On 11/2/26 05:32, Hsieh Hung-En wrote:
> Convert hexadecimal literals in the RM68200 register definitions and
> initialization sequence to lowercase for consistency with the
> preferred formatting convention.
> 
> This is a formatting-only change. Register addresses and command
> data remain unchanged.
> 
> Suggested-by: Douglas Anderson <dianders@chromium.org>
> Signed-off-by: Hsieh Hung-En <hungen3108@gmail.com>
> ---
> 
> Notes:
>      Changes in v2:
>      - Add a separate patch to convert hexadecimal literals to lowercase,
>        as suggested by Doug, keeping the _multi() conversion focused on
>        functional changes.
>      
>      Validation:
>      - Compared all 65 modified source lines after normalizing only the
>        hexadecimal digits in literals. No other differences were found.
>      - Confirmed that no uppercase hexadecimal literals remain.
>      - Built the driver before and after the change using the same
>        configuration. The .text, .rodata, .rodata.str1.8 and .data sections
>        were byte-for-byte identical.
>      - The build completed with W=1 and no warnings or errors.
>        checkpatch reported no issues.
> 
>   drivers/gpu/drm/panel/panel-raydium-rm68200.c | 132 +++++++++---------
>   1 file changed, 66 insertions(+), 66 deletions(-)
> 
> diff --git a/drivers/gpu/drm/panel/panel-raydium-rm68200.c b/drivers/gpu/drm/panel/panel-raydium-rm68200.c
> index 8ce89f09540c..df99b6837057 100644
> --- a/drivers/gpu/drm/panel/panel-raydium-rm68200.c
> +++ b/drivers/gpu/drm/panel/panel-raydium-rm68200.c
> @@ -18,7 +18,7 @@
>   #include <drm/drm_panel.h>
>   
>   /*** Manufacturer Command Set ***/
> -#define MCS_CMD_MODE_SW		0xFE /* CMD Mode Switch */
> +#define MCS_CMD_MODE_SW		0xfe /* CMD Mode Switch */
>   #define MCS_CMD1_UCS		0x00 /* User Command Set (UCS = CMD1) */
>   #define MCS_CMD2_P0		0x01 /* Manufacture Command Set Page0 (CMD2 P0) */
>   #define MCS_CMD2_P1		0x02 /* Manufacture Command Set Page1 (CMD2 P1) */
> @@ -28,44 +28,44 @@
>   /* CMD2 P0 commands (Display Options and Power) */
>   #define MCS_STBCTR		0x12 /* TE1 Output Setting Zig-Zag Connection */
>   #define MCS_SGOPCTR		0x16 /* Source Bias Current */
> -#define MCS_SDCTR		0x1A /* Source Output Delay Time */
> -#define MCS_INVCTR		0x1B /* Inversion Type */
> +#define MCS_SDCTR		0x1a /* Source Output Delay Time */
> +#define MCS_INVCTR		0x1b /* Inversion Type */
>   #define MCS_EXT_PWR_IC		0x24 /* External PWR IC Control */
>   #define MCS_SETAVDD		0x27 /* PFM Control for AVDD Output */
>   #define MCS_SETAVEE		0x29 /* PFM Control for AVEE Output */
> -#define MCS_BT2CTR		0x2B /* DDVDL Charge Pump Control */
> -#define MCS_BT3CTR		0x2F /* VGH Charge Pump Control */
> +#define MCS_BT2CTR		0x2b /* DDVDL Charge Pump Control */
> +#define MCS_BT3CTR		0x2f /* VGH Charge Pump Control */
>   #define MCS_BT4CTR		0x34 /* VGL Charge Pump Control */
>   #define MCS_VCMCTR		0x46 /* VCOM Output Level Control */
>   #define MCS_SETVGN		0x52 /* VG M/S N Control */
>   #define MCS_SETVGP		0x54 /* VG M/S P Control */
> -#define MCS_SW_CTRL		0x5F /* Interface Control for PFM and MIPI */
> +#define MCS_SW_CTRL		0x5f /* Interface Control for PFM and MIPI */
>   
>   /* CMD2 P2 commands (GOA Timing Control) - no description in datasheet */
>   #define GOA_VSTV1		0x00
>   #define GOA_VSTV2		0x07
> -#define GOA_VCLK1		0x0E
> +#define GOA_VCLK1		0x0e
>   #define GOA_VCLK2		0x17
>   #define GOA_VCLK_OPT1		0x20
> -#define GOA_BICLK1		0x2A
> +#define GOA_BICLK1		0x2a
>   #define GOA_BICLK2		0x37
>   #define GOA_BICLK3		0x44
> -#define GOA_BICLK4		0x4F
> -#define GOA_BICLK_OPT1		0x5B
> +#define GOA_BICLK4		0x4f
> +#define GOA_BICLK_OPT1		0x5b
>   #define GOA_BICLK_OPT2		0x60
> -#define MCS_GOA_GPO1		0x6D
> +#define MCS_GOA_GPO1		0x6d
>   #define MCS_GOA_GPO2		0x71
>   #define MCS_GOA_EQ		0x74
> -#define MCS_GOA_CLK_GALLON	0x7C
> -#define MCS_GOA_FS_SEL0		0x7E
> +#define MCS_GOA_CLK_GALLON	0x7c
> +#define MCS_GOA_FS_SEL0		0x7e
>   #define MCS_GOA_FS_SEL1		0x87
>   #define MCS_GOA_FS_SEL2		0x91
> -#define MCS_GOA_FS_SEL3		0x9B
> -#define MCS_GOA_BS_SEL0		0xAC
> -#define MCS_GOA_BS_SEL1		0xB5
> -#define MCS_GOA_BS_SEL2		0xBF
> -#define MCS_GOA_BS_SEL3		0xC9
> -#define MCS_GOA_BS_SEL4		0xD3
> +#define MCS_GOA_FS_SEL3		0x9b
> +#define MCS_GOA_BS_SEL0		0xac
> +#define MCS_GOA_BS_SEL1		0xb5
> +#define MCS_GOA_BS_SEL2		0xbf
> +#define MCS_GOA_BS_SEL3		0xc9
> +#define MCS_GOA_BS_SEL4		0xd3
>   
>   /* CMD2 P3 commands (Gamma) */
>   #define MCS_GAMMA_VP		0x60 /* Gamma VP1~VP16 */
> @@ -119,41 +119,41 @@ static void rm68200_init_sequence(struct mipi_dsi_multi_context *dsi_ctx)
>   {
>   	/* Enter CMD2 with page 0 */
>   	mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_CMD_MODE_SW, MCS_CMD2_P0);
> -	dcs_write_cmd_seq(dsi_ctx, MCS_EXT_PWR_IC, 0xC0, 0x53, 0x00);
> -	mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_BT2CTR, 0xE5);
> -	mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_SETAVDD, 0x0A);
> -	mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_SETAVEE, 0x0A);
> +	dcs_write_cmd_seq(dsi_ctx, MCS_EXT_PWR_IC, 0xc0, 0x53, 0x00);
> +	mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_BT2CTR, 0xe5);
> +	mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_SETAVDD, 0x0a);
> +	mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_SETAVEE, 0x0a);
>   	mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_SGOPCTR, 0x52);
>   	mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_BT3CTR, 0x53);
> -	mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_BT4CTR, 0x5A);
> +	mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_BT4CTR, 0x5a);
>   	mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_INVCTR, 0x00);
> -	mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_STBCTR, 0x0A);
> +	mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_STBCTR, 0x0a);
>   	mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_SDCTR, 0x06);
>   	mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_VCMCTR, 0x56);
> -	mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_SETVGN, 0xA0, 0x00);
> -	mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_SETVGP, 0xA0, 0x00);
> +	mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_SETVGN, 0xa0, 0x00);
> +	mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_SETVGP, 0xa0, 0x00);
>   	mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_SW_CTRL, 0x11); /* 2 data lanes, see doc */
>   
>   	mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_CMD_MODE_SW, MCS_CMD2_P2);
>   	mipi_dsi_dcs_write_seq_multi(dsi_ctx, GOA_VSTV1, 0x05);
> -	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x02, 0x0B);
> -	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x03, 0x0F);
> -	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x04, 0x7D, 0x00, 0x50);
> -	dcs_write_cmd_seq(dsi_ctx, GOA_VSTV2, 0x05, 0x16, 0x0D, 0x11, 0x7D, 0x00,
> +	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x02, 0x0b);
> +	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x03, 0x0f);
> +	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x04, 0x7d, 0x00, 0x50);
> +	dcs_write_cmd_seq(dsi_ctx, GOA_VSTV2, 0x05, 0x16, 0x0d, 0x11, 0x7d, 0x00,
>   			  0x50);
> -	dcs_write_cmd_seq(dsi_ctx, GOA_VCLK1, 0x07, 0x08, 0x01, 0x02, 0x00, 0x7D,
> +	dcs_write_cmd_seq(dsi_ctx, GOA_VCLK1, 0x07, 0x08, 0x01, 0x02, 0x00, 0x7d,
>   			  0x00, 0x85, 0x08);
> -	dcs_write_cmd_seq(dsi_ctx, GOA_VCLK2, 0x03, 0x04, 0x05, 0x06, 0x00, 0x7D,
> +	dcs_write_cmd_seq(dsi_ctx, GOA_VCLK2, 0x03, 0x04, 0x05, 0x06, 0x00, 0x7d,
>   			  0x00, 0x85, 0x08);
>   	mipi_dsi_dcs_write_seq_multi(dsi_ctx, GOA_VCLK_OPT1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
>   				     0x00, 0x00, 0x00, 0x00);
>   	dcs_write_cmd_seq(dsi_ctx, GOA_BICLK1, 0x07, 0x08);
> -	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x2D, 0x01);
> -	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x2F, 0x02, 0x00, 0x40, 0x05, 0x08, 0x54, 0x7D,
> +	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x2d, 0x01);
> +	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x2f, 0x02, 0x00, 0x40, 0x05, 0x08, 0x54, 0x7d,
>   				     0x00);
>   	dcs_write_cmd_seq(dsi_ctx, GOA_BICLK2, 0x03, 0x04, 0x05, 0x06, 0x00);
> -	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x3D, 0x40);
> -	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x3F, 0x05, 0x08, 0x54, 0x7D, 0x00);
> +	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x3d, 0x40);
> +	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x3f, 0x05, 0x08, 0x54, 0x7d, 0x00);
>   	mipi_dsi_dcs_write_seq_multi(dsi_ctx, GOA_BICLK3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
>   				     0x00, 0x00, 0x00, 0x00, 0x00);
>   	mipi_dsi_dcs_write_seq_multi(dsi_ctx, GOA_BICLK4, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
> @@ -167,38 +167,38 @@ static void rm68200_init_sequence(struct mipi_dsi_multi_context *dsi_ctx)
>   	mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_GOA_EQ, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08,
>   				     0x00, 0x00);
>   	mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_GOA_CLK_GALLON, 0x00, 0x00);
> -	dcs_write_cmd_seq(dsi_ctx, MCS_GOA_FS_SEL0, 0xBF, 0x02, 0x06, 0x14, 0x10,
> -			  0x16, 0x12, 0x08, 0x3F);
> -	dcs_write_cmd_seq(dsi_ctx, MCS_GOA_FS_SEL1, 0x3F, 0x3F, 0x3F, 0x3F, 0x0C,
> -			  0x0A, 0x0E, 0x3F, 0x3F, 0x00);
> -	dcs_write_cmd_seq(dsi_ctx, MCS_GOA_FS_SEL2, 0x04, 0x3F, 0x3F, 0x3F, 0x3F,
> -			  0x05, 0x01, 0x3F, 0x3F, 0x0F);
> -	dcs_write_cmd_seq(dsi_ctx, MCS_GOA_FS_SEL3, 0x0B, 0x0D, 0x3F, 0x3F, 0x3F,
> -			  0x3F);
> -	dcs_write_cmd_seq(dsi_ctx, 0xA2, 0x3F, 0x09, 0x13, 0x17, 0x11, 0x15);
> -	dcs_write_cmd_seq(dsi_ctx, 0xA9, 0x07, 0x03, 0x3F);
> -	dcs_write_cmd_seq(dsi_ctx, MCS_GOA_BS_SEL0, 0x3F, 0x05, 0x01, 0x17, 0x13,
> -			  0x15, 0x11, 0x0F, 0x3F);
> -	dcs_write_cmd_seq(dsi_ctx, MCS_GOA_BS_SEL1, 0x3F, 0x3F, 0x3F, 0x3F, 0x0B,
> -			  0x0D, 0x09, 0x3F, 0x3F, 0x07);
> -	dcs_write_cmd_seq(dsi_ctx, MCS_GOA_BS_SEL2, 0x03, 0x3F, 0x3F, 0x3F, 0x3F,
> -			  0x02, 0x06, 0x3F, 0x3F, 0x08);
> -	dcs_write_cmd_seq(dsi_ctx, MCS_GOA_BS_SEL3, 0x0C, 0x0A, 0x3F, 0x3F, 0x3F,
> -			  0x3F, 0x3F, 0x0E, 0x10, 0x14);
> -	dcs_write_cmd_seq(dsi_ctx, MCS_GOA_BS_SEL4, 0x12, 0x16, 0x00, 0x04, 0x3F);
> -	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xDC, 0x02);
> -	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xDE, 0x12);
> -
> -	mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_CMD_MODE_SW, 0x0E); /* No documentation */
> +	dcs_write_cmd_seq(dsi_ctx, MCS_GOA_FS_SEL0, 0xbf, 0x02, 0x06, 0x14, 0x10,
> +			  0x16, 0x12, 0x08, 0x3f);
> +	dcs_write_cmd_seq(dsi_ctx, MCS_GOA_FS_SEL1, 0x3f, 0x3f, 0x3f, 0x3f, 0x0c,
> +			  0x0a, 0x0e, 0x3f, 0x3f, 0x00);
> +	dcs_write_cmd_seq(dsi_ctx, MCS_GOA_FS_SEL2, 0x04, 0x3f, 0x3f, 0x3f, 0x3f,
> +			  0x05, 0x01, 0x3f, 0x3f, 0x0f);
> +	dcs_write_cmd_seq(dsi_ctx, MCS_GOA_FS_SEL3, 0x0b, 0x0d, 0x3f, 0x3f, 0x3f,
> +			  0x3f);
> +	dcs_write_cmd_seq(dsi_ctx, 0xa2, 0x3f, 0x09, 0x13, 0x17, 0x11, 0x15);
> +	dcs_write_cmd_seq(dsi_ctx, 0xa9, 0x07, 0x03, 0x3f);
> +	dcs_write_cmd_seq(dsi_ctx, MCS_GOA_BS_SEL0, 0x3f, 0x05, 0x01, 0x17, 0x13,
> +			  0x15, 0x11, 0x0f, 0x3f);
> +	dcs_write_cmd_seq(dsi_ctx, MCS_GOA_BS_SEL1, 0x3f, 0x3f, 0x3f, 0x3f, 0x0b,
> +			  0x0d, 0x09, 0x3f, 0x3f, 0x07);
> +	dcs_write_cmd_seq(dsi_ctx, MCS_GOA_BS_SEL2, 0x03, 0x3f, 0x3f, 0x3f, 0x3f,
> +			  0x02, 0x06, 0x3f, 0x3f, 0x08);
> +	dcs_write_cmd_seq(dsi_ctx, MCS_GOA_BS_SEL3, 0x0c, 0x0a, 0x3f, 0x3f, 0x3f,
> +			  0x3f, 0x3f, 0x0e, 0x10, 0x14);
> +	dcs_write_cmd_seq(dsi_ctx, MCS_GOA_BS_SEL4, 0x12, 0x16, 0x00, 0x04, 0x3f);
> +	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xdc, 0x02);
> +	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0xde, 0x12);
> +
> +	mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_CMD_MODE_SW, 0x0e); /* No documentation */
>   	mipi_dsi_dcs_write_seq_multi(dsi_ctx, 0x01, 0x75);
>   
>   	mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_CMD_MODE_SW, MCS_CMD2_P3);
> -	dcs_write_cmd_seq(dsi_ctx, MCS_GAMMA_VP, 0x00, 0x0C, 0x12, 0x0E, 0x06,
> -			  0x12, 0x0E, 0x0B, 0x15, 0x0B, 0x10, 0x07, 0x0F,
> -			  0x12, 0x0C, 0x00);
> -	dcs_write_cmd_seq(dsi_ctx, MCS_GAMMA_VN, 0x00, 0x0C, 0x12, 0x0E, 0x06,
> -			  0x12, 0x0E, 0x0B, 0x15, 0x0B, 0x10, 0x07, 0x0F,
> -			  0x12, 0x0C, 0x00);
> +	dcs_write_cmd_seq(dsi_ctx, MCS_GAMMA_VP, 0x00, 0x0c, 0x12, 0x0e, 0x06,
> +			  0x12, 0x0e, 0x0b, 0x15, 0x0b, 0x10, 0x07, 0x0f,
> +			  0x12, 0x0c, 0x00);
> +	dcs_write_cmd_seq(dsi_ctx, MCS_GAMMA_VN, 0x00, 0x0c, 0x12, 0x0e, 0x06,
> +			  0x12, 0x0e, 0x0b, 0x15, 0x0b, 0x10, 0x07, 0x0f,
> +			  0x12, 0x0c, 0x00);
>   
>   	/* Exit CMD2 */
>   	mipi_dsi_dcs_write_seq_multi(dsi_ctx, MCS_CMD_MODE_SW, MCS_CMD1_UCS);

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>

Thanks,
Neil

Re: [PATCH v2 0/5] drm/panel: Use mipi_dsi_*_multi() in feiyang and rm68200

[Neil Armstrong]

Hi,

On Mon, 02 Nov 2026 12:32:10 +0800, Hsieh Hung-En wrote:
> This series converts the Feiyang FY07024DI26A30-D and Raydium RM68200
> panel drivers to the MIPI DSI multi-context helpers, as suggested in
> Documentation/gpu/todo.rst.
> 
> The first two patches fix pre-existing prepare() error paths that leave
> regulators enabled on failure. The following two patches convert the
> DCS helpers and initialization sequences, with command failures
> propagated through the cleanup paths. The final patch normalizes the
> RM68200 hexadecimal literals.
> 
> [...]

Thanks, Applied to https://gitlab.freedesktop.org/drm/misc/kernel.git (drm-misc-next)

[1/5] drm/panel: feiyang-fy07024di26a30d: Fix prepare error cleanup
      https://gitlab.freedesktop.org/drm/misc/kernel/-/commit/439e9dcfb3ba4980522cbb2c33eff5f9f321db64
[2/5] drm/panel: raydium-rm68200: Fix prepare error cleanup
      https://gitlab.freedesktop.org/drm/misc/kernel/-/commit/a1b23a5bc8567c16552e5e16cb6e9d59c54d262b
[3/5] drm/panel: feiyang-fy07024di26a30d: Use mipi_dsi_*_multi() functions
      https://gitlab.freedesktop.org/drm/misc/kernel/-/commit/6b84154cdc1a4ebc237b308640d2ecd67aa90cb6
[4/5] drm/panel: raydium-rm68200: Use mipi_dsi_*_multi() functions
      https://gitlab.freedesktop.org/drm/misc/kernel/-/commit/c8e7ae312688b05836376d11420bcaa4893053e6
[5/5] drm/panel: raydium-rm68200: Use lowercase hex literals
      https://gitlab.freedesktop.org/drm/misc/kernel/-/commit/57a2f4d7c90ba17a5bb84ce6741927e85896f413

-- 
Neil