[PATCH 0/8] clk: ath79: move the PLL clock driver to drivers/clk

[Rosen Penev <rosenp@gmail.com>]

The ath79 PLL clock code lives in arch/mips/ath79/clock.c and uses the
arch headers and ath79_reset_base. This series makes it a normal clk
driver in drivers/clk and then cleans it up.

Patches 1-2 remove what ties it to the arch code. The QCA956x timer
interrupt workaround moves to plat_time_init(), and so does reading the
reference clock rate from the bootstrap pins, for boards whose device
tree leaves the rate out. The arch code also warns when a rate in the
device tree disagrees with the pins.

Patch 3 moves the driver, with copies of the PLL register definitions it
uses, and adds a MAINTAINERS entry from the qca,ath79-pll binding. It
stays a CLK_OF_DECLARE driver, as the MIPS timer needs the CPU clock.

Patches 4-8 clean it up:
- 4: use GENMASK() and FIELD_GET() for the register fields (the
  generated code is unchanged)
- 5: convert to clk_hw. This also fixes the AR724x and AR933x clocks,
  whose parent was looked up by the name "ref", so they were orphans
  when the device tree's reference clock node has a different name.
- 6: fix the error handling: an unchecked ioremap(), clk_put() of an
  error pointer, and panics or BUG_ON() where an error return will do
- 7: one init function per compatible instead of re-matching it
- 8: share the fractional PLL calculation, using 64-bit maths. This
  fixes a 32-bit overflow of the QCA955x DDR PLL rate whenever its
  NFRAC is above 107 with a 40 MHz reference clock, or above 171 with
  25 MHz.

The series touches both arch/mips and drivers/clk. Patches 3-8 depend on
1-2, so it would be easiest to take it all through one tree with an ack
from the other maintainer.

Not addressed: the QCA956x PLL formula. It ignores the NFRAC_H field
("hfrac >> 13" of a 13-bit field is always 0) and divides NFRAC_L by
25 << 13 instead of 2^18. Mainline U-Boot has the same code, so it is
no independent check. I left it unchanged until it can be checked
against register values from a QCA956x board.

Tool use, per Documentation/process/generated-content.rst: this series
was developed with Claude Code (Claude Opus 5.5). It wrote most of the
code changes and changelogs in patches 3-8, following my review of the
driver and my requests, and reviewed patches 1-2. It also wrote the
user space harness used to test patch 8, and it fetched and compared
the U-Boot sources for the QCA956x formula. I reviewed and tested all
of it and take responsibility for it.

Rosen Penev (8):
  MIPS: ath79: apply the QCA956x timer workaround in setup
  MIPS: ath79: move the bootstrap reference clock to setup
  clk: ath79: move the ath79 clock driver to drivers/clk
  clk: ath79: use FIELD_GET() for the PLL register fields
  clk: ath79: convert to clk_hw based registration
  clk: ath79: fix the error handling
  clk: ath79: give each compatible its own init function
  clk: ath79: share the fractional PLL calculation

 MAINTAINERS              |   8 +
 arch/mips/ath79/Makefile |   2 +-
 arch/mips/ath79/clock.c  | 673 ---------------------------------------
 arch/mips/ath79/setup.c  | 100 ++++++
 drivers/clk/Kconfig      |  12 +
 drivers/clk/Makefile     |   1 +
 drivers/clk/clk-ath79.c  | 593 ++++++++++++++++++++++++++++++++++
 drivers/clk/clk-ath79.h  | 140 ++++++++
 8 files changed, 855 insertions(+), 674 deletions(-)
 delete mode 100644 arch/mips/ath79/clock.c
 create mode 100644 drivers/clk/clk-ath79.c
 create mode 100644 drivers/clk/clk-ath79.h


base-commit: d6bcfc94eb4da6e089c5473970cd96727292fd97
-- 
2.56.0