From: Rosen Penev <rosenp@gmail.com>
To: linux-mips@vger.kernel.org,
Thomas Bogendoerfer <tsbogend@alpha.franken.de>,
Stephen Boyd <sboyd@kernel.org>
Cc: Brian Masney <bmasney+clk@redhat.com>,
Jerome Brunet <jbrunet+clk@baylibre.com>,
Alban Bedel <albeu@free.fr>,
Antony Pavlov <antonynpavlov@gmail.com>,
linux-kernel@vger.kernel.org (open list),
linux-clk@vger.kernel.org (open list:COMMON CLK FRAMEWORK)
Subject: [PATCH 7/8] clk: ath79: give each compatible its own init function
Date: Tue, 3 Nov 2026 21:58:51 -0800 [thread overview]
Message-ID: <20261104055852.152340-8-rosenp@gmail.com> (raw)
In-Reply-To: <20261104055852.152340-1-rosenp@gmail.com>
Every compatible already has its own CLK_OF_DECLARE(), yet they all
shared one init function, which then matched the compatible again to
pick the SoC code. Have each CLK_OF_DECLARE() call a small wrapper
that passes the SoC init function to the common code instead.
Signed-off-by: Rosen Penev <rosenp@gmail.com>
---
drivers/clk/clk-ath79.c | 72 +++++++++++++++++++++++++++--------------
1 file changed, 47 insertions(+), 25 deletions(-)
diff --git a/drivers/clk/clk-ath79.c b/drivers/clk/clk-ath79.c
index 768c9e410b59..8086b4f6378c 100644
--- a/drivers/clk/clk-ath79.c
+++ b/drivers/clk/clk-ath79.c
@@ -504,11 +504,12 @@ static int __init qca956x_clocks_init(void __iomem *pll_base)
return ath79_set_clks(cpu_rate, ddr_rate, ahb_rate);
}
-static void __init ath79_clocks_init_dt(struct device_node *np)
+static void __init ath79_clocks_init_dt(struct device_node *np,
+ int (*soc_init)(void __iomem *pll_base))
{
struct clk *ref_clk;
void __iomem *pll_base;
- int ret = -ENODEV;
+ int ret;
clk_data = kzalloc_flex(*clk_data, hws, ATH79_CLK_END);
if (!clk_data)
@@ -534,21 +535,7 @@ static void __init ath79_clocks_init_dt(struct device_node *np)
goto err_clk;
}
- if (of_device_is_compatible(np, "qca,ar7100-pll"))
- ret = ar71xx_clocks_init(pll_base);
- else if (of_device_is_compatible(np, "qca,ar7240-pll") ||
- of_device_is_compatible(np, "qca,ar9130-pll"))
- ret = ar724x_clocks_init(pll_base);
- else if (of_device_is_compatible(np, "qca,ar9330-pll"))
- ret = ar933x_clocks_init(pll_base);
- else if (of_device_is_compatible(np, "qca,ar9340-pll"))
- ret = ar934x_clocks_init(pll_base);
- else if (of_device_is_compatible(np, "qca,qca9530-pll"))
- ret = qca953x_clocks_init(pll_base);
- else if (of_device_is_compatible(np, "qca,qca9550-pll"))
- ret = qca955x_clocks_init(pll_base);
- else if (of_device_is_compatible(np, "qca,qca9560-pll"))
- ret = qca956x_clocks_init(pll_base);
+ ret = soc_init(pll_base);
/* the rates are fixed, so the registers aren't needed any more */
iounmap(pll_base);
@@ -578,11 +565,46 @@ static void __init ath79_clocks_init_dt(struct device_node *np)
clk_data = NULL;
}
-CLK_OF_DECLARE(ar7100_clk, "qca,ar7100-pll", ath79_clocks_init_dt);
-CLK_OF_DECLARE(ar7240_clk, "qca,ar7240-pll", ath79_clocks_init_dt);
-CLK_OF_DECLARE(ar9130_clk, "qca,ar9130-pll", ath79_clocks_init_dt);
-CLK_OF_DECLARE(ar9330_clk, "qca,ar9330-pll", ath79_clocks_init_dt);
-CLK_OF_DECLARE(ar9340_clk, "qca,ar9340-pll", ath79_clocks_init_dt);
-CLK_OF_DECLARE(ar9530_clk, "qca,qca9530-pll", ath79_clocks_init_dt);
-CLK_OF_DECLARE(ar9550_clk, "qca,qca9550-pll", ath79_clocks_init_dt);
-CLK_OF_DECLARE(ar9560_clk, "qca,qca9560-pll", ath79_clocks_init_dt);
+static void __init ar71xx_clocks_init_dt(struct device_node *np)
+{
+ ath79_clocks_init_dt(np, ar71xx_clocks_init);
+}
+
+static void __init ar724x_clocks_init_dt(struct device_node *np)
+{
+ ath79_clocks_init_dt(np, ar724x_clocks_init);
+}
+
+static void __init ar933x_clocks_init_dt(struct device_node *np)
+{
+ ath79_clocks_init_dt(np, ar933x_clocks_init);
+}
+
+static void __init ar934x_clocks_init_dt(struct device_node *np)
+{
+ ath79_clocks_init_dt(np, ar934x_clocks_init);
+}
+
+static void __init qca953x_clocks_init_dt(struct device_node *np)
+{
+ ath79_clocks_init_dt(np, qca953x_clocks_init);
+}
+
+static void __init qca955x_clocks_init_dt(struct device_node *np)
+{
+ ath79_clocks_init_dt(np, qca955x_clocks_init);
+}
+
+static void __init qca956x_clocks_init_dt(struct device_node *np)
+{
+ ath79_clocks_init_dt(np, qca956x_clocks_init);
+}
+
+CLK_OF_DECLARE(ar7100_clk, "qca,ar7100-pll", ar71xx_clocks_init_dt);
+CLK_OF_DECLARE(ar7240_clk, "qca,ar7240-pll", ar724x_clocks_init_dt);
+CLK_OF_DECLARE(ar9130_clk, "qca,ar9130-pll", ar724x_clocks_init_dt);
+CLK_OF_DECLARE(ar9330_clk, "qca,ar9330-pll", ar933x_clocks_init_dt);
+CLK_OF_DECLARE(ar9340_clk, "qca,ar9340-pll", ar934x_clocks_init_dt);
+CLK_OF_DECLARE(ar9530_clk, "qca,qca9530-pll", qca953x_clocks_init_dt);
+CLK_OF_DECLARE(ar9550_clk, "qca,qca9550-pll", qca955x_clocks_init_dt);
+CLK_OF_DECLARE(ar9560_clk, "qca,qca9560-pll", qca956x_clocks_init_dt);
--
2.56.0
next prev parent reply other threads:[~2026-11-04 5:59 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-11-04 5:58 [PATCH 0/8] clk: ath79: move the PLL clock driver to drivers/clk Rosen Penev
2026-11-04 5:58 ` [PATCH 1/8] MIPS: ath79: apply the QCA956x timer workaround in setup Rosen Penev
2026-11-04 5:58 ` [PATCH 2/8] MIPS: ath79: move the bootstrap reference clock to setup Rosen Penev
2026-11-04 5:58 ` [PATCH 3/8] clk: ath79: move the ath79 clock driver to drivers/clk Rosen Penev
2026-11-04 5:58 ` [PATCH 4/8] clk: ath79: use FIELD_GET() for the PLL register fields Rosen Penev
2026-11-04 5:58 ` [PATCH 5/8] clk: ath79: convert to clk_hw based registration Rosen Penev
2026-11-04 5:58 ` [PATCH 6/8] clk: ath79: fix the error handling Rosen Penev
2026-11-04 5:58 ` Rosen Penev [this message]
2026-11-04 5:58 ` [PATCH 8/8] clk: ath79: share the fractional PLL calculation Rosen Penev
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