[PATCH 5/8] clk: ath79: convert to clk_hw based registration

[Rosen Penev <rosenp@gmail.com>]

Register the clocks with the clk_hw API and provide them with
of_clk_add_hw_provider() and of_clk_hw_onecell_get(), instead of the
struct clk based clk_register_*() and of_clk_src_onecell_get().

The AR724x and AR933x CPU, DDR and AHB clocks are fixed factors of the
reference clock, but named their parent "ref". That only works when the
reference clock is registered under that name, as the fallback from the
bootstrap pins is, or a device tree fixed clock whose node happens to be
called "ref". With any other node name, the clocks were orphans and ran
at 0 Hz. Give them the reference clock's clk_hw as the parent instead.

Signed-off-by: Rosen Penev <rosenp@gmail.com>
---
 drivers/clk/clk-ath79.c | 68 ++++++++++++++++++++++-------------------
 1 file changed, 36 insertions(+), 32 deletions(-)

diff --git a/drivers/clk/clk-ath79.c b/drivers/clk/clk-ath79.c
index 8279d58be318..3afda29377b5 100644
--- a/drivers/clk/clk-ath79.c
+++ b/drivers/clk/clk-ath79.c
@@ -18,17 +18,14 @@
 #include <linux/clk-provider.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
+#include <linux/slab.h>
 #include <dt-bindings/clock/ath79-clk.h>
 
 #include <asm/div64.h>
 
 #include "clk-ath79.h"
 
-static struct clk *clks[ATH79_CLK_END];
-static struct clk_onecell_data clk_data = {
-	.clks = clks,
-	.clk_num = ARRAY_SIZE(clks),
-};
+static struct clk_hw_onecell_data *clk_data;
 
 static const char * const clk_names[ATH79_CLK_END] = {
 	[ATH79_CLK_CPU] = "cpu",
@@ -44,42 +41,44 @@ static const char * __init ath79_clk_name(int type)
 	return clk_names[type];
 }
 
-static void __init __ath79_set_clk(int type, const char *name, struct clk *clk)
+static void __init __ath79_set_clk(int type, const char *name,
+				   struct clk_hw *hw)
 {
-	if (IS_ERR(clk))
+	if (IS_ERR(hw))
 		panic("failed to allocate %s clock structure", clk_names[type]);
 
-	clks[type] = clk;
-	clk_register_clkdev(clk, name, NULL);
+	clk_data->hws[type] = hw;
+	clk_hw_register_clkdev(hw, name, NULL);
 }
 
-static struct clk * __init ath79_set_clk(int type, unsigned long rate)
+static void __init ath79_set_clk(int type, unsigned long rate)
 {
 	const char *name = ath79_clk_name(type);
-	struct clk *clk;
+	struct clk_hw *hw;
 
-	clk = clk_register_fixed_rate(NULL, name, NULL, 0, rate);
-	__ath79_set_clk(type, name, clk);
-	return clk;
+	hw = clk_hw_register_fixed_rate(NULL, name, NULL, 0, rate);
+	__ath79_set_clk(type, name, hw);
 }
 
-static struct clk * __init ath79_set_ff_clk(int type, const char *parent,
-					    unsigned int mult, unsigned int div)
+/* a clock derived from the reference clock by a fixed factor */
+static void __init ath79_set_ff_clk(int type, unsigned int mult,
+				    unsigned int div)
 {
 	const char *name = ath79_clk_name(type);
-	struct clk *clk;
+	struct clk_hw *hw;
 
-	clk = clk_register_fixed_factor(NULL, name, parent, 0, mult, div);
-	__ath79_set_clk(type, name, clk);
-	return clk;
+	hw = clk_hw_register_fixed_factor_parent_hw(NULL, name,
+						    clk_data->hws[ATH79_CLK_REF],
+						    0, mult, div);
+	__ath79_set_clk(type, name, hw);
 }
 
 static unsigned long __init ath79_get_ref_rate(void)
 {
-	if (!clks[ATH79_CLK_REF])
+	if (!clk_data->hws[ATH79_CLK_REF])
 		panic("ath79: no reference clock");
 
-	return clk_get_rate(clks[ATH79_CLK_REF]);
+	return clk_hw_get_rate(clk_data->hws[ATH79_CLK_REF]);
 }
 
 static void __init ar71xx_clocks_init(void __iomem *pll_base)
@@ -128,9 +127,9 @@ static void __init ar724x_clocks_init(void __iomem *pll_base)
 	ddr_div = FIELD_GET(AR724X_DDR_DIV, pll) + 1;
 	ahb_div = (FIELD_GET(AR724X_AHB_DIV, pll) + 1) * 2;
 
-	ath79_set_ff_clk(ATH79_CLK_CPU, "ref", mult, div);
-	ath79_set_ff_clk(ATH79_CLK_DDR, "ref", mult, div * ddr_div);
-	ath79_set_ff_clk(ATH79_CLK_AHB, "ref", mult, div * ahb_div);
+	ath79_set_ff_clk(ATH79_CLK_CPU, mult, div);
+	ath79_set_ff_clk(ATH79_CLK_DDR, mult, div * ddr_div);
+	ath79_set_ff_clk(ATH79_CLK_AHB, mult, div * ahb_div);
 }
 
 static void __init ar933x_clocks_init(void __iomem *pll_base)
@@ -175,11 +174,11 @@ static void __init ar933x_clocks_init(void __iomem *pll_base)
 		ahb_div = FIELD_GET(AR933X_PLL_CLOCK_CTRL_AHB_DIV, clock_ctrl) + 1;
 	}
 
-	ath79_set_ff_clk(ATH79_CLK_CPU, "ref", ninit_mul,
+	ath79_set_ff_clk(ATH79_CLK_CPU, ninit_mul,
 			 ref_div * out_div * cpu_div);
-	ath79_set_ff_clk(ATH79_CLK_DDR, "ref", ninit_mul,
+	ath79_set_ff_clk(ATH79_CLK_DDR, ninit_mul,
 			 ref_div * out_div * ddr_div);
-	ath79_set_ff_clk(ATH79_CLK_AHB, "ref", ninit_mul,
+	ath79_set_ff_clk(ATH79_CLK_AHB, ninit_mul,
 			 ref_div * out_div * ahb_div);
 }
 
@@ -504,6 +503,11 @@ static void __init ath79_clocks_init_dt(struct device_node *np)
 	struct clk *ref_clk;
 	void __iomem *pll_base;
 
+	clk_data = kzalloc_flex(*clk_data, hws, ATH79_CLK_END);
+	if (!clk_data)
+		panic("ath79: can't allocate the clock data");
+	clk_data->num = ATH79_CLK_END;
+
 	/*
 	 * The board's crystal. Without a rate in the device tree, the arch
 	 * code registers it from the bootstrap pins.
@@ -512,7 +516,7 @@ static void __init ath79_clocks_init_dt(struct device_node *np)
 	if (IS_ERR(ref_clk))
 		ref_clk = clk_get_sys(NULL, "ref");
 	if (!IS_ERR(ref_clk))
-		clks[ATH79_CLK_REF] = ref_clk;
+		clk_data->hws[ATH79_CLK_REF] = __clk_get_hw(ref_clk);
 
 	pll_base = of_iomap(np, 0);
 	if (!pll_base) {
@@ -536,10 +540,10 @@ static void __init ath79_clocks_init_dt(struct device_node *np)
 	else if (of_device_is_compatible(np, "qca,qca9560-pll"))
 		qca956x_clocks_init(pll_base);
 
-	if (!clks[ATH79_CLK_MDIO])
-		clks[ATH79_CLK_MDIO] = clks[ATH79_CLK_REF];
+	if (!clk_data->hws[ATH79_CLK_MDIO])
+		clk_data->hws[ATH79_CLK_MDIO] = clk_data->hws[ATH79_CLK_REF];
 
-	if (of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data)) {
+	if (of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data)) {
 		pr_err("%pOF: could not register clk provider\n", np);
 		goto err_iounmap;
 	}
-- 
2.56.0