From: Rosen Penev <rosenp@gmail.com>
To: linux-mips@vger.kernel.org,
Thomas Bogendoerfer <tsbogend@alpha.franken.de>,
Stephen Boyd <sboyd@kernel.org>
Cc: Brian Masney <bmasney+clk@redhat.com>,
Jerome Brunet <jbrunet+clk@baylibre.com>,
Alban Bedel <albeu@free.fr>,
Antony Pavlov <antonynpavlov@gmail.com>,
linux-kernel@vger.kernel.org (open list),
linux-clk@vger.kernel.org (open list:COMMON CLK FRAMEWORK)
Subject: [PATCH 4/8] clk: ath79: use FIELD_GET() for the PLL register fields
Date: Tue, 3 Nov 2026 21:58:48 -0800 [thread overview]
Message-ID: <20261104055852.152340-5-rosenp@gmail.com> (raw)
In-Reply-To: <20261104055852.152340-1-rosenp@gmail.com>
Describe the PLL and SRIF register fields with GENMASK() instead of
separate _SHIFT and _MASK pairs, and extract them with FIELD_GET()
instead of open-coded shifts and masks.
No functional change: the generated code is the same, apart from a
register allocation swap in ar933x_clocks_init().
Signed-off-by: Rosen Penev <rosenp@gmail.com>
---
drivers/clk/clk-ath79.c | 199 +++++++++++---------------------
drivers/clk/clk-ath79.h | 246 ++++++++++++++++------------------------
2 files changed, 165 insertions(+), 280 deletions(-)
diff --git a/drivers/clk/clk-ath79.c b/drivers/clk/clk-ath79.c
index c5da404c9c48..8279d58be318 100644
--- a/drivers/clk/clk-ath79.c
+++ b/drivers/clk/clk-ath79.c
@@ -8,6 +8,7 @@
* Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
*/
+#include <linux/bitfield.h>
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/io.h>
@@ -95,16 +96,16 @@ static void __init ar71xx_clocks_init(void __iomem *pll_base)
pll = __raw_readl(pll_base + AR71XX_PLL_REG_CPU_CONFIG);
- div = ((pll >> AR71XX_PLL_FB_SHIFT) & AR71XX_PLL_FB_MASK) + 1;
+ div = FIELD_GET(AR71XX_PLL_FB, pll) + 1;
freq = div * ref_rate;
- div = ((pll >> AR71XX_CPU_DIV_SHIFT) & AR71XX_CPU_DIV_MASK) + 1;
+ div = FIELD_GET(AR71XX_CPU_DIV, pll) + 1;
cpu_rate = freq / div;
- div = ((pll >> AR71XX_DDR_DIV_SHIFT) & AR71XX_DDR_DIV_MASK) + 1;
+ div = FIELD_GET(AR71XX_DDR_DIV, pll) + 1;
ddr_rate = freq / div;
- div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2;
+ div = (FIELD_GET(AR71XX_AHB_DIV, pll) + 1) * 2;
ahb_rate = cpu_rate / div;
ath79_set_clk(ATH79_CLK_CPU, cpu_rate);
@@ -121,11 +122,11 @@ static void __init ar724x_clocks_init(void __iomem *pll_base)
pll = __raw_readl(pll_base + AR724X_PLL_REG_CPU_CONFIG);
- mult = ((pll >> AR724X_PLL_FB_SHIFT) & AR724X_PLL_FB_MASK);
- div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK) * 2;
+ mult = FIELD_GET(AR724X_PLL_FB, pll);
+ div = FIELD_GET(AR724X_PLL_REF_DIV, pll) * 2;
- ddr_div = ((pll >> AR724X_DDR_DIV_SHIFT) & AR724X_DDR_DIV_MASK) + 1;
- ahb_div = (((pll >> AR724X_AHB_DIV_SHIFT) & AR724X_AHB_DIV_MASK) + 1) * 2;
+ ddr_div = FIELD_GET(AR724X_DDR_DIV, pll) + 1;
+ ahb_div = (FIELD_GET(AR724X_AHB_DIV, pll) + 1) * 2;
ath79_set_ff_clk(ATH79_CLK_CPU, "ref", mult, div);
ath79_set_ff_clk(ATH79_CLK_DDR, "ref", mult, div * ddr_div);
@@ -160,28 +161,18 @@ static void __init ar933x_clocks_init(void __iomem *pll_base)
cpu_config = __raw_readl(pll_base + AR933X_PLL_CPU_CONFIG_REG);
- t = (cpu_config >> AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
- AR933X_PLL_CPU_CONFIG_REFDIV_MASK;
- ref_div = t;
+ ref_div = FIELD_GET(AR933X_PLL_CPU_CONFIG_REFDIV, cpu_config);
+ ninit_mul = FIELD_GET(AR933X_PLL_CPU_CONFIG_NINT, cpu_config);
- ninit_mul = (cpu_config >> AR933X_PLL_CPU_CONFIG_NINT_SHIFT) &
- AR933X_PLL_CPU_CONFIG_NINT_MASK;
-
- t = (cpu_config >> AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
- AR933X_PLL_CPU_CONFIG_OUTDIV_MASK;
+ t = FIELD_GET(AR933X_PLL_CPU_CONFIG_OUTDIV, cpu_config);
if (t == 0)
t = 1;
out_div = (1 << t);
- cpu_div = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT) &
- AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK) + 1;
-
- ddr_div = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT) &
- AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK) + 1;
-
- ahb_div = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT) &
- AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK) + 1;
+ cpu_div = FIELD_GET(AR933X_PLL_CLOCK_CTRL_CPU_DIV, clock_ctrl) + 1;
+ ddr_div = FIELD_GET(AR933X_PLL_CLOCK_CTRL_DDR_DIV, clock_ctrl) + 1;
+ ahb_div = FIELD_GET(AR933X_PLL_CLOCK_CTRL_AHB_DIV, clock_ctrl) + 1;
}
ath79_set_ff_clk(ATH79_CLK_CPU, "ref", ninit_mul,
@@ -228,25 +219,18 @@ static void __init ar934x_clocks_init(void __iomem *pll_base)
pll = __raw_readl(dpll_base + AR934X_SRIF_CPU_DPLL2_REG);
if (pll & AR934X_SRIF_DPLL2_LOCAL_PLL) {
- out_div = (pll >> AR934X_SRIF_DPLL2_OUTDIV_SHIFT) &
- AR934X_SRIF_DPLL2_OUTDIV_MASK;
+ out_div = FIELD_GET(AR934X_SRIF_DPLL2_OUTDIV, pll);
pll = __raw_readl(dpll_base + AR934X_SRIF_CPU_DPLL1_REG);
- nint = (pll >> AR934X_SRIF_DPLL1_NINT_SHIFT) &
- AR934X_SRIF_DPLL1_NINT_MASK;
- nfrac = pll & AR934X_SRIF_DPLL1_NFRAC_MASK;
- ref_div = (pll >> AR934X_SRIF_DPLL1_REFDIV_SHIFT) &
- AR934X_SRIF_DPLL1_REFDIV_MASK;
+ nint = FIELD_GET(AR934X_SRIF_DPLL1_NINT, pll);
+ nfrac = FIELD_GET(AR934X_SRIF_DPLL1_NFRAC, pll);
+ ref_div = FIELD_GET(AR934X_SRIF_DPLL1_REFDIV, pll);
frac = 1 << 18;
} else {
pll = __raw_readl(pll_base + AR934X_PLL_CPU_CONFIG_REG);
- out_div = (pll >> AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
- AR934X_PLL_CPU_CONFIG_OUTDIV_MASK;
- ref_div = (pll >> AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
- AR934X_PLL_CPU_CONFIG_REFDIV_MASK;
- nint = (pll >> AR934X_PLL_CPU_CONFIG_NINT_SHIFT) &
- AR934X_PLL_CPU_CONFIG_NINT_MASK;
- nfrac = (pll >> AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
- AR934X_PLL_CPU_CONFIG_NFRAC_MASK;
+ out_div = FIELD_GET(AR934X_PLL_CPU_CONFIG_OUTDIV, pll);
+ ref_div = FIELD_GET(AR934X_PLL_CPU_CONFIG_REFDIV, pll);
+ nint = FIELD_GET(AR934X_PLL_CPU_CONFIG_NINT, pll);
+ nfrac = FIELD_GET(AR934X_PLL_CPU_CONFIG_NFRAC, pll);
frac = 1 << 6;
}
@@ -255,25 +239,18 @@ static void __init ar934x_clocks_init(void __iomem *pll_base)
pll = __raw_readl(dpll_base + AR934X_SRIF_DDR_DPLL2_REG);
if (pll & AR934X_SRIF_DPLL2_LOCAL_PLL) {
- out_div = (pll >> AR934X_SRIF_DPLL2_OUTDIV_SHIFT) &
- AR934X_SRIF_DPLL2_OUTDIV_MASK;
+ out_div = FIELD_GET(AR934X_SRIF_DPLL2_OUTDIV, pll);
pll = __raw_readl(dpll_base + AR934X_SRIF_DDR_DPLL1_REG);
- nint = (pll >> AR934X_SRIF_DPLL1_NINT_SHIFT) &
- AR934X_SRIF_DPLL1_NINT_MASK;
- nfrac = pll & AR934X_SRIF_DPLL1_NFRAC_MASK;
- ref_div = (pll >> AR934X_SRIF_DPLL1_REFDIV_SHIFT) &
- AR934X_SRIF_DPLL1_REFDIV_MASK;
+ nint = FIELD_GET(AR934X_SRIF_DPLL1_NINT, pll);
+ nfrac = FIELD_GET(AR934X_SRIF_DPLL1_NFRAC, pll);
+ ref_div = FIELD_GET(AR934X_SRIF_DPLL1_REFDIV, pll);
frac = 1 << 18;
} else {
pll = __raw_readl(pll_base + AR934X_PLL_DDR_CONFIG_REG);
- out_div = (pll >> AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
- AR934X_PLL_DDR_CONFIG_OUTDIV_MASK;
- ref_div = (pll >> AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
- AR934X_PLL_DDR_CONFIG_REFDIV_MASK;
- nint = (pll >> AR934X_PLL_DDR_CONFIG_NINT_SHIFT) &
- AR934X_PLL_DDR_CONFIG_NINT_MASK;
- nfrac = (pll >> AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
- AR934X_PLL_DDR_CONFIG_NFRAC_MASK;
+ out_div = FIELD_GET(AR934X_PLL_DDR_CONFIG_OUTDIV, pll);
+ ref_div = FIELD_GET(AR934X_PLL_DDR_CONFIG_REFDIV, pll);
+ nint = FIELD_GET(AR934X_PLL_DDR_CONFIG_NINT, pll);
+ nfrac = FIELD_GET(AR934X_PLL_DDR_CONFIG_NFRAC, pll);
frac = 1 << 10;
}
@@ -282,8 +259,7 @@ static void __init ar934x_clocks_init(void __iomem *pll_base)
clk_ctrl = __raw_readl(pll_base + AR934X_PLL_CPU_DDR_CLK_CTRL_REG);
- postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT) &
- AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK;
+ postdiv = FIELD_GET(AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV, clk_ctrl);
if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS)
cpu_rate = ref_rate;
@@ -292,8 +268,7 @@ static void __init ar934x_clocks_init(void __iomem *pll_base)
else
cpu_rate = ddr_pll / (postdiv + 1);
- postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT) &
- AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK;
+ postdiv = FIELD_GET(AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV, clk_ctrl);
if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS)
ddr_rate = ref_rate;
@@ -302,8 +277,7 @@ static void __init ar934x_clocks_init(void __iomem *pll_base)
else
ddr_rate = cpu_pll / (postdiv + 1);
- postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT) &
- AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK;
+ postdiv = FIELD_GET(AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV, clk_ctrl);
if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS)
ahb_rate = ref_rate;
@@ -335,28 +309,20 @@ static void __init qca953x_clocks_init(void __iomem *pll_base)
ref_rate = ath79_get_ref_rate();
pll = __raw_readl(pll_base + QCA953X_PLL_CPU_CONFIG_REG);
- out_div = (pll >> QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
- QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK;
- ref_div = (pll >> QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
- QCA953X_PLL_CPU_CONFIG_REFDIV_MASK;
- nint = (pll >> QCA953X_PLL_CPU_CONFIG_NINT_SHIFT) &
- QCA953X_PLL_CPU_CONFIG_NINT_MASK;
- frac = (pll >> QCA953X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
- QCA953X_PLL_CPU_CONFIG_NFRAC_MASK;
+ out_div = FIELD_GET(QCA953X_PLL_CPU_CONFIG_OUTDIV, pll);
+ ref_div = FIELD_GET(QCA953X_PLL_CPU_CONFIG_REFDIV, pll);
+ nint = FIELD_GET(QCA953X_PLL_CPU_CONFIG_NINT, pll);
+ frac = FIELD_GET(QCA953X_PLL_CPU_CONFIG_NFRAC, pll);
cpu_pll = nint * ref_rate / ref_div;
cpu_pll += frac * (ref_rate >> 6) / ref_div;
cpu_pll /= (1 << out_div);
pll = __raw_readl(pll_base + QCA953X_PLL_DDR_CONFIG_REG);
- out_div = (pll >> QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
- QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK;
- ref_div = (pll >> QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
- QCA953X_PLL_DDR_CONFIG_REFDIV_MASK;
- nint = (pll >> QCA953X_PLL_DDR_CONFIG_NINT_SHIFT) &
- QCA953X_PLL_DDR_CONFIG_NINT_MASK;
- frac = (pll >> QCA953X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
- QCA953X_PLL_DDR_CONFIG_NFRAC_MASK;
+ out_div = FIELD_GET(QCA953X_PLL_DDR_CONFIG_OUTDIV, pll);
+ ref_div = FIELD_GET(QCA953X_PLL_DDR_CONFIG_REFDIV, pll);
+ nint = FIELD_GET(QCA953X_PLL_DDR_CONFIG_NINT, pll);
+ frac = FIELD_GET(QCA953X_PLL_DDR_CONFIG_NFRAC, pll);
ddr_pll = nint * ref_rate / ref_div;
ddr_pll += frac * (ref_rate >> 6) / (ref_div << 4);
@@ -364,8 +330,7 @@ static void __init qca953x_clocks_init(void __iomem *pll_base)
clk_ctrl = __raw_readl(pll_base + QCA953X_PLL_CLK_CTRL_REG);
- postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
- QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
+ postdiv = FIELD_GET(QCA953X_PLL_CLK_CTRL_CPU_POST_DIV, clk_ctrl);
if (clk_ctrl & QCA953X_PLL_CLK_CTRL_CPU_PLL_BYPASS)
cpu_rate = ref_rate;
@@ -374,8 +339,7 @@ static void __init qca953x_clocks_init(void __iomem *pll_base)
else
cpu_rate = ddr_pll / (postdiv + 1);
- postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) &
- QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_MASK;
+ postdiv = FIELD_GET(QCA953X_PLL_CLK_CTRL_DDR_POST_DIV, clk_ctrl);
if (clk_ctrl & QCA953X_PLL_CLK_CTRL_DDR_PLL_BYPASS)
ddr_rate = ref_rate;
@@ -384,8 +348,7 @@ static void __init qca953x_clocks_init(void __iomem *pll_base)
else
ddr_rate = cpu_pll / (postdiv + 1);
- postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) &
- QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_MASK;
+ postdiv = FIELD_GET(QCA953X_PLL_CLK_CTRL_AHB_POST_DIV, clk_ctrl);
if (clk_ctrl & QCA953X_PLL_CLK_CTRL_AHB_PLL_BYPASS)
ahb_rate = ref_rate;
@@ -411,28 +374,20 @@ static void __init qca955x_clocks_init(void __iomem *pll_base)
ref_rate = ath79_get_ref_rate();
pll = __raw_readl(pll_base + QCA955X_PLL_CPU_CONFIG_REG);
- out_div = (pll >> QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
- QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK;
- ref_div = (pll >> QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
- QCA955X_PLL_CPU_CONFIG_REFDIV_MASK;
- nint = (pll >> QCA955X_PLL_CPU_CONFIG_NINT_SHIFT) &
- QCA955X_PLL_CPU_CONFIG_NINT_MASK;
- frac = (pll >> QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
- QCA955X_PLL_CPU_CONFIG_NFRAC_MASK;
+ out_div = FIELD_GET(QCA955X_PLL_CPU_CONFIG_OUTDIV, pll);
+ ref_div = FIELD_GET(QCA955X_PLL_CPU_CONFIG_REFDIV, pll);
+ nint = FIELD_GET(QCA955X_PLL_CPU_CONFIG_NINT, pll);
+ frac = FIELD_GET(QCA955X_PLL_CPU_CONFIG_NFRAC, pll);
cpu_pll = nint * ref_rate / ref_div;
cpu_pll += frac * ref_rate / (ref_div * (1 << 6));
cpu_pll /= (1 << out_div);
pll = __raw_readl(pll_base + QCA955X_PLL_DDR_CONFIG_REG);
- out_div = (pll >> QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
- QCA955X_PLL_DDR_CONFIG_OUTDIV_MASK;
- ref_div = (pll >> QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
- QCA955X_PLL_DDR_CONFIG_REFDIV_MASK;
- nint = (pll >> QCA955X_PLL_DDR_CONFIG_NINT_SHIFT) &
- QCA955X_PLL_DDR_CONFIG_NINT_MASK;
- frac = (pll >> QCA955X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
- QCA955X_PLL_DDR_CONFIG_NFRAC_MASK;
+ out_div = FIELD_GET(QCA955X_PLL_DDR_CONFIG_OUTDIV, pll);
+ ref_div = FIELD_GET(QCA955X_PLL_DDR_CONFIG_REFDIV, pll);
+ nint = FIELD_GET(QCA955X_PLL_DDR_CONFIG_NINT, pll);
+ frac = FIELD_GET(QCA955X_PLL_DDR_CONFIG_NFRAC, pll);
ddr_pll = nint * ref_rate / ref_div;
ddr_pll += frac * ref_rate / (ref_div * (1 << 10));
@@ -440,8 +395,7 @@ static void __init qca955x_clocks_init(void __iomem *pll_base)
clk_ctrl = __raw_readl(pll_base + QCA955X_PLL_CLK_CTRL_REG);
- postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
- QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
+ postdiv = FIELD_GET(QCA955X_PLL_CLK_CTRL_CPU_POST_DIV, clk_ctrl);
if (clk_ctrl & QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS)
cpu_rate = ref_rate;
@@ -450,8 +404,7 @@ static void __init qca955x_clocks_init(void __iomem *pll_base)
else
cpu_rate = cpu_pll / (postdiv + 1);
- postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) &
- QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_MASK;
+ postdiv = FIELD_GET(QCA955X_PLL_CLK_CTRL_DDR_POST_DIV, clk_ctrl);
if (clk_ctrl & QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS)
ddr_rate = ref_rate;
@@ -460,8 +413,7 @@ static void __init qca955x_clocks_init(void __iomem *pll_base)
else
ddr_rate = ddr_pll / (postdiv + 1);
- postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) &
- QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_MASK;
+ postdiv = FIELD_GET(QCA955X_PLL_CLK_CTRL_AHB_POST_DIV, clk_ctrl);
if (clk_ctrl & QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS)
ahb_rate = ref_rate;
@@ -487,18 +439,13 @@ static void __init qca956x_clocks_init(void __iomem *pll_base)
ref_rate = ath79_get_ref_rate();
pll = __raw_readl(pll_base + QCA956X_PLL_CPU_CONFIG_REG);
- out_div = (pll >> QCA956X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
- QCA956X_PLL_CPU_CONFIG_OUTDIV_MASK;
- ref_div = (pll >> QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
- QCA956X_PLL_CPU_CONFIG_REFDIV_MASK;
+ out_div = FIELD_GET(QCA956X_PLL_CPU_CONFIG_OUTDIV, pll);
+ ref_div = FIELD_GET(QCA956X_PLL_CPU_CONFIG_REFDIV, pll);
pll = __raw_readl(pll_base + QCA956X_PLL_CPU_CONFIG1_REG);
- nint = (pll >> QCA956X_PLL_CPU_CONFIG1_NINT_SHIFT) &
- QCA956X_PLL_CPU_CONFIG1_NINT_MASK;
- hfrac = (pll >> QCA956X_PLL_CPU_CONFIG1_NFRAC_H_SHIFT) &
- QCA956X_PLL_CPU_CONFIG1_NFRAC_H_MASK;
- lfrac = (pll >> QCA956X_PLL_CPU_CONFIG1_NFRAC_L_SHIFT) &
- QCA956X_PLL_CPU_CONFIG1_NFRAC_L_MASK;
+ nint = FIELD_GET(QCA956X_PLL_CPU_CONFIG1_NINT, pll);
+ hfrac = FIELD_GET(QCA956X_PLL_CPU_CONFIG1_NFRAC_H, pll);
+ lfrac = FIELD_GET(QCA956X_PLL_CPU_CONFIG1_NFRAC_L, pll);
cpu_pll = nint * ref_rate / ref_div;
cpu_pll += (lfrac * ref_rate) / ((ref_div * 25) << 13);
@@ -506,17 +453,12 @@ static void __init qca956x_clocks_init(void __iomem *pll_base)
cpu_pll /= (1 << out_div);
pll = __raw_readl(pll_base + QCA956X_PLL_DDR_CONFIG_REG);
- out_div = (pll >> QCA956X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
- QCA956X_PLL_DDR_CONFIG_OUTDIV_MASK;
- ref_div = (pll >> QCA956X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
- QCA956X_PLL_DDR_CONFIG_REFDIV_MASK;
+ out_div = FIELD_GET(QCA956X_PLL_DDR_CONFIG_OUTDIV, pll);
+ ref_div = FIELD_GET(QCA956X_PLL_DDR_CONFIG_REFDIV, pll);
pll = __raw_readl(pll_base + QCA956X_PLL_DDR_CONFIG1_REG);
- nint = (pll >> QCA956X_PLL_DDR_CONFIG1_NINT_SHIFT) &
- QCA956X_PLL_DDR_CONFIG1_NINT_MASK;
- hfrac = (pll >> QCA956X_PLL_DDR_CONFIG1_NFRAC_H_SHIFT) &
- QCA956X_PLL_DDR_CONFIG1_NFRAC_H_MASK;
- lfrac = (pll >> QCA956X_PLL_DDR_CONFIG1_NFRAC_L_SHIFT) &
- QCA956X_PLL_DDR_CONFIG1_NFRAC_L_MASK;
+ nint = FIELD_GET(QCA956X_PLL_DDR_CONFIG1_NINT, pll);
+ hfrac = FIELD_GET(QCA956X_PLL_DDR_CONFIG1_NFRAC_H, pll);
+ lfrac = FIELD_GET(QCA956X_PLL_DDR_CONFIG1_NFRAC_L, pll);
ddr_pll = nint * ref_rate / ref_div;
ddr_pll += (lfrac * ref_rate) / ((ref_div * 25) << 13);
@@ -525,8 +467,7 @@ static void __init qca956x_clocks_init(void __iomem *pll_base)
clk_ctrl = __raw_readl(pll_base + QCA956X_PLL_CLK_CTRL_REG);
- postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
- QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
+ postdiv = FIELD_GET(QCA956X_PLL_CLK_CTRL_CPU_POST_DIV, clk_ctrl);
if (clk_ctrl & QCA956X_PLL_CLK_CTRL_CPU_PLL_BYPASS)
cpu_rate = ref_rate;
@@ -535,8 +476,7 @@ static void __init qca956x_clocks_init(void __iomem *pll_base)
else
cpu_rate = cpu_pll / (postdiv + 1);
- postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) &
- QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_MASK;
+ postdiv = FIELD_GET(QCA956X_PLL_CLK_CTRL_DDR_POST_DIV, clk_ctrl);
if (clk_ctrl & QCA956X_PLL_CLK_CTRL_DDR_PLL_BYPASS)
ddr_rate = ref_rate;
@@ -545,8 +485,7 @@ static void __init qca956x_clocks_init(void __iomem *pll_base)
else
ddr_rate = ddr_pll / (postdiv + 1);
- postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) &
- QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_MASK;
+ postdiv = FIELD_GET(QCA956X_PLL_CLK_CTRL_AHB_POST_DIV, clk_ctrl);
if (clk_ctrl & QCA956X_PLL_CLK_CTRL_AHB_PLL_BYPASS)
ahb_rate = ref_rate;
diff --git a/drivers/clk/clk-ath79.h b/drivers/clk/clk-ath79.h
index 12d7488eb5d2..dbff1b813562 100644
--- a/drivers/clk/clk-ath79.h
+++ b/drivers/clk/clk-ath79.h
@@ -9,186 +9,132 @@
#include <linux/bits.h>
-#define AR71XX_APB_BASE 0x18000000
-#define AR934X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000)
-#define AR934X_SRIF_SIZE 0x1000
-#define AR71XX_PLL_REG_CPU_CONFIG 0x00
-#define AR71XX_PLL_FB_SHIFT 3
-#define AR71XX_PLL_FB_MASK 0x1f
-#define AR71XX_CPU_DIV_SHIFT 16
-#define AR71XX_CPU_DIV_MASK 0x3
-#define AR71XX_DDR_DIV_SHIFT 18
-#define AR71XX_DDR_DIV_MASK 0x3
-#define AR71XX_AHB_DIV_SHIFT 20
-#define AR71XX_AHB_DIV_MASK 0x7
-#define AR724X_PLL_REG_CPU_CONFIG 0x00
-#define AR724X_PLL_FB_SHIFT 0
-#define AR724X_PLL_FB_MASK 0x3ff
-#define AR724X_PLL_REF_DIV_SHIFT 10
-#define AR724X_PLL_REF_DIV_MASK 0xf
-#define AR724X_AHB_DIV_SHIFT 19
-#define AR724X_AHB_DIV_MASK 0x1
-#define AR724X_DDR_DIV_SHIFT 22
-#define AR724X_DDR_DIV_MASK 0x3
-#define AR933X_PLL_CPU_CONFIG_REG 0x00
-#define AR933X_PLL_CLOCK_CTRL_REG 0x08
-#define AR933X_PLL_CPU_CONFIG_NINT_SHIFT 10
-#define AR933X_PLL_CPU_CONFIG_NINT_MASK 0x3f
-#define AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT 16
-#define AR933X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f
-#define AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT 23
-#define AR933X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7
-#define AR933X_PLL_CLOCK_CTRL_BYPASS BIT(2)
-#define AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT 5
-#define AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK 0x3
-#define AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT 10
-#define AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK 0x3
-#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT 15
-#define AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK 0x7
-#define AR934X_PLL_CPU_CONFIG_REG 0x00
-#define AR934X_PLL_DDR_CONFIG_REG 0x04
-#define AR934X_PLL_CPU_DDR_CLK_CTRL_REG 0x08
-#define AR934X_PLL_SWITCH_CLOCK_CONTROL_REG 0x24
-#define AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT 0
-#define AR934X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f
-#define AR934X_PLL_CPU_CONFIG_NINT_SHIFT 6
-#define AR934X_PLL_CPU_CONFIG_NINT_MASK 0x3f
-#define AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT 12
-#define AR934X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f
-#define AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19
-#define AR934X_PLL_CPU_CONFIG_OUTDIV_MASK 0x3
-#define AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT 0
-#define AR934X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff
-#define AR934X_PLL_DDR_CONFIG_NINT_SHIFT 10
-#define AR934X_PLL_DDR_CONFIG_NINT_MASK 0x3f
-#define AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT 16
-#define AR934X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f
-#define AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23
-#define AR934X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7
+#define AR71XX_APB_BASE 0x18000000
+
+#define AR934X_SRIF_BASE (AR71XX_APB_BASE + 0x00116000)
+#define AR934X_SRIF_SIZE 0x1000
+
+#define AR71XX_PLL_REG_CPU_CONFIG 0x00
+#define AR71XX_PLL_FB GENMASK(7, 3)
+#define AR71XX_CPU_DIV GENMASK(17, 16)
+#define AR71XX_DDR_DIV GENMASK(19, 18)
+#define AR71XX_AHB_DIV GENMASK(22, 20)
+
+#define AR724X_PLL_REG_CPU_CONFIG 0x00
+#define AR724X_PLL_FB GENMASK(9, 0)
+#define AR724X_PLL_REF_DIV GENMASK(13, 10)
+#define AR724X_AHB_DIV GENMASK(19, 19)
+#define AR724X_DDR_DIV GENMASK(23, 22)
+
+#define AR933X_PLL_CPU_CONFIG_REG 0x00
+#define AR933X_PLL_CLOCK_CTRL_REG 0x08
+#define AR933X_PLL_CPU_CONFIG_NINT GENMASK(15, 10)
+#define AR933X_PLL_CPU_CONFIG_REFDIV GENMASK(20, 16)
+#define AR933X_PLL_CPU_CONFIG_OUTDIV GENMASK(25, 23)
+#define AR933X_PLL_CLOCK_CTRL_BYPASS BIT(2)
+#define AR933X_PLL_CLOCK_CTRL_CPU_DIV GENMASK(6, 5)
+#define AR933X_PLL_CLOCK_CTRL_DDR_DIV GENMASK(11, 10)
+#define AR933X_PLL_CLOCK_CTRL_AHB_DIV GENMASK(17, 15)
+
+#define AR934X_PLL_CPU_CONFIG_REG 0x00
+#define AR934X_PLL_DDR_CONFIG_REG 0x04
+#define AR934X_PLL_CPU_DDR_CLK_CTRL_REG 0x08
+#define AR934X_PLL_SWITCH_CLOCK_CONTROL_REG 0x24
+#define AR934X_PLL_CPU_CONFIG_NFRAC GENMASK(5, 0)
+#define AR934X_PLL_CPU_CONFIG_NINT GENMASK(11, 6)
+#define AR934X_PLL_CPU_CONFIG_REFDIV GENMASK(16, 12)
+#define AR934X_PLL_CPU_CONFIG_OUTDIV GENMASK(20, 19)
+#define AR934X_PLL_DDR_CONFIG_NFRAC GENMASK(9, 0)
+#define AR934X_PLL_DDR_CONFIG_NINT GENMASK(15, 10)
+#define AR934X_PLL_DDR_CONFIG_REFDIV GENMASK(20, 16)
+#define AR934X_PLL_DDR_CONFIG_OUTDIV GENMASK(25, 23)
#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS BIT(2)
#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS BIT(3)
#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS BIT(4)
-#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT 5
-#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK 0x1f
-#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT 10
-#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK 0x1f
-#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT 15
-#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK 0x1f
+#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV GENMASK(9, 5)
+#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV GENMASK(14, 10)
+#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV GENMASK(19, 15)
#define AR934X_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20)
#define AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21)
#define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
#define AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL BIT(6)
#define AR934X_PLL_SWITCH_CLOCK_CONTROL_UART1_CLK_SEL BIT(7)
-#define QCA953X_PLL_CPU_CONFIG_REG 0x00
-#define QCA953X_PLL_DDR_CONFIG_REG 0x04
-#define QCA953X_PLL_CLK_CTRL_REG 0x08
-#define QCA953X_PLL_CPU_CONFIG_NFRAC_SHIFT 0
-#define QCA953X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f
-#define QCA953X_PLL_CPU_CONFIG_NINT_SHIFT 6
-#define QCA953X_PLL_CPU_CONFIG_NINT_MASK 0x3f
-#define QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT 12
-#define QCA953X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f
-#define QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19
-#define QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7
-#define QCA953X_PLL_DDR_CONFIG_NFRAC_SHIFT 0
-#define QCA953X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff
-#define QCA953X_PLL_DDR_CONFIG_NINT_SHIFT 10
-#define QCA953X_PLL_DDR_CONFIG_NINT_MASK 0x3f
-#define QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT 16
-#define QCA953X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f
-#define QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23
-#define QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7
+
+#define QCA953X_PLL_CPU_CONFIG_REG 0x00
+#define QCA953X_PLL_DDR_CONFIG_REG 0x04
+#define QCA953X_PLL_CLK_CTRL_REG 0x08
+#define QCA953X_PLL_CPU_CONFIG_NFRAC GENMASK(5, 0)
+#define QCA953X_PLL_CPU_CONFIG_NINT GENMASK(11, 6)
+#define QCA953X_PLL_CPU_CONFIG_REFDIV GENMASK(16, 12)
+#define QCA953X_PLL_CPU_CONFIG_OUTDIV GENMASK(21, 19)
+#define QCA953X_PLL_DDR_CONFIG_NFRAC GENMASK(9, 0)
+#define QCA953X_PLL_DDR_CONFIG_NINT GENMASK(15, 10)
+#define QCA953X_PLL_DDR_CONFIG_REFDIV GENMASK(20, 16)
+#define QCA953X_PLL_DDR_CONFIG_OUTDIV GENMASK(25, 23)
#define QCA953X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2)
#define QCA953X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3)
#define QCA953X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4)
-#define QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5
-#define QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f
-#define QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10
-#define QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f
-#define QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15
-#define QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f
+#define QCA953X_PLL_CLK_CTRL_CPU_POST_DIV GENMASK(9, 5)
+#define QCA953X_PLL_CLK_CTRL_DDR_POST_DIV GENMASK(14, 10)
+#define QCA953X_PLL_CLK_CTRL_AHB_POST_DIV GENMASK(19, 15)
#define QCA953X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20)
#define QCA953X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21)
#define QCA953X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
-#define QCA955X_PLL_CPU_CONFIG_REG 0x00
-#define QCA955X_PLL_DDR_CONFIG_REG 0x04
-#define QCA955X_PLL_CLK_CTRL_REG 0x08
-#define QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT 0
-#define QCA955X_PLL_CPU_CONFIG_NFRAC_MASK 0x3f
-#define QCA955X_PLL_CPU_CONFIG_NINT_SHIFT 6
-#define QCA955X_PLL_CPU_CONFIG_NINT_MASK 0x3f
-#define QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT 12
-#define QCA955X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f
-#define QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19
-#define QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK 0x3
-#define QCA955X_PLL_DDR_CONFIG_NFRAC_SHIFT 0
-#define QCA955X_PLL_DDR_CONFIG_NFRAC_MASK 0x3ff
-#define QCA955X_PLL_DDR_CONFIG_NINT_SHIFT 10
-#define QCA955X_PLL_DDR_CONFIG_NINT_MASK 0x3f
-#define QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT 16
-#define QCA955X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f
-#define QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23
-#define QCA955X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7
+
+#define QCA955X_PLL_CPU_CONFIG_REG 0x00
+#define QCA955X_PLL_DDR_CONFIG_REG 0x04
+#define QCA955X_PLL_CLK_CTRL_REG 0x08
+#define QCA955X_PLL_CPU_CONFIG_NFRAC GENMASK(5, 0)
+#define QCA955X_PLL_CPU_CONFIG_NINT GENMASK(11, 6)
+#define QCA955X_PLL_CPU_CONFIG_REFDIV GENMASK(16, 12)
+#define QCA955X_PLL_CPU_CONFIG_OUTDIV GENMASK(20, 19)
+#define QCA955X_PLL_DDR_CONFIG_NFRAC GENMASK(9, 0)
+#define QCA955X_PLL_DDR_CONFIG_NINT GENMASK(15, 10)
+#define QCA955X_PLL_DDR_CONFIG_REFDIV GENMASK(20, 16)
+#define QCA955X_PLL_DDR_CONFIG_OUTDIV GENMASK(25, 23)
#define QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2)
#define QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3)
#define QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4)
-#define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5
-#define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f
-#define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10
-#define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f
-#define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15
-#define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f
+#define QCA955X_PLL_CLK_CTRL_CPU_POST_DIV GENMASK(9, 5)
+#define QCA955X_PLL_CLK_CTRL_DDR_POST_DIV GENMASK(14, 10)
+#define QCA955X_PLL_CLK_CTRL_AHB_POST_DIV GENMASK(19, 15)
#define QCA955X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL BIT(20)
#define QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL BIT(21)
#define QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
+
#define QCA956X_PLL_CPU_CONFIG_REG 0x00
#define QCA956X_PLL_CPU_CONFIG1_REG 0x04
#define QCA956X_PLL_DDR_CONFIG_REG 0x08
#define QCA956X_PLL_DDR_CONFIG1_REG 0x0c
#define QCA956X_PLL_CLK_CTRL_REG 0x10
-#define QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT 12
-#define QCA956X_PLL_CPU_CONFIG_REFDIV_MASK 0x1f
-#define QCA956X_PLL_CPU_CONFIG_OUTDIV_SHIFT 19
-#define QCA956X_PLL_CPU_CONFIG_OUTDIV_MASK 0x7
-#define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_SHIFT 0
-#define QCA956X_PLL_CPU_CONFIG1_NFRAC_L_MASK 0x1f
-#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_SHIFT 5
-#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H_MASK 0x1fff
-#define QCA956X_PLL_CPU_CONFIG1_NINT_SHIFT 18
-#define QCA956X_PLL_CPU_CONFIG1_NINT_MASK 0x1ff
-#define QCA956X_PLL_DDR_CONFIG_REFDIV_SHIFT 16
-#define QCA956X_PLL_DDR_CONFIG_REFDIV_MASK 0x1f
-#define QCA956X_PLL_DDR_CONFIG_OUTDIV_SHIFT 23
-#define QCA956X_PLL_DDR_CONFIG_OUTDIV_MASK 0x7
-#define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_SHIFT 0
-#define QCA956X_PLL_DDR_CONFIG1_NFRAC_L_MASK 0x1f
-#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_SHIFT 5
-#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H_MASK 0x1fff
-#define QCA956X_PLL_DDR_CONFIG1_NINT_SHIFT 18
-#define QCA956X_PLL_DDR_CONFIG1_NINT_MASK 0x1ff
+#define QCA956X_PLL_CPU_CONFIG_REFDIV GENMASK(16, 12)
+#define QCA956X_PLL_CPU_CONFIG_OUTDIV GENMASK(21, 19)
+#define QCA956X_PLL_CPU_CONFIG1_NFRAC_L GENMASK(4, 0)
+#define QCA956X_PLL_CPU_CONFIG1_NFRAC_H GENMASK(17, 5)
+#define QCA956X_PLL_CPU_CONFIG1_NINT GENMASK(26, 18)
+#define QCA956X_PLL_DDR_CONFIG_REFDIV GENMASK(20, 16)
+#define QCA956X_PLL_DDR_CONFIG_OUTDIV GENMASK(25, 23)
+#define QCA956X_PLL_DDR_CONFIG1_NFRAC_L GENMASK(4, 0)
+#define QCA956X_PLL_DDR_CONFIG1_NFRAC_H GENMASK(17, 5)
+#define QCA956X_PLL_DDR_CONFIG1_NINT GENMASK(26, 18)
#define QCA956X_PLL_CLK_CTRL_CPU_PLL_BYPASS BIT(2)
#define QCA956X_PLL_CLK_CTRL_DDR_PLL_BYPASS BIT(3)
#define QCA956X_PLL_CLK_CTRL_AHB_PLL_BYPASS BIT(4)
-#define QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT 5
-#define QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_MASK 0x1f
-#define QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT 10
-#define QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_MASK 0x1f
-#define QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT 15
-#define QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_MASK 0x1f
+#define QCA956X_PLL_CLK_CTRL_CPU_POST_DIV GENMASK(9, 5)
+#define QCA956X_PLL_CLK_CTRL_DDR_POST_DIV GENMASK(14, 10)
+#define QCA956X_PLL_CLK_CTRL_AHB_POST_DIV GENMASK(19, 15)
#define QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_DDRPLL BIT(20)
#define QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_CPUPLL BIT(21)
#define QCA956X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL BIT(24)
-#define AR934X_SRIF_CPU_DPLL1_REG 0x1c0
-#define AR934X_SRIF_CPU_DPLL2_REG 0x1c4
-#define AR934X_SRIF_DDR_DPLL1_REG 0x240
-#define AR934X_SRIF_DDR_DPLL2_REG 0x244
-#define AR934X_SRIF_DPLL1_REFDIV_SHIFT 27
-#define AR934X_SRIF_DPLL1_REFDIV_MASK 0x1f
-#define AR934X_SRIF_DPLL1_NINT_SHIFT 18
-#define AR934X_SRIF_DPLL1_NINT_MASK 0x1ff
-#define AR934X_SRIF_DPLL1_NFRAC_MASK 0x0003ffff
-#define AR934X_SRIF_DPLL2_LOCAL_PLL BIT(30)
-#define AR934X_SRIF_DPLL2_OUTDIV_SHIFT 13
-#define AR934X_SRIF_DPLL2_OUTDIV_MASK 0x7
+
+#define AR934X_SRIF_CPU_DPLL1_REG 0x1c0
+#define AR934X_SRIF_CPU_DPLL2_REG 0x1c4
+#define AR934X_SRIF_DDR_DPLL1_REG 0x240
+#define AR934X_SRIF_DDR_DPLL2_REG 0x244
+#define AR934X_SRIF_DPLL1_REFDIV GENMASK(31, 27)
+#define AR934X_SRIF_DPLL1_NINT GENMASK(26, 18)
+#define AR934X_SRIF_DPLL1_NFRAC GENMASK(17, 0)
+#define AR934X_SRIF_DPLL2_LOCAL_PLL BIT(30)
+#define AR934X_SRIF_DPLL2_OUTDIV GENMASK(15, 13)
#endif /* __CLK_ATH79_H */
--
2.56.0
next prev parent reply other threads:[~2026-11-04 5:59 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-11-04 5:58 [PATCH 0/8] clk: ath79: move the PLL clock driver to drivers/clk Rosen Penev
2026-11-04 5:58 ` [PATCH 1/8] MIPS: ath79: apply the QCA956x timer workaround in setup Rosen Penev
2026-11-04 5:58 ` [PATCH 2/8] MIPS: ath79: move the bootstrap reference clock to setup Rosen Penev
2026-11-04 5:58 ` [PATCH 3/8] clk: ath79: move the ath79 clock driver to drivers/clk Rosen Penev
2026-11-04 5:58 ` Rosen Penev [this message]
2026-11-04 5:58 ` [PATCH 5/8] clk: ath79: convert to clk_hw based registration Rosen Penev
2026-11-04 5:58 ` [PATCH 6/8] clk: ath79: fix the error handling Rosen Penev
2026-11-04 5:58 ` [PATCH 7/8] clk: ath79: give each compatible its own init function Rosen Penev
2026-11-04 5:58 ` [PATCH 8/8] clk: ath79: share the fractional PLL calculation Rosen Penev
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