[PATCH net-next 0/4] net: enetc: add i.MX952 NETC v4.6 support

[PATCH net-next 0/4] net: enetc: add i.MX952 NETC v4.6 support

[xiaoning.wang]

From: Clark Wang <xiaoning.wang@nxp.com>

This series adds Ethernet support for the NXP i.MX952, whose NETC is
revision 4.6. Its NETC integration differs from i.MX95 and i.MX94 in
the following ways:
 - there are two standalone ENETCs and no switch: ENETC 0 on PCIe bus 0
   (RMII/RGMII) and ENETC 1 on PCIe bus 1 (RMII/RGMII/SGMII), plus a
   single IEEE 1588 timer;
 - the NETC system clock is 133 MHz instead of 333 MHz;
 - the reset value of the ENETC 0 Tx byte credit registers is too small
   for jumbo frames.

The DTS patch set will be sent separately after this series is applied.

Clark Wang (4):
  dt-bindings: net: netc-blk-ctrl: add compatible string for i.MX952
    platforms
  net: enetc: add i.MX952 NETC blocks control support
  net: enetc: add i.MX952 ENETC support
  ptp: netc: use 133MHz as the default reference clock rate for i.MX952

 .../bindings/net/nxp,netc-blk-ctrl.yaml       |  1 +
 drivers/net/ethernet/freescale/enetc/enetc.c  | 23 ++++++
 .../ethernet/freescale/enetc/enetc_ethtool.c  |  1 +
 .../net/ethernet/freescale/enetc/enetc_hw.h   |  2 +
 .../ethernet/freescale/enetc/netc_blk_ctrl.c  | 76 +++++++++++++++++++
 drivers/ptp/ptp_netc.c                        |  7 +-
 6 files changed, 109 insertions(+), 1 deletion(-)

-- 
2.43.0

[PATCH net-next 1/4] dt-bindings: net: netc-blk-ctrl: add compatible string for i.MX952 platforms

[xiaoning.wang]

From: Clark Wang <xiaoning.wang@nxp.com>

Add the compatible string "nxp,imx952-netc-blk-ctrl" for i.MX952
platforms.

Signed-off-by: Clark Wang <xiaoning.wang@nxp.com>
---
 Documentation/devicetree/bindings/net/nxp,netc-blk-ctrl.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/net/nxp,netc-blk-ctrl.yaml b/Documentation/devicetree/bindings/net/nxp,netc-blk-ctrl.yaml
index deea4fd73d76..c443fe0b4693 100644
--- a/Documentation/devicetree/bindings/net/nxp,netc-blk-ctrl.yaml
+++ b/Documentation/devicetree/bindings/net/nxp,netc-blk-ctrl.yaml
@@ -23,6 +23,7 @@ properties:
     enum:
       - nxp,imx94-netc-blk-ctrl
       - nxp,imx95-netc-blk-ctrl
+      - nxp,imx952-netc-blk-ctrl
 
   reg:
     maxItems: 3
-- 
2.43.0

[PATCH net-next 2/4] net: enetc: add i.MX952 NETC blocks control support

[xiaoning.wang]

From: Clark Wang <xiaoning.wang@nxp.com>

The NETC of i.MX952(v4.6) has two standalone ENETCs.
 - ENETC 0 is on PCIe bus 0 and supports RMII and RGMII.
 - ENETC 1 is on PCIe bus 1 and supports RMII, RGMII and SGMII.
Add the netc_devinfo for i.MX952 to do the following pre-boot
initialization.

1. Set the MII protocol of the links in NETCMIX according to the
   'phy-mode' property of the ENETC nodes. RGMII is used by default.
   The PCS configuration required by SGMII will be added separately.

2. The reset value of the ENETC 0 transmit byte credit registers
   (E0TXHPTBCR and E0TXLPTBCR) is 0x5dc, which is only suitable for a
   maximum frame size of 1536 bytes. When jumbo frames are used, the
   byte credits are exhausted too early, so HTA has to wait for the
   credits to be returned, which reduces the transmit throughput. So
   set them to 0xc35, the same as the reset value of the ENETC 1
   registers.

Signed-off-by: Clark Wang <xiaoning.wang@nxp.com>
---
 .../ethernet/freescale/enetc/netc_blk_ctrl.c  | 76 +++++++++++++++++++
 1 file changed, 76 insertions(+)

diff --git a/drivers/net/ethernet/freescale/enetc/netc_blk_ctrl.c b/drivers/net/ethernet/freescale/enetc/netc_blk_ctrl.c
index c7eb0234c785..7320ea0e713f 100644
--- a/drivers/net/ethernet/freescale/enetc/netc_blk_ctrl.c
+++ b/drivers/net/ethernet/freescale/enetc/netc_blk_ctrl.c
@@ -67,6 +67,8 @@
 #define IERB_EMDIOFAUXR			0x344
 #define IERB_T0FAUXR			0x444
 #define IERB_ETBCR(a)			(0x300c + 0x100 * (a))
+#define IERB_ETXHPTBCR(a)		(0x3070 + 0x100 * (a))
+#define IERB_ETXLPTBCR(a)		(0x3074 + 0x100 * (a))
 #define IERB_LBCR(a)			(0x1010 + 0x40 * (a))
 #define  LBCR_MDIO_PHYAD_PRTAD(addr)	(((addr) & 0x1f) << 8)
 
@@ -89,6 +91,10 @@
 #define IMX94_ENETC1_LINK		4
 #define IMX94_ENETC2_LINK		5
 
+#define IMX952_ENETC0_BUS_DEVFN		0x0
+#define IMX952_ENETC1_BUS_DEVFN		0x100
+#define IMX952_TX_BYTE_CREDIT		0xc35
+
 #define NETC_ENETC_ID(a)		(a)
 #define NETC_TIMER_ID(a)		(a)
 
@@ -368,6 +374,56 @@ static int imx94_netcmix_init(struct platform_device *pdev)
 	return 0;
 }
 
+static int imx952_netcmix_init(struct platform_device *pdev)
+{
+	struct netc_blk_ctrl *priv = platform_get_drvdata(pdev);
+	struct device_node *np = pdev->dev.of_node;
+	phy_interface_t interface;
+	int bus_devfn, mii_proto;
+	u32 val;
+	int err;
+
+	/* Default setting of MII protocol */
+	val = MII_PROT(0, MII_PROT_RGMII) | MII_PROT(1, MII_PROT_RGMII);
+
+	/* Update the link MII protocol through parsing phy-mode */
+	for_each_child_of_node_scoped(np, child) {
+		for_each_child_of_node_scoped(child, gchild) {
+			if (!of_device_is_compatible(gchild, "pci1131,e101"))
+				continue;
+
+			bus_devfn = netc_of_pci_get_bus_devfn(gchild);
+			if (bus_devfn < 0)
+				return bus_devfn;
+
+			err = of_get_phy_mode(gchild, &interface);
+			if (err)
+				continue;
+
+			mii_proto = netc_get_link_mii_protocol(interface);
+			if (mii_proto < 0)
+				return mii_proto;
+
+			switch (bus_devfn) {
+			case IMX952_ENETC0_BUS_DEVFN:
+				val = u32_replace_bits(val, mii_proto,
+						       CFG_LINK_MII_PORT_0);
+				break;
+			case IMX952_ENETC1_BUS_DEVFN:
+				val = u32_replace_bits(val, mii_proto,
+						       CFG_LINK_MII_PORT_1);
+				break;
+			default:
+				return -EINVAL;
+			}
+		}
+	}
+
+	netc_reg_write(priv->netcmix, IMX95_CFG_LINK_MII_PROT, val);
+
+	return 0;
+}
+
 static bool netc_ierb_is_locked(struct netc_blk_ctrl *priv)
 {
 	return !!(netc_reg_read(priv->prb, PRB_NETCRR) & NETCRR_LOCK);
@@ -783,6 +839,19 @@ static int imx94_ierb_init(struct platform_device *pdev)
 	return 0;
 }
 
+static int imx952_ierb_init(struct platform_device *pdev)
+{
+	struct netc_blk_ctrl *priv = platform_get_drvdata(pdev);
+
+	/* The reset value of ENETC 0 Tx byte credits is too small for
+	 * jumbo frames, so use the same value as ENETC 1.
+	 */
+	netc_reg_write(priv->ierb, IERB_ETXHPTBCR(0), IMX952_TX_BYTE_CREDIT);
+	netc_reg_write(priv->ierb, IERB_ETXLPTBCR(0), IMX952_TX_BYTE_CREDIT);
+
+	return 0;
+}
+
 static int netc_ierb_init(struct platform_device *pdev)
 {
 	struct netc_blk_ctrl *priv = platform_get_drvdata(pdev);
@@ -882,9 +951,16 @@ static const struct netc_devinfo imx94_devinfo = {
 	.ierb_init = imx94_ierb_init,
 };
 
+static const struct netc_devinfo imx952_devinfo = {
+	.flags = NETC_HAS_NETCMIX,
+	.netcmix_init = imx952_netcmix_init,
+	.ierb_init = imx952_ierb_init,
+};
+
 static const struct of_device_id netc_blk_ctrl_match[] = {
 	{ .compatible = "nxp,imx95-netc-blk-ctrl", .data = &imx95_devinfo },
 	{ .compatible = "nxp,imx94-netc-blk-ctrl", .data = &imx94_devinfo },
+	{ .compatible = "nxp,imx952-netc-blk-ctrl", .data = &imx952_devinfo },
 	{},
 };
 MODULE_DEVICE_TABLE(of, netc_blk_ctrl_match);
-- 
2.43.0

[PATCH net-next 3/4] net: enetc: add i.MX952 ENETC support

[xiaoning.wang]

From: Clark Wang <xiaoning.wang@nxp.com>

The driver gets the driver data of ENETC based on the IP revision, so
the ENETC PF and VF fail to probe on i.MX952 because its revision(v4.6)
is not present in enetc_info.
Add the v4.6 entries to enetc_info.

Unlike i.MX95 and i.MX94, the NETC system clock of i.MX952 is 133MHz
rather than 333MHz. So add the new PF and VF driver data with
ENETC_CLK_133M for ENETC v4.6.

In addition, similar to i.MX94, the PTP timer is function 1 of device
0 on the PCIe bus of ENETC 0, so update enetc_get_phc_index_by_pdev()
to support getting the PHC index for ENETC v4.6.

Signed-off-by: Clark Wang <xiaoning.wang@nxp.com>
---
 drivers/net/ethernet/freescale/enetc/enetc.c  | 23 +++++++++++++++++++
 .../ethernet/freescale/enetc/enetc_ethtool.c  |  1 +
 .../net/ethernet/freescale/enetc/enetc_hw.h   |  2 ++
 3 files changed, 26 insertions(+)

diff --git a/drivers/net/ethernet/freescale/enetc/enetc.c b/drivers/net/ethernet/freescale/enetc/enetc.c
index c6571b5cc842..4ef387578b1e 100644
--- a/drivers/net/ethernet/freescale/enetc/enetc.c
+++ b/drivers/net/ethernet/freescale/enetc/enetc.c
@@ -3812,6 +3812,14 @@ static const struct enetc_drvdata enetc4_pf_data = {
 	.eth_ops = &enetc4_pf_ethtool_ops,
 };
 
+static const struct enetc_drvdata enetc4_6_pf_data = {
+	.sysclk_freq = ENETC_CLK_133M,
+	.tx_csum = true,
+	.max_frags = ENETC4_MAX_SKB_FRAGS,
+	.pmac_offset = ENETC4_PMAC_OFFSET,
+	.eth_ops = &enetc4_pf_ethtool_ops,
+};
+
 static const struct enetc_drvdata enetc4_ppm_data = {
 	.sysclk_freq = ENETC_CLK_333M,
 	.tx_csum = true,
@@ -3832,6 +3840,13 @@ static const struct enetc_drvdata enetc4_vf_data = {
 	.eth_ops = &enetc_vf_ethtool_ops,
 };
 
+static const struct enetc_drvdata enetc4_6_vf_data = {
+	.sysclk_freq = ENETC_CLK_133M,
+	.tx_csum = true,
+	.max_frags = ENETC4_MAX_SKB_FRAGS,
+	.eth_ops = &enetc_vf_ethtool_ops,
+};
+
 static const struct enetc_platform_info enetc_info[] = {
 	{ .revision = ENETC_REV_1_0,
 	  .dev_id = ENETC_DEV_ID_PF,
@@ -3862,6 +3877,14 @@ static const struct enetc_platform_info enetc_info[] = {
 	  .dev_id = NXP_ENETC_VF_DEV_ID,
 	  .data = &enetc4_vf_data,
 	},
+	{ .revision = ENETC_REV_4_6,
+	  .dev_id = NXP_ENETC_PF_DEV_ID,
+	  .data = &enetc4_6_pf_data,
+	},
+	{ .revision = ENETC_REV_4_6,
+	  .dev_id = NXP_ENETC_VF_DEV_ID,
+	  .data = &enetc4_6_vf_data,
+	},
 };
 
 int enetc_get_driver_data(struct enetc_si *si)
diff --git a/drivers/net/ethernet/freescale/enetc/enetc_ethtool.c b/drivers/net/ethernet/freescale/enetc/enetc_ethtool.c
index 7965dfd06f5f..3c6c6fc0ab8c 100644
--- a/drivers/net/ethernet/freescale/enetc/enetc_ethtool.c
+++ b/drivers/net/ethernet/freescale/enetc/enetc_ethtool.c
@@ -1149,6 +1149,7 @@ static int enetc_get_phc_index_by_pdev(struct enetc_si *si)
 		devfn = PCI_DEVFN(24, 0);
 		break;
 	case ENETC_REV_4_3:
+	case ENETC_REV_4_6:
 		devfn = PCI_DEVFN(0, 1);
 		break;
 	default:
diff --git a/drivers/net/ethernet/freescale/enetc/enetc_hw.h b/drivers/net/ethernet/freescale/enetc/enetc_hw.h
index 2c9d9042eb0b..339691cdf44f 100644
--- a/drivers/net/ethernet/freescale/enetc/enetc_hw.h
+++ b/drivers/net/ethernet/freescale/enetc/enetc_hw.h
@@ -414,6 +414,7 @@ enum enetc_bdr_type {TX, RX};
 #define ENETC_REV_1_0		0x0100
 #define ENETC_REV_4_1		0X0401
 #define ENETC_REV_4_3		0x0403
+#define ENETC_REV_4_6		0x0406
 
 #define ENETC_G_EIPBRR1		0x0bfc
 #define ENETC_G_EPFBLPR(n)	(0xd00 + 4 * (n))
@@ -1050,6 +1051,7 @@ struct enetc_cbd {
 
 #define ENETC_CLK_400M		400000000ULL
 #define ENETC_CLK_333M		333000000ULL
+#define ENETC_CLK_133M		133000000ULL
 
 static inline u32 enetc_cycles_to_usecs(u32 cycles, u64 clk_freq)
 {
-- 
2.43.0

[PATCH net-next 4/4] ptp: netc: use 133MHz as the default reference clock rate for i.MX952

[xiaoning.wang]

From: Clark Wang <xiaoning.wang@nxp.com>

If the 'clocks' property is not present in the DT node, the NETC system
clock is selected as the reference clock of the NETC Timer, and the
driver assumes that its rate is 333MHz. However, the NETC system clock
of i.MX952 (NETC v4.6) is 133MHz. Therefore, use 133MHz as the default
reference clock rate for i.MX952.

Signed-off-by: Clark Wang <xiaoning.wang@nxp.com>
---
 drivers/ptp/ptp_netc.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/ptp/ptp_netc.c b/drivers/ptp/ptp_netc.c
index 19ca99d80e95..e2f7dd8595f1 100644
--- a/drivers/ptp/ptp_netc.c
+++ b/drivers/ptp/ptp_netc.c
@@ -72,6 +72,7 @@
 #define NETC_GLOBAL_IPBRR0		0xbf8
 #define  IPBRR0_IP_REV			GENMASK(15, 0)
 #define NETC_REV_4_1			0x0401
+#define NETC_REV_4_6			0x0406
 
 #define NETC_TMR_FIPER_NUM		3
 #define NETC_TMR_INVALID_CHANNEL	NETC_TMR_FIPER_NUM
@@ -88,6 +89,7 @@
 #define NETC_TMR_EXT_OSC		2 /* tmr_1588_clk, from IO pins */
 
 #define NETC_TMR_SYSCLK_333M		333333333U
+#define NETC_TMR_SYSCLK_133M		133333333U
 
 enum netc_pp_type {
 	NETC_PP_PPS = 1,
@@ -858,7 +860,10 @@ static int netc_timer_get_reference_clk_source(struct netc_timer *priv)
 
 	/* Select NETC system clock as the reference clock by default */
 	priv->clk_select = NETC_TMR_SYSTEM_CLK;
-	priv->clk_freq = NETC_TMR_SYSCLK_333M;
+	if (priv->revision == NETC_REV_4_6)
+		priv->clk_freq = NETC_TMR_SYSCLK_133M;
+	else
+		priv->clk_freq = NETC_TMR_SYSCLK_333M;
 
 	/* Update the clock source of the reference clock if the clock
 	 * is specified in DT node.
-- 
2.43.0

Re: [PATCH net-next 4/4] ptp: netc: use 133MHz as the default reference clock rate for i.MX952

[Daniel Baluta]

On 11/4/26 11:22, xiaoning.wang@oss.nxp.com wrote:
> +#define NETC_REV_4_6			0x0406
>  
>  #define NETC_TMR_FIPER_NUM		3
>  #define NETC_TMR_INVALID_CHANNEL	NETC_TMR_FIPER_NUM
> @@ -88,6 +89,7 @@
>  #define NETC_TMR_EXT_OSC		2 /* tmr_1588_clk, from IO pins */
>  
>  #define NETC_TMR_SYSCLK_333M		333333333U
> +#define NETC_TMR_SYSCLK_133M		133333333U
>  

I wonder if you want to keep this sorted so that you add NETC_TMR_SYSCLK_133M
before NETC_TMR_SYSCLK_333M