[PATCH 0/3] dmaengine: tegra210-adma: Add Tegra268 support

[PATCH 0/3] dmaengine: tegra210-adma: Add Tegra268 support

[Sheetal]

Tegra268 reuses the Tegra264 ADMA register layout but has ten DMA
channels, five request IDs, six pages and a different uniform FIFO size.
Add its binding and SoC data, and derive the shared page configuration
masks from these limits.

Make the Tegra264 FIFO size explicit first so Tegra268 can select its
FIFO size without changing the existing devices' FIFO programming.

Anupama Kunkulagunta (2):
  dt-bindings: dma: nvidia,tegra210-adma: Add Tegra268 support
  dmaengine: tegra210-adma: Add Tegra268 support

Sheetal (1):
  dmaengine: tegra210-adma: Make Tegra264 FIFO size explicit

 .../bindings/dma/nvidia,tegra210-adma.yaml    | 13 ++++
 drivers/dma/tegra210-adma.c                   | 73 +++++++++++++++----
 2 files changed, 73 insertions(+), 13 deletions(-)

-- 
2.43.0

[PATCH 1/3] dt-bindings: dma: nvidia,tegra210-adma: Add Tegra268 support

[Sheetal]

From: Anupama Kunkulagunta <akunkulagunt@nvidia.com>

Add the Tegra268 ADMA compatible. Tegra268 has 10 ADMA channels,
so set the interrupt limit accordingly.

Signed-off-by: Anupama Kunkulagunta <akunkulagunt@nvidia.com>
Signed-off-by: Sheetal <sheetal@nvidia.com>
---
 .../bindings/dma/nvidia,tegra210-adma.yaml          | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/Documentation/devicetree/bindings/dma/nvidia,tegra210-adma.yaml b/Documentation/devicetree/bindings/dma/nvidia,tegra210-adma.yaml
index 269a1f7ebdbb..6aa9b83b90d9 100644
--- a/Documentation/devicetree/bindings/dma/nvidia,tegra210-adma.yaml
+++ b/Documentation/devicetree/bindings/dma/nvidia,tegra210-adma.yaml
@@ -20,6 +20,7 @@ properties:
           - nvidia,tegra210-adma
           - nvidia,tegra186-adma
           - nvidia,tegra264-adma
+          - nvidia,tegra268-adma
       - items:
           - enum:
               - nvidia,tegra234-adma
@@ -100,6 +101,17 @@ allOf:
         interrupts:
           maxItems: 32
 
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - nvidia,tegra268-adma
+    then:
+      properties:
+        interrupts:
+          maxItems: 10
+
   - if:
       properties:
         compatible:
@@ -107,6 +119,7 @@ allOf:
             enum:
               - nvidia,tegra186-adma
               - nvidia,tegra264-adma
+              - nvidia,tegra268-adma
     then:
       anyOf:
         - properties:
-- 
2.43.0

[PATCH 2/3] dmaengine: tegra210-adma: Make Tegra264 FIFO size explicit

[Sheetal]

Tegra264 uses the same ADMA FIFO size for every ADMAIF request. The
driver currently obtains this by setting sreq_index_offset to zero,
which makes every valid request select a FIFO size of 2.

Add a SoC data field for the uniform FIFO size and set it to 2 for
Tegra264. Retain the request-index-based FIFO selection for earlier
SoCs. This preserves existing FIFO programming and allows devices
with a different uniform FIFO size to specify it in their SoC data.

Signed-off-by: Sheetal <sheetal@nvidia.com>
---
 drivers/dma/tegra210-adma.c | 26 +++++++++++++++++++-------
 1 file changed, 19 insertions(+), 7 deletions(-)

diff --git a/drivers/dma/tegra210-adma.c b/drivers/dma/tegra210-adma.c
index 21a381d022cf..293a1119e07a 100644
--- a/drivers/dma/tegra210-adma.c
+++ b/drivers/dma/tegra210-adma.c
@@ -101,6 +101,7 @@ struct tegra_adma;
  * @ch_reg_size: Size of DMA channel register space.
  * @nr_channels: Number of DMA channels available.
  * @ch_fifo_size_mask: Mask for FIFO size field.
+ * @ch_fifo_size: FIFO size for devices with uniform channel FIFO size.
  * @sreq_index_offset: Slave channel index offset.
  * @max_page: Maximum ADMA Channel Page.
  * @set_global_pg_config: Global page programming.
@@ -125,6 +126,7 @@ struct tegra_adma_chip_data {
 	unsigned int ch_reg_size;
 	unsigned int nr_channels;
 	unsigned int ch_fifo_size_mask;
+	unsigned int ch_fifo_size;
 	unsigned int sreq_index_offset;
 	unsigned int max_page;
 	void (*set_global_pg_config)(struct tegra_adma *tdma);
@@ -725,18 +727,28 @@ static int tegra_adma_set_xfer_params(struct tegra_adma_chan *tdc,
 	 *
 	 * ADMA FIFO size is set as per below (based on default ADMAIF channel
 	 * FIFO sizes):
+	 * For Tegra264:
+	 *    fifo_size = ch_fifo_size
+	 * For devices prior to Tegra264:
 	 *    fifo_size = 0x2 (sreq_index > sreq_index_offset)
 	 *    fifo_size = 0x3 (sreq_index <= sreq_index_offset)
 	 *
 	 */
-	if (tdc->sreq_index > cdata->sreq_index_offset)
+	if (cdata->ch_fifo_size) {
 		ch_regs->fifo_ctrl =
-			ADMA_CH_REG_FIELD_VAL(2, cdata->ch_fifo_size_mask,
-					      fifo_size_shift);
-	else
-		ch_regs->fifo_ctrl =
-			ADMA_CH_REG_FIELD_VAL(3, cdata->ch_fifo_size_mask,
+			ADMA_CH_REG_FIELD_VAL(cdata->ch_fifo_size,
+					      cdata->ch_fifo_size_mask,
 					      fifo_size_shift);
+	} else {
+		if (tdc->sreq_index > cdata->sreq_index_offset)
+			ch_regs->fifo_ctrl =
+				ADMA_CH_REG_FIELD_VAL(2, cdata->ch_fifo_size_mask,
+						      fifo_size_shift);
+		else
+			ch_regs->fifo_ctrl =
+				ADMA_CH_REG_FIELD_VAL(3, cdata->ch_fifo_size_mask,
+						      fifo_size_shift);
+	}
 
 	ch_regs->tc = desc->period_len & ADMA_CH_TC_COUNT_MASK;
 
@@ -1018,7 +1030,7 @@ static const struct tegra_adma_chip_data tegra264_chip_data = {
 	.ch_reg_size		= 0x100,
 	.nr_channels		= 64,
 	.ch_fifo_size_mask	= 0x7f,
-	.sreq_index_offset	= 0,
+	.ch_fifo_size		= 2,
 	.max_page		= 10,
 	.set_global_pg_config	= tegra264_adma_global_page_config,
 };
-- 
2.43.0

[PATCH 3/3] dmaengine: tegra210-adma: Add Tegra268 support

[Sheetal]

From: Anupama Kunkulagunta <akunkulagunt@nvidia.com>

Tegra268 has 10 bidirectional ADMA channels to support the five RX and
five TX ADMA interfaces exposed by the audio processing engine (APE).
Only DMA request IDs 1 through 5 are valid for this device. Set
nr_channels to 10 and ch_req_max to 5 to match these limits.

Reuse the Tegra264 register layout and page configuration helper.
Derive the channel and request masks from the SoC data so the helper
handles both devices while preserving the existing Tegra264 register
values. Keep request bit 0 set, as in the Tegra264 programming.

Add the Tegra268 compatible and SoC data, including its six ADMA pages
and uniform FIFO size.

Signed-off-by: Anupama Kunkulagunta <akunkulagunt@nvidia.com>
Signed-off-by: Sheetal <sheetal@nvidia.com>
---
 drivers/dma/tegra210-adma.c | 49 +++++++++++++++++++++++++++++++------
 1 file changed, 42 insertions(+), 7 deletions(-)

diff --git a/drivers/dma/tegra210-adma.c b/drivers/dma/tegra210-adma.c
index 293a1119e07a..2d9dd41141cd 100644
--- a/drivers/dma/tegra210-adma.c
+++ b/drivers/dma/tegra210-adma.c
@@ -5,6 +5,7 @@
  * Copyright (c) 2016, NVIDIA CORPORATION.  All rights reserved.
  */
 
+#include <linux/bits.h>
 #include <linux/clk.h>
 #include <linux/iopoll.h>
 #include <linux/module.h>
@@ -279,6 +280,8 @@ static void tegra186_adma_global_page_config(struct tegra_adma *tdma)
 static void tegra264_adma_global_page_config(struct tegra_adma *tdma)
 {
 	u32 global_page_offset = tdma->ch_page_no * TEGRA264_ADMA_GLOBAL_PAGE_OFFSET;
+	u64 ch_mask = GENMASK_ULL(tdma->cdata->nr_channels - 1, 0);
+	u64 req_mask = GENMASK_ULL(tdma->cdata->ch_req_max, 0);
 
 	/* If the default page (page1) is not used, then clear page1 registers */
 	if (tdma->ch_page_no) {
@@ -291,12 +294,18 @@ static void tegra264_adma_global_page_config(struct tegra_adma *tdma)
 	}
 
 	/* Program global registers for selected page */
-	tdma_write(tdma, TEGRA264_ADMA_GLOBAL_PAGE_CHGRP_0 + global_page_offset, 0xffffffff);
-	tdma_write(tdma, TEGRA264_ADMA_GLOBAL_PAGE_CHGRP_1 + global_page_offset, 0xffffffff);
-	tdma_write(tdma, TEGRA264_ADMA_GLOBAL_PAGE_RX_REQ_0 + global_page_offset, 0xffffffff);
-	tdma_write(tdma, TEGRA264_ADMA_GLOBAL_PAGE_RX_REQ_1 + global_page_offset, 0x1);
-	tdma_write(tdma, TEGRA264_ADMA_GLOBAL_PAGE_TX_REQ_0 + global_page_offset, 0xffffffff);
-	tdma_write(tdma, TEGRA264_ADMA_GLOBAL_PAGE_TX_REQ_1 + global_page_offset, 0x1);
+	tdma_write(tdma, TEGRA264_ADMA_GLOBAL_PAGE_CHGRP_0 + global_page_offset,
+		   lower_32_bits(ch_mask));
+	tdma_write(tdma, TEGRA264_ADMA_GLOBAL_PAGE_CHGRP_1 + global_page_offset,
+		   upper_32_bits(ch_mask));
+	tdma_write(tdma, TEGRA264_ADMA_GLOBAL_PAGE_RX_REQ_0 + global_page_offset,
+		   lower_32_bits(req_mask));
+	tdma_write(tdma, TEGRA264_ADMA_GLOBAL_PAGE_RX_REQ_1 + global_page_offset,
+		   upper_32_bits(req_mask));
+	tdma_write(tdma, TEGRA264_ADMA_GLOBAL_PAGE_TX_REQ_0 + global_page_offset,
+		   lower_32_bits(req_mask));
+	tdma_write(tdma, TEGRA264_ADMA_GLOBAL_PAGE_TX_REQ_1 + global_page_offset,
+		   upper_32_bits(req_mask));
 }
 
 static int tegra_adma_init(struct tegra_adma *tdma)
@@ -727,7 +736,7 @@ static int tegra_adma_set_xfer_params(struct tegra_adma_chan *tdc,
 	 *
 	 * ADMA FIFO size is set as per below (based on default ADMAIF channel
 	 * FIFO sizes):
-	 * For Tegra264:
+	 * For Tegra264 and Tegra268:
 	 *    fifo_size = ch_fifo_size
 	 * For devices prior to Tegra264:
 	 *    fifo_size = 0x2 (sreq_index > sreq_index_offset)
@@ -1035,10 +1044,36 @@ static const struct tegra_adma_chip_data tegra264_chip_data = {
 	.set_global_pg_config	= tegra264_adma_global_page_config,
 };
 
+static const struct tegra_adma_chip_data tegra268_chip_data = {
+	.adma_get_burst_config	= tegra186_adma_get_burst_config,
+	.global_reg_offset	= 0,
+	.global_int_clear	= 0x800c,
+	.global_ch_fifo_base	= ADMA_GLOBAL_CH_FIFO_CTRL,
+	.global_ch_config_base	= ADMA_GLOBAL_CH_CONFIG,
+	.ch_req_tx_shift	= 26,
+	.ch_req_rx_shift	= 20,
+	.ch_dir_shift		= 10,
+	.ch_mode_shift		= 7,
+	.ch_base_offset		= 0x10000,
+	.ch_tc_offset_diff	= 4,
+	.ch_config		= ADMA_GLOBAL_CH_CONFIG_WEIGHT_FOR_WRR(1) |
+				  ADMA_GLOBAL_CH_CONFIG_OUTSTANDING_REQS(8),
+	.ch_req_mask		= 0x3f,
+	.ch_dir_mask		= 7,
+	.ch_req_max		= 5,
+	.ch_reg_size		= 0x100,
+	.nr_channels		= 10,
+	.ch_fifo_size_mask	= 0x7f,
+	.ch_fifo_size		= 5,
+	.max_page		= 6,
+	.set_global_pg_config	= tegra264_adma_global_page_config,
+};
+
 static const struct of_device_id tegra_adma_of_match[] = {
 	{ .compatible = "nvidia,tegra210-adma", .data = &tegra210_chip_data },
 	{ .compatible = "nvidia,tegra186-adma", .data = &tegra186_chip_data },
 	{ .compatible = "nvidia,tegra264-adma", .data = &tegra264_chip_data },
+	{ .compatible = "nvidia,tegra268-adma", .data = &tegra268_chip_data },
 	{ },
 };
 MODULE_DEVICE_TABLE(of, tegra_adma_of_match);
-- 
2.43.0