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From: Joshua Machauer <machaujo@amazon.de>
To: Srirangan Madhavan <smadhavan@nvidia.com>
Cc: Alison Schofield <alison.schofield@intel.com>,
	Bjorn Helgaas <bhelgaas@google.com>,
	Dave Jiang <dave.jiang@intel.com>,
	Davidlohr Bueso <dave@stgolabs.net>,
	Ira Weiny <ira.weiny@intel.com>,
	Jonathan Cameron <jic23@kernel.org>,
	Vishal Verma <vishal.l.verma@intel.com>,
	<linux-cxl@vger.kernel.org>, <linux-pci@vger.kernel.org>,
	<linux-kernel@vger.kernel.org>, Li Ming <ming.li@zohomail.com>,
	"Alex Williamson" <alex.williamson@redhat.com>,
	<vsethi@nvidia.com>, <alwilliamson@nvidia.com>,
	Sai Yashwanth Reddy Kancherla <skancherla@nvidia.com>,
	Vishal Aslot <vaslot@nvidia.com>,
	Manish Honap <mhonap@nvidia.com>, Jiandi An <jan@nvidia.com>,
	Richard Cheng <icheng@nvidia.com>, <linux-tegra@vger.kernel.org>
Subject: Re: [PATCH v16 14/18] PCI/CXL: Reject reset with unsafe function scope
Date: Thu, 5 Nov 2026 14:36:10 +0000	[thread overview]
Message-ID: <20261105143611.31563-1-machaujo@amazon.de> (raw)
In-Reply-To: <20261029145703.2185231-15-smadhavan@nvidia.com>

On Thu, Oct 29, 2026 at 02:56:59PM +0000, Srirangan Madhavan wrote:
> @@ -515,6 +515,9 @@ int cxl_reset_function(struct pci_dev *pdev, bool probe)
>  	    !(ctrl & PCI_DVSEC_CXL_MEM_ENABLE))
>  		return -ENOTTY;
>
> +	if (pdev->is_virtfn || pdev->multifunction || pci_num_vf(pdev))
> +		return -ENOTTY;
> +
>  	if (probe)
>  		return 0;

[...]

> @@ -5026,6 +5026,9 @@ static int cxl_reset_bus_function(struct pci_dev *dev, bool probe)
>  	if (!dvsec)
>  		return -ENOTTY;
>
> +	if (dev->is_virtfn || dev->multifunction || pci_num_vf(dev))
> +		return -ENOTTY;
> +
>  	if (probe)
>  		return 0;

Could both checks go at the top of their functions, before the DVSEC
lookups? None of the three conditions depends on what the lookups
find.

pci_init_reset_methods() probes every reset method for every device
that is added, and enabling SR-IOV adds the VFs one after another.
Where the checks are now, each VF probe walks the extended
capabilities twice before it returns -ENOTTY: cxl_reset walks the
VF's own list for the CXL Device DVSEC, and cxl_bus walks the
upstream bridge's list for the CXL Port DVSEC. All VFs of a PF share
that bridge, so its walk repeats once per VF with the same result.

With the checks first, a VF returns -ENOTTY without a config read,
and the result for every device stays the same.

Thanks,
Joshua

  parent reply	other threads:[~2026-11-05 14:36 UTC|newest]

Thread overview: 42+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-10-29 14:56 [PATCH v16 00/18] PCI/CXL: Add CXL reset support for Type 2 devices Srirangan Madhavan
2026-10-29 14:56 ` [PATCH v16 01/18] cxl: Clarify decoder interleave limit Srirangan Madhavan
2026-10-29 14:56 ` [PATCH v16 02/18] cxl: Share CXL port upstream PCI device lookup Srirangan Madhavan
2026-10-29 14:56 ` [PATCH v16 03/18] cxl: Move decoder declarations to shared header Srirangan Madhavan
2026-10-29 14:56 ` [PATCH v16 04/18] cxl: Embed decoder configuration in a standalone structure Srirangan Madhavan
2026-10-29 14:56 ` [PATCH v16 05/18] cxl: Introduce endpoint HDM decoder settings Srirangan Madhavan
2026-10-29 14:56 ` [PATCH v16 06/18] cxl: Move HDM decoder helpers to built-in code Srirangan Madhavan
2026-10-30  4:01   ` Richard Cheng
2026-10-29 14:56 ` [PATCH v16 07/18] cxl: Share HDM decoder register unpacking Srirangan Madhavan
2026-10-30  6:21   ` Richard Cheng
2026-11-05 16:07     ` Srirangan Madhavan
2026-10-29 14:56 ` [PATCH v16 08/18] cxl: Move cxl_rwsem into built-in code Srirangan Madhavan
2026-10-30  6:26   ` Richard Cheng
2026-10-29 14:56 ` [PATCH v16 09/18] cxl: Refresh cached PCI HDM decoder settings Srirangan Madhavan
2026-10-30  6:58   ` Richard Cheng
2026-10-29 14:56 ` [PATCH v16 10/18] cxl: Build register block helpers into the kernel Srirangan Madhavan
2026-10-30  7:02   ` Richard Cheng
2026-10-29 14:56 ` [PATCH v16 11/18] PCI/CXL: Cache endpoint HDM state during PCI enumeration Srirangan Madhavan
2026-10-30  8:22   ` Richard Cheng
2026-11-05 16:06     ` Srirangan Madhavan
2026-11-02  7:47   ` Li Ming
2026-11-05 16:04     ` Srirangan Madhavan
2026-10-29 14:56 ` [PATCH v16 12/18] PCI/CXL: Add CXL Device Reset sequencing Srirangan Madhavan
2026-10-30  3:22   ` Richard Cheng
2026-11-05 16:12     ` Srirangan Madhavan
2026-10-29 14:56 ` [PATCH v16 13/18] cxl: Validate and synchronize HDM ranges around reset Srirangan Madhavan
2026-10-30  3:45   ` Richard Cheng
2026-11-05 16:28     ` Srirangan Madhavan
2026-10-29 14:56 ` [PATCH v16 14/18] PCI/CXL: Reject reset with unsafe function scope Srirangan Madhavan
2026-10-30  8:37   ` Richard Cheng
2026-11-05 14:36   ` Joshua Machauer [this message]
2026-11-05 16:50     ` Srirangan Madhavan
2026-10-29 14:57 ` [PATCH v16 15/18] PCI/CXL: Restore CXL state after PCI reset Srirangan Madhavan
2026-10-29 14:57 ` [PATCH v16 16/18] PCI/CXL: Expose CXL Reset as a PCI reset method Srirangan Madhavan
2026-10-30  8:36   ` Richard Cheng
2026-10-29 14:57 ` [PATCH v16 17/18] PCI/CXL: Restore CXL state after CXL bus reset Srirangan Madhavan
2026-10-30  9:22   ` Richard Cheng
2026-11-05 16:49     ` Srirangan Madhavan
2026-10-29 14:57 ` [PATCH v16 18/18] cxl: Add KUnit checks for HDM decoder unpacking Srirangan Madhavan
2026-10-29 18:58 ` [PATCH v16 00/18] PCI/CXL: Add CXL reset support for Type 2 devices Alison Schofield
2026-10-29 23:03   ` Srirangan Madhavan
2026-11-05 19:09   ` Srirangan Madhavan

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