Re: [PATCH v16 12/18] PCI/CXL: Add CXL Device Reset sequencing

[Srirangan Madhavan <smadhavan@nvidia.com>]

On 10/29/26 8:22 PM, Richard Cheng wrote:
>> +	/* Allow one retry after the mandatory 100 ms quiet period. */
>> +	timeout_ms = clamp_t(u32, cxl_reset_timeout_ms[idx],
>> +			     CXL_RESET_RRS_WAIT_MS + CXL_RESET_STATUS_POLL_MS,
>> +			     CXL_RESET_MAX_WAIT_MS);
> This part will make 100 sec clamps to 20s if I understand correctly.
> 
> However the device is still legal to advertise 100s timeout according to the
> spec. If the reset procedure takes longer than 20s, driver can read/write to
> "Control2" register while device is still resetting, which is prohibited
> by the spec, software should access only "Status2" until completion, error,
> or expiration of the advertised timeout.
> 
> I wonder what's the reason here, if we really going to disagree with the spec,
> though I think it's not a wise choice.

Hi Richard,

Thanks for highlighting. You are right. The 20 second cap came from 
Benjamin Cheatham's v13 suggestion that a 100 second wait was too long,
but it let the driver access Control2 while a device advertising 100
seconds could still be resetting.

I checked the spec again and in v17 I dropped the cap. The wait now uses 
the timeout the device advertises, up to 100 seconds, and only Status2 
is accessed until reset completion, error, or expiry. Control2 cleanup 
runs afterwards.

The cost is that the global region lock can be held for that long. The
patch 13 commit message now says so. Unless there is others objection to 
using the advertised timeout.

-- 
Regards,
Srirangan