Re: [PATCH v16 11/18] PCI/CXL: Cache endpoint HDM state during PCI enumeration

[Srirangan Madhavan <smadhavan@nvidia.com>]

On 11/1/26 11:47 PM, Li Ming wrote:
>> +/* A published cache is usable only if its HDM register block was 
>> mapped. */
>> +bool cxl_hdm_cache_present(struct cxl_hdm_info *const *slot)
>> +{
>> +     guard(rwsem_read)(&cxl_rwsem.dpa);
>> +
>> +     return *slot && (*slot)->hdm_size;
>> +}
> 
> Hi Srirangan,
> 
> I raised a question about why using cxl_rwsem.dpa lock here in v15
> version[1] that may have gone unnoticed. I am still wondering why you
> use cxl_rwsem.dpa rather than the device lock here, if the lock is just
> used to protect assignments to info, I think device lock is enough,
> cxl_rwsem.dpa is a global lock, it will block other flows in CXL
> subsystem that are unrelated to the current device.
> 
> If I miss some cases, please let me know, thanks.
> 
> 
> [1]:
> https://lore.kernel.org/linux-cxl/20261011021422.3428136-1- 
> smadhavan@nvidia.com/T/#m7f8d0e51d4cfe09fefcebd93d49dcb916be9198a
> 
> 
> Ming

Hi Li,

You are right, and I'm sorry I missed your v15 question. The PCI device 
lock held since the cache check already excludes other initializers, and
no CXL driver is bound before enumeration finishes, so no cache mutator
can run yet. The DPA lock is not needed to publish the cache.

In v17 I dropped it and removed the cxl_hdm_cache_present() and
cxl_hdm_cache_publish() helpers.
Thank you.

-- 
Regards,
Srirangan