From: Srirangan Madhavan <smadhavan@nvidia.com>
To: Alison Schofield <alison.schofield@intel.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>,
Dave Jiang <dave.jiang@intel.com>,
Davidlohr Bueso <dave@stgolabs.net>,
Ira Weiny <ira.weiny@intel.com>,
Jonathan Cameron <jic23@kernel.org>,
Vishal Verma <vishal.l.verma@intel.com>,
linux-cxl@vger.kernel.org, linux-pci@vger.kernel.org,
linux-kernel@vger.kernel.org, Li Ming <ming.li@zohomail.com>,
Alex Williamson <alex.williamson@redhat.com>,
vsethi@nvidia.com, alwilliamson@nvidia.com,
Sai Yashwanth Reddy Kancherla <skancherla@nvidia.com>,
Vishal Aslot <vaslot@nvidia.com>,
Manish Honap <mhonap@nvidia.com>, Jiandi An <jan@nvidia.com>,
Richard Cheng <icheng@nvidia.com>,
linux-tegra@vger.kernel.org
Subject: Re: [PATCH v16 00/18] PCI/CXL: Add CXL reset support for Type 2 devices
Date: Thu, 5 Nov 2026 11:09:45 -0800 [thread overview]
Message-ID: <e05d04f4-a5d5-426b-b6e2-59eef53c277b@nvidia.com> (raw)
In-Reply-To: <auOXW3BTb8CYIh4m@aschofie-mobl2.lan>
On 10/29/26 11:58 AM, Alison Schofield wrote:
>> Userspace selects "cxl_reset" in reset_method and triggers the reset
>> through reset. Following Dan's v6 feedback, this uses the PCI interface
>> instead of adding a memdev-specific sysfs ABI.
>>
>> For sysfs reset, the generic PCI path invokes the driver's reset_prepare()
>> callback when provided and disables PCI I/O, memory decoding, and bus
>> mastering. The CXL path reserves affected HDM ranges exclusively and
>> blocks IOMMU translations where applicable. It does not offline memory
>> or revoke mappings; it relies on CXL.mem users retaining conflicting
>> iomem resources while access remains active.
>>
>> Changes from v15 [1]:
>
> Srirangan,
>
> I notice you posted this v16 without responding to review feedback on v15.
>
> I've already compared v15 and v16 to see which review comments were addressed.
> However, that exercise is no substitute for responding to reviewers and
> resolving the discussions they initiate. Rather than me repeating the
> outstanding comments from v15, in v16, can you go back and respond to the v15
> reviews before we proceed?
>
> Reference is the guidance in Documentation/process/submitting-patches.rst,
> under "Respond to review comments". CXL subsystem contributors also often
> append the reviewer's name to the end of each changelog item to identify
> whose feedback prompted the change.
>
> Thanks,
> Alison
Hi Alison,
Following up now that I sent v17 out. I replied to the v15 comments, and
each v17 changelog item ends with the name of the reviewer whose
feedback prompted it, with links to the comments in the per-patch notes.
Two v15 discussions are still open and are noted in the cover letter:
the scope of the region lock, and the attribution for Dave's reference
branch. Please let me know if anything is missing.
--
Regards,
Srirangan
prev parent reply other threads:[~2026-11-05 19:10 UTC|newest]
Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-29 14:56 Srirangan Madhavan
2026-10-29 14:56 ` [PATCH v16 01/18] cxl: Clarify decoder interleave limit Srirangan Madhavan
2026-10-29 14:56 ` [PATCH v16 02/18] cxl: Share CXL port upstream PCI device lookup Srirangan Madhavan
2026-10-29 14:56 ` [PATCH v16 03/18] cxl: Move decoder declarations to shared header Srirangan Madhavan
2026-10-29 14:56 ` [PATCH v16 04/18] cxl: Embed decoder configuration in a standalone structure Srirangan Madhavan
2026-10-29 14:56 ` [PATCH v16 05/18] cxl: Introduce endpoint HDM decoder settings Srirangan Madhavan
2026-10-29 14:56 ` [PATCH v16 06/18] cxl: Move HDM decoder helpers to built-in code Srirangan Madhavan
2026-10-30 4:01 ` Richard Cheng
2026-10-29 14:56 ` [PATCH v16 07/18] cxl: Share HDM decoder register unpacking Srirangan Madhavan
2026-10-30 6:21 ` Richard Cheng
2026-11-05 16:07 ` Srirangan Madhavan
2026-10-29 14:56 ` [PATCH v16 08/18] cxl: Move cxl_rwsem into built-in code Srirangan Madhavan
2026-10-30 6:26 ` Richard Cheng
2026-10-29 14:56 ` [PATCH v16 09/18] cxl: Refresh cached PCI HDM decoder settings Srirangan Madhavan
2026-10-30 6:58 ` Richard Cheng
2026-10-29 14:56 ` [PATCH v16 10/18] cxl: Build register block helpers into the kernel Srirangan Madhavan
2026-10-30 7:02 ` Richard Cheng
2026-10-29 14:56 ` [PATCH v16 11/18] PCI/CXL: Cache endpoint HDM state during PCI enumeration Srirangan Madhavan
2026-10-30 8:22 ` Richard Cheng
2026-11-05 16:06 ` Srirangan Madhavan
2026-11-02 7:47 ` Li Ming
2026-11-05 16:04 ` Srirangan Madhavan
2026-10-29 14:56 ` [PATCH v16 12/18] PCI/CXL: Add CXL Device Reset sequencing Srirangan Madhavan
2026-10-30 3:22 ` Richard Cheng
2026-11-05 16:12 ` Srirangan Madhavan
2026-10-29 14:56 ` [PATCH v16 13/18] cxl: Validate and synchronize HDM ranges around reset Srirangan Madhavan
2026-10-30 3:45 ` Richard Cheng
2026-11-05 16:28 ` Srirangan Madhavan
2026-10-29 14:56 ` [PATCH v16 14/18] PCI/CXL: Reject reset with unsafe function scope Srirangan Madhavan
2026-10-30 8:37 ` Richard Cheng
2026-11-05 14:36 ` Joshua Machauer
2026-11-05 16:50 ` Srirangan Madhavan
2026-10-29 14:57 ` [PATCH v16 15/18] PCI/CXL: Restore CXL state after PCI reset Srirangan Madhavan
2026-10-29 14:57 ` [PATCH v16 16/18] PCI/CXL: Expose CXL Reset as a PCI reset method Srirangan Madhavan
2026-10-30 8:36 ` Richard Cheng
2026-10-29 14:57 ` [PATCH v16 17/18] PCI/CXL: Restore CXL state after CXL bus reset Srirangan Madhavan
2026-10-30 9:22 ` Richard Cheng
2026-11-05 16:49 ` Srirangan Madhavan
2026-10-29 14:57 ` [PATCH v16 18/18] cxl: Add KUnit checks for HDM decoder unpacking Srirangan Madhavan
2026-10-29 18:58 ` [PATCH v16 00/18] PCI/CXL: Add CXL reset support for Type 2 devices Alison Schofield
2026-10-29 23:03 ` Srirangan Madhavan
2026-11-05 19:09 ` Srirangan Madhavan [this message]
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