* [PATCH 1/3] dt-bindings: gpu: Add CIX Sky1 Mali support
2026-11-06 10:47 [PATCH 0/3] Add initial GPU support for CIX Sky1 Cunyuan Liu
@ 2026-11-06 10:47 ` Cunyuan Liu
2026-11-06 17:17 ` Conor Dooley
2026-11-06 10:47 ` [PATCH 2/3] drm/panthor: Add initial support for CIX Sky1 Cunyuan Liu
2026-11-06 10:47 ` [PATCH 3/3] arm64: dts: cix: Add GPU support for Sky1 Orion O6 Cunyuan Liu
2 siblings, 1 reply; 7+ messages in thread
From: Cunyuan Liu @ 2026-11-06 10:47 UTC (permalink / raw)
To: boris.brezillon, steven.price, liviu.dudau, robh, krzk+dt,
conor+dt, gary.yang, fugang.duan
Cc: daniel.almeida, aliceryhl, p.zabel, dri-devel, devicetree,
linux-arm-kernel, linux-kernel, rust-for-linux,
cix-kernel-upstream, robin.wang, cunyuan.liu
Describe the Mali CSF GPU on CIX Sky1. It uses core and stacks clocks,
an external reset and a GPU power domain.
Add the compatible string, resource requirements and an example.
Signed-off-by: Cunyuan Liu <cunyuan.liu@cixtech.com>
---
.../bindings/gpu/arm,mali-valhall-csf.yaml | 51 +++++++++++++++++++
1 file changed, 51 insertions(+)
diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml
index 8eccd4338a2b..a93acc6d91ec 100644
--- a/Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml
+++ b/Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml
@@ -18,6 +18,7 @@ properties:
oneOf:
- items:
- enum:
+ - cix,sky1-mali
- mediatek,mt8196-mali
- nxp,imx95-mali # G310
- rockchip,rk3588-mali
@@ -51,6 +52,9 @@ properties:
- stacks
- const: stacks
+ resets:
+ maxItems: 1
+
nvmem-cells:
items:
- description: bitmask of functional shader cores
@@ -146,6 +150,34 @@ allOf:
- nvmem-cells
- nvmem-cell-names
- power-domains
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: cix,sky1-mali
+ then:
+ properties:
+ clocks:
+ minItems: 2
+ maxItems: 2
+ clock-names:
+ items:
+ - const: core
+ - const: stacks
+ power-domains:
+ maxItems: 1
+ power-domain-names: false
+ mali-supply: false
+ sram-supply: false
+ nvmem-cells: false
+ nvmem-cell-names: false
+ required:
+ - clock-names
+ - resets
+ - power-domains
+ else:
+ properties:
+ resets: false
examples:
- |
@@ -196,4 +228,23 @@ examples:
power-domains = <&gpufreq>;
};
+ - |
+ #include <dt-bindings/clock/cix,sky1.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/reset/cix,sky1-s5-system-control.h>
+
+ gpu@15010000 {
+ compatible = "cix,sky1-mali", "arm,mali-valhall-csf";
+ reg = <0x15010000 0x480000>;
+ interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "job", "mmu", "gpu";
+ clocks = <&scmi_clk CLK_TREE_GPU_CLK_CORE>,
+ <&scmi_clk CLK_TREE_GPU_CLK_STACKS>;
+ clock-names = "core", "stacks";
+ resets = <&s5_syscon SKY1_GPU_RESET_N>;
+ power-domains = <&smc_devpd 21>;
+ };
+
...
--
2.53.0
^ permalink raw reply [flat|nested] 7+ messages in thread* [PATCH 2/3] drm/panthor: Add initial support for CIX Sky1
2026-11-06 10:47 [PATCH 0/3] Add initial GPU support for CIX Sky1 Cunyuan Liu
2026-11-06 10:47 ` [PATCH 1/3] dt-bindings: gpu: Add CIX Sky1 Mali support Cunyuan Liu
@ 2026-11-06 10:47 ` Cunyuan Liu
2026-11-06 12:04 ` Philipp Zabel
2026-11-06 10:47 ` [PATCH 3/3] arm64: dts: cix: Add GPU support for Sky1 Orion O6 Cunyuan Liu
2 siblings, 1 reply; 7+ messages in thread
From: Cunyuan Liu @ 2026-11-06 10:47 UTC (permalink / raw)
To: boris.brezillon, steven.price, liviu.dudau, robh, krzk+dt,
conor+dt, gary.yang, fugang.duan
Cc: daniel.almeida, aliceryhl, p.zabel, dri-devel, devicetree,
linux-arm-kernel, linux-kernel, rust-for-linux,
cix-kernel-upstream, robin.wang, cunyuan.liu
Add Sky1 SoC data to support the external reset and system-level cache
settings, and to skip devfreq.
The GPU on CIX Sky1 needs an external reset before the driver first
accesses the hardware. Without this reset, the GPU hardware cannot be
accessed correctly.
Configure SYSC_ALLOC before L2 power-on. Without these settings, GPU
rendering results are displayed incorrectly.
Keep the clock settings provided by the PM firmware. This first version
does not read OPPs or enable devfreq. It does not register a GPU cooling
device.
Tested on Orion O6: offscreen pixel readback, kmscube, glmark2 at 1080p,
runtime suspend and resume with a retained EGL context, software-triggered
reset-worker tests, and module unload and reload. Display tests used
local Komeda support.
Signed-off-by: Cunyuan Liu <cunyuan.liu@cixtech.com>
---
drivers/gpu/drm/panthor/panthor_devfreq.c | 11 +++++++++-
drivers/gpu/drm/panthor/panthor_device.c | 15 +++++++++++++
drivers/gpu/drm/panthor/panthor_device.h | 25 ++++++++++++++++++++++
drivers/gpu/drm/panthor/panthor_drv.c | 15 +++++++++++++
drivers/gpu/drm/panthor/panthor_gpu.c | 14 ++++++++++++
drivers/gpu/drm/panthor/panthor_gpu_regs.h | 2 ++
6 files changed, 81 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/panthor/panthor_devfreq.c b/drivers/gpu/drm/panthor/panthor_devfreq.c
index 2249b41ca4af..1914549f7b1f 100644
--- a/drivers/gpu/drm/panthor/panthor_devfreq.c
+++ b/drivers/gpu/drm/panthor/panthor_devfreq.c
@@ -154,6 +154,12 @@ int panthor_devfreq_init(struct panthor_device *ptdev)
ptdev->devfreq = pdevfreq;
+ /* Keep the firmware clock settings until Sky1 devfreq is supported. */
+ if (ptdev->soc_data && ptdev->soc_data->skip_devfreq) {
+ ptdev->fast_rate = clk_get_rate(ptdev->clks.core);
+ return 0;
+ }
+
/*
* The power domain associated with the GPU may have already added an
* OPP table, complete with OPPs, as part of the platform bus
@@ -323,8 +329,11 @@ unsigned long panthor_devfreq_get_freq(struct panthor_device *ptdev)
unsigned long freq = 0;
int ret;
- if (!pdevfreq->devfreq)
+ if (!pdevfreq->devfreq) {
+ if (ptdev->soc_data && ptdev->soc_data->skip_devfreq)
+ return clk_get_rate(ptdev->clks.core);
return 0;
+ }
ret = pdevfreq->devfreq->profile->get_cur_freq(ptdev->base.dev, &freq);
if (ret)
diff --git a/drivers/gpu/drm/panthor/panthor_device.c b/drivers/gpu/drm/panthor/panthor_device.c
index 9687c59de350..1d682731a181 100644
--- a/drivers/gpu/drm/panthor/panthor_device.c
+++ b/drivers/gpu/drm/panthor/panthor_device.c
@@ -229,6 +229,13 @@ int panthor_device_init(struct panthor_device *ptdev)
return ret;
}
+ if (ptdev->soc_data && ptdev->soc_data->needs_external_reset) {
+ ptdev->reset_control = devm_reset_control_get_exclusive(ptdev->base.dev, NULL);
+ if (IS_ERR(ptdev->reset_control))
+ return dev_err_probe(ptdev->base.dev, PTR_ERR(ptdev->reset_control),
+ "Failed to get GPU reset\n");
+ }
+
ret = panthor_devfreq_init(ptdev);
if (ret)
return ret;
@@ -511,6 +518,12 @@ int panthor_device_resume(struct device *dev)
if (ret)
goto err_disable_stacks_clk;
+ if (ptdev->reset_control && !panthor_device_is_initialized(ptdev)) {
+ ret = reset_control_reset(ptdev->reset_control);
+ if (ret)
+ goto err_disable_coregroup_clk;
+ }
+
panthor_devfreq_resume(ptdev);
if (panthor_device_is_initialized(ptdev) &&
@@ -553,6 +566,8 @@ int panthor_device_resume(struct device *dev)
err_suspend_devfreq:
panthor_devfreq_suspend(ptdev);
+
+err_disable_coregroup_clk:
clk_disable_unprepare(ptdev->clks.coregroup);
err_disable_stacks_clk:
diff --git a/drivers/gpu/drm/panthor/panthor_device.h b/drivers/gpu/drm/panthor/panthor_device.h
index b55a3f9edd41..0923cc5df042 100644
--- a/drivers/gpu/drm/panthor/panthor_device.h
+++ b/drivers/gpu/drm/panthor/panthor_device.h
@@ -19,6 +19,8 @@
#include <drm/gpu_scheduler.h>
#include <drm/panthor_drm.h>
+struct reset_control;
+
struct panthor_csf;
struct panthor_csf_ctx;
struct panthor_device;
@@ -34,10 +36,30 @@ struct panthor_pwr;
struct panthor_vm;
struct panthor_vm_pool;
+/**
+ * struct panthor_sysc_config - GPU system-cache configuration
+ */
+struct panthor_sysc_config {
+ /** @alloc: System-cache allocation policies for GPU access types. */
+ u32 alloc[8];
+};
+
/**
* struct panthor_soc_data - Panthor SoC Data
*/
struct panthor_soc_data {
+ /**
+ * @needs_external_reset: Reset the GPU after enabling its clocks
+ * during initial probe.
+ */
+ bool needs_external_reset;
+
+ /** @skip_devfreq: Keep the firmware clock settings without devfreq. */
+ bool skip_devfreq;
+
+ /** @sysc_config: System-cache configuration, or NULL to keep defaults. */
+ const struct panthor_sysc_config *sysc_config;
+
/** @asn_hash_enable: True if GPU_L2_CONFIG_ASN_HASH_ENABLE must be set. */
bool asn_hash_enable;
@@ -138,6 +160,9 @@ struct panthor_device {
/** @soc_data: Optional SoC data. */
const struct panthor_soc_data *soc_data;
+ /** @reset_control: Optional external GPU reset. */
+ struct reset_control *reset_control;
+
/** @phys_addr: Physical address of the iomem region. */
phys_addr_t phys_addr;
diff --git a/drivers/gpu/drm/panthor/panthor_drv.c b/drivers/gpu/drm/panthor/panthor_drv.c
index dc8d0191aef4..766df6505a7b 100644
--- a/drivers/gpu/drm/panthor/panthor_drv.c
+++ b/drivers/gpu/drm/panthor/panthor_drv.c
@@ -1872,12 +1872,27 @@ static struct attribute *panthor_attrs[] = {
ATTRIBUTE_GROUPS(panthor);
+static const struct panthor_sysc_config sysc_config_cix_sky1 = {
+ /* Sky1 needs these SYSC_ALLOC policies for correct display of GPU output. */
+ .alloc = {
+ 0x00230000, 0x00000023, 0x00000000, 0x00000000,
+ 0x00523222, 0x00523200, 0x00000022, 0x00000032,
+ },
+};
+
+static const struct panthor_soc_data soc_data_cix_sky1 = {
+ .needs_external_reset = true,
+ .skip_devfreq = true,
+ .sysc_config = &sysc_config_cix_sky1,
+};
+
static const struct panthor_soc_data soc_data_mediatek_mt8196 = {
.asn_hash_enable = true,
.asn_hash = { 0xb, 0xe, 0x0, },
};
static const struct of_device_id dt_match[] = {
+ { .compatible = "cix,sky1-mali", .data = &soc_data_cix_sky1 },
{ .compatible = "mediatek,mt8196-mali", .data = &soc_data_mediatek_mt8196, },
{ .compatible = "rockchip,rk3588-mali" },
{ .compatible = "arm,mali-valhall-csf" },
diff --git a/drivers/gpu/drm/panthor/panthor_gpu.c b/drivers/gpu/drm/panthor/panthor_gpu.c
index a383b04f101e..9a6963fe62ae 100644
--- a/drivers/gpu/drm/panthor/panthor_gpu.c
+++ b/drivers/gpu/drm/panthor/panthor_gpu.c
@@ -63,6 +63,19 @@ static void panthor_gpu_coherency_set(struct panthor_device *ptdev)
ptdev->gpu_info.selected_coherency);
}
+static void panthor_gpu_sysc_config_set(struct panthor_device *ptdev)
+{
+ const struct panthor_sysc_config *config;
+ unsigned int i;
+
+ if (!ptdev->soc_data || !ptdev->soc_data->sysc_config)
+ return;
+
+ config = ptdev->soc_data->sysc_config;
+ for (i = 0; i < ARRAY_SIZE(config->alloc); i++)
+ gpu_write(ptdev->gpu->iomem, GPU_SYSC_ALLOC(i), config->alloc[i]);
+}
+
static void panthor_gpu_l2_config_set(struct panthor_device *ptdev)
{
struct panthor_gpu *gpu = ptdev->gpu;
@@ -317,6 +330,7 @@ int panthor_gpu_l2_power_on(struct panthor_device *ptdev)
}
/* Set the desired coherency mode and L2 config before the power up of L2 */
+ panthor_gpu_sysc_config_set(ptdev);
panthor_gpu_coherency_set(ptdev);
panthor_gpu_l2_config_set(ptdev);
diff --git a/drivers/gpu/drm/panthor/panthor_gpu_regs.h b/drivers/gpu/drm/panthor/panthor_gpu_regs.h
index 4c5b953796e4..f9b65a4dae83 100644
--- a/drivers/gpu/drm/panthor/panthor_gpu_regs.h
+++ b/drivers/gpu/drm/panthor/panthor_gpu_regs.h
@@ -116,4 +116,6 @@
#define GPU_COHERENCY_ACE 1
#define GPU_COHERENCY_NONE 31
+#define GPU_SYSC_ALLOC(n) (0x340 + (n) * 4)
+
#endif /* __PANTHOR_GPU_REGS_H__ */
--
2.53.0
^ permalink raw reply [flat|nested] 7+ messages in thread* [PATCH 3/3] arm64: dts: cix: Add GPU support for Sky1 Orion O6
2026-11-06 10:47 [PATCH 0/3] Add initial GPU support for CIX Sky1 Cunyuan Liu
2026-11-06 10:47 ` [PATCH 1/3] dt-bindings: gpu: Add CIX Sky1 Mali support Cunyuan Liu
2026-11-06 10:47 ` [PATCH 2/3] drm/panthor: Add initial support for CIX Sky1 Cunyuan Liu
@ 2026-11-06 10:47 ` Cunyuan Liu
2 siblings, 0 replies; 7+ messages in thread
From: Cunyuan Liu @ 2026-11-06 10:47 UTC (permalink / raw)
To: boris.brezillon, steven.price, liviu.dudau, robh, krzk+dt,
conor+dt, gary.yang, fugang.duan
Cc: daniel.almeida, aliceryhl, p.zabel, dri-devel, devicetree,
linux-arm-kernel, linux-kernel, rust-for-linux,
cix-kernel-upstream, robin.wang, cunyuan.liu
Add the Sky1 Mali GPU node with its registers, interrupts, clocks,
external reset and GPU power domain.
Keep the node disabled in the SoC file and enable it on Orion O6.
Signed-off-by: Cunyuan Liu <cunyuan.liu@cixtech.com>
---
arch/arm64/boot/dts/cix/sky1-orion-o6.dts | 4 ++++
arch/arm64/boot/dts/cix/sky1.dtsi | 16 ++++++++++++++++
2 files changed, 20 insertions(+)
diff --git a/arch/arm64/boot/dts/cix/sky1-orion-o6.dts b/arch/arm64/boot/dts/cix/sky1-orion-o6.dts
index e39c87774c12..853c9c6f202c 100644
--- a/arch/arm64/boot/dts/cix/sky1-orion-o6.dts
+++ b/arch/arm64/boot/dts/cix/sky1-orion-o6.dts
@@ -52,6 +52,10 @@ &fch_gpio3 {
status = "okay";
};
+&gpu {
+ status = "okay";
+};
+
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
diff --git a/arch/arm64/boot/dts/cix/sky1.dtsi b/arch/arm64/boot/dts/cix/sky1.dtsi
index 0a820f45feb9..d5d347964ad7 100644
--- a/arch/arm64/boot/dts/cix/sky1.dtsi
+++ b/arch/arm64/boot/dts/cix/sky1.dtsi
@@ -762,6 +762,22 @@ ppi_partition1: interrupt-partition-1 {
};
};
+ gpu: gpu@15010000 {
+ compatible = "cix,sky1-mali", "arm,mali-valhall-csf";
+ reg = <0x0 0x15010000 0x0 0x480000>;
+ interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "job", "mmu", "gpu";
+ clocks = <&scmi_clk CLK_TREE_GPU_CLK_CORE>,
+ <&scmi_clk CLK_TREE_GPU_CLK_STACKS>;
+ clock-names = "core", "stacks";
+ resets = <&s5_syscon SKY1_GPU_RESET_N>;
+ power-domains = <&smc_devpd SKY1_PD_GPU>;
+
+ status = "disabled";
+ };
+
s5_syscon: syscon@16000000 {
compatible = "cix,sky1-s5-system-control", "syscon";
reg = <0x0 0x16000000 0x0 0x1000>;
--
2.53.0
^ permalink raw reply [flat|nested] 7+ messages in thread