* [PATCH 1/3] dt-bindings: nvmem: Add SpacemiT K3 eFuse controller
2026-11-06 6:05 [PATCH 0/3] Add read-only SpacemiT K3 eFuse support Jiayu Du
@ 2026-11-06 6:05 ` Jiayu Du
2026-11-06 6:05 ` [PATCH 2/3] nvmem: Add read-only SpacemiT K3 eFuse support Jiayu Du
2026-11-06 6:05 ` [PATCH 3/3] riscv: dts: spacemit: Add K3 eFuse and temperature trim cells Jiayu Du
2 siblings, 0 replies; 5+ messages in thread
From: Jiayu Du @ 2026-11-06 6:05 UTC (permalink / raw)
To: srini
Cc: robh, krzk+dt, conor+dt, dlan, troy.mitchell, pjw, palmer, aou,
alex, p.zabel, devicetree, linux-riscv, spacemit, linux-kernel,
Jiayu Du
Describe the SpacemiT K3 eFuse controller and its readable bank 0 and
bank 7 shadow windows, which contain temperature calibration parameters
and other configuration data.
Define the AES_WTM clock and reset, little-endian data and
controller-relative NVMEM offsets. Use fixed-layout cells for the
temperature calibration parameters.
Signed-off-by: Jiayu Du <duge1256@gmail.com>
---
.../bindings/nvmem/spacemit,k3-efuse.yaml | 63 +++++++++++++++++++
MAINTAINERS | 5 ++
2 files changed, 68 insertions(+)
create mode 100644 Documentation/devicetree/bindings/nvmem/spacemit,k3-efuse.yaml
diff --git a/Documentation/devicetree/bindings/nvmem/spacemit,k3-efuse.yaml b/Documentation/devicetree/bindings/nvmem/spacemit,k3-efuse.yaml
new file mode 100644
index 000000000000..93f4301c8289
--- /dev/null
+++ b/Documentation/devicetree/bindings/nvmem/spacemit,k3-efuse.yaml
@@ -0,0 +1,63 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/nvmem/spacemit,k3-efuse.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: SpacemiT K3 eFuse controller
+
+maintainers:
+ - Jiayu Du <duge1256@gmail.com>
+
+description:
+ The K3 eFuse controller provides configuration and calibration data through
+ shadow registers. NVMEM uses little-endian data and controller-relative
+ offsets. Read access is limited to bank 0 (0x104-0x123) and bank 7 (0x190-0x1af).
+
+allOf:
+ - $ref: nvmem.yaml#
+
+properties:
+ compatible:
+ const: spacemit,k3-efuse
+
+ reg:
+ maxItems: 1
+ description: The 0x400-byte eFuse controller register block.
+
+ clocks:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - resets
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/spacemit,k3-clocks.h>
+ #include <dt-bindings/reset/spacemit,k3-resets.h>
+
+ efuse@f0702800 {
+ compatible = "spacemit,k3-efuse";
+ reg = <0xf0702800 0x400>;
+ clocks = <&syscon_apmu CLK_APMU_AES_WTM>;
+ resets = <&syscon_apmu RESET_APMU_AES_WTM>;
+
+ nvmem-layout {
+ compatible = "fixed-layout";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ temperature-trim@19a {
+ reg = <0x19a 0x2>;
+ bits = <4 8>;
+ };
+ };
+ };
diff --git a/MAINTAINERS b/MAINTAINERS
index 46c416cadacd..0a9eb764ffee 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -26525,6 +26525,11 @@ S: Maintained
F: Documentation/devicetree/bindings/sound/spacemit,k1-i2s.yaml
F: sound/soc/spacemit/k1_i2s.c
+SPACEMIT K3 EFUSE DRIVER
+M: Jiayu Du <duge1256@gmail.com>
+S: Maintained
+F: Documentation/devicetree/bindings/nvmem/spacemit,k3-efuse.yaml
+
SPACEMIT RESET CONTROLLER DRIVER
M: Guodong Xu <docular.xu@gmail.com>
L: linux-riscv@lists.infradead.org
--
2.43.0
^ permalink raw reply [flat|nested] 5+ messages in thread* [PATCH 2/3] nvmem: Add read-only SpacemiT K3 eFuse support
2026-11-06 6:05 [PATCH 0/3] Add read-only SpacemiT K3 eFuse support Jiayu Du
2026-11-06 6:05 ` [PATCH 1/3] dt-bindings: nvmem: Add SpacemiT K3 eFuse controller Jiayu Du
@ 2026-11-06 6:05 ` Jiayu Du
2026-11-06 12:15 ` Troy Mitchell
2026-11-06 6:05 ` [PATCH 3/3] riscv: dts: spacemit: Add K3 eFuse and temperature trim cells Jiayu Du
2 siblings, 1 reply; 5+ messages in thread
From: Jiayu Du @ 2026-11-06 6:05 UTC (permalink / raw)
To: srini
Cc: robh, krzk+dt, conor+dt, dlan, troy.mitchell, pjw, palmer, aou,
alex, p.zabel, devicetree, linux-riscv, spacemit, linux-kernel,
Jiayu Du
Add read-only NVMEM access to bank 0 and bank 7 of the SpacemiT K3 eFuse
controller. These banks contain temperature calibration parameters and
other configuration data.
Snapshot the shadow registers with aligned 32-bit reads and expose the
data in little-endian order at controller-relative offsets. Serve reads
from the snapshot and use keepouts for the remaining register ranges.
Keep the AES_WTM clock enabled and its shared reset deasserted while the
provider is registered.
Signed-off-by: Jiayu Du <duge1256@gmail.com>
---
MAINTAINERS | 1 +
drivers/nvmem/Kconfig | 14 +++
drivers/nvmem/Makefile | 1 +
drivers/nvmem/spacemit-k3-efuse.c | 151 ++++++++++++++++++++++++++++++
4 files changed, 167 insertions(+)
create mode 100644 drivers/nvmem/spacemit-k3-efuse.c
diff --git a/MAINTAINERS b/MAINTAINERS
index 0a9eb764ffee..e0af83ecee37 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -26529,6 +26529,7 @@ SPACEMIT K3 EFUSE DRIVER
M: Jiayu Du <duge1256@gmail.com>
S: Maintained
F: Documentation/devicetree/bindings/nvmem/spacemit,k3-efuse.yaml
+F: drivers/nvmem/spacemit-k3-efuse.c
SPACEMIT RESET CONTROLLER DRIVER
M: Guodong Xu <docular.xu@gmail.com>
diff --git a/drivers/nvmem/Kconfig b/drivers/nvmem/Kconfig
index d2f5bb236663..28d6c59fbd74 100644
--- a/drivers/nvmem/Kconfig
+++ b/drivers/nvmem/Kconfig
@@ -476,6 +476,20 @@ config NVMEM_SNVS_LPGPR
This driver can also be built as a module. If so, the module
will be called nvmem-snvs-lpgpr.
+config NVMEM_SPACEMIT_K3_EFUSE
+ tristate "SpacemiT K3 eFuse support"
+ depends on ARCH_SPACEMIT || COMPILE_TEST
+ depends on OF && HAS_IOMEM
+ depends on COMMON_CLK && RESET_CONTROLLER
+ help
+ Say Y here to read configuration and calibration data from the
+ SpacemiT K3 eFuse shadow banks. The boot firmware must have loaded
+ the shadow registers before Linux starts. Programming and reloading
+ the fuses are not supported.
+
+ This driver can also be built as a module. If so, the module will
+ be called spacemit-k3-efuse.
+
config NVMEM_SPMI_SDAM
tristate "SPMI SDAM Support"
depends on SPMI
diff --git a/drivers/nvmem/Makefile b/drivers/nvmem/Makefile
index 5e70bad9f0f9..d29716957faf 100644
--- a/drivers/nvmem/Makefile
+++ b/drivers/nvmem/Makefile
@@ -81,6 +81,7 @@ obj-$(CONFIG_NVMEM_SC27XX_EFUSE) += nvmem-sc27xx-efuse.o
nvmem-sc27xx-efuse-y := sc27xx-efuse.o
obj-$(CONFIG_NVMEM_SNVS_LPGPR) += nvmem_snvs_lpgpr.o
nvmem_snvs_lpgpr-y := snvs_lpgpr.o
+obj-$(CONFIG_NVMEM_SPACEMIT_K3_EFUSE) += spacemit-k3-efuse.o
obj-$(CONFIG_NVMEM_SPMI_SDAM) += nvmem_qcom-spmi-sdam.o
nvmem_qcom-spmi-sdam-y += qcom-spmi-sdam.o
obj-$(CONFIG_NVMEM_SPRD_EFUSE) += nvmem_sprd_efuse.o
diff --git a/drivers/nvmem/spacemit-k3-efuse.c b/drivers/nvmem/spacemit-k3-efuse.c
new file mode 100644
index 000000000000..d106053beae8
--- /dev/null
+++ b/drivers/nvmem/spacemit-k3-efuse.c
@@ -0,0 +1,151 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * SpacemiT K3 read-only eFuse driver
+ *
+ * Copyright (c) 2026 Spacemit Co. Ltd.
+ */
+
+#include <linux/array_size.h>
+#include <linux/clk.h>
+#include <linux/device.h>
+#include <linux/err.h>
+#include <linux/errno.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/nvmem-provider.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/reset.h>
+#include <linux/slab.h>
+#include <linux/string.h>
+#include <linux/unaligned.h>
+
+#define K3_EFUSE_REG_SIZE 0x400
+#define K3_EFUSE_BANK_SIZE 0x20
+#define K3_EFUSE_BANK0_OFFSET 0x104
+#define K3_EFUSE_BANK7_OFFSET 0x190
+
+static const unsigned int k3_efuse_bank_offsets[] = {
+ K3_EFUSE_BANK0_OFFSET,
+ K3_EFUSE_BANK7_OFFSET,
+};
+
+static const struct nvmem_keepout k3_efuse_keepouts[] = {
+ {
+ .start = 0,
+ .end = K3_EFUSE_BANK0_OFFSET,
+ }, {
+ .start = K3_EFUSE_BANK0_OFFSET + K3_EFUSE_BANK_SIZE,
+ .end = K3_EFUSE_BANK7_OFFSET,
+ }, {
+ .start = K3_EFUSE_BANK7_OFFSET + K3_EFUSE_BANK_SIZE,
+ .end = K3_EFUSE_REG_SIZE,
+ },
+};
+
+struct k3_efuse {
+ u8 data[ARRAY_SIZE(k3_efuse_bank_offsets)][K3_EFUSE_BANK_SIZE];
+};
+
+static int k3_efuse_read(void *context, unsigned int offset, void *val,
+ size_t bytes)
+{
+ struct k3_efuse *efuse = context;
+ unsigned int bank, index;
+
+ for (bank = 0; bank < ARRAY_SIZE(k3_efuse_bank_offsets); bank++) {
+ if (offset < k3_efuse_bank_offsets[bank])
+ continue;
+
+ index = offset - k3_efuse_bank_offsets[bank];
+ if (index >= K3_EFUSE_BANK_SIZE || bytes > K3_EFUSE_BANK_SIZE - index)
+ continue;
+
+ memcpy(val, efuse->data[bank] + index, bytes);
+ return 0;
+ }
+
+ return -EINVAL;
+}
+
+static int k3_efuse_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct nvmem_config config = {
+ .dev = dev,
+ .name = dev_name(dev),
+ .id = NVMEM_DEVID_NONE,
+ .owner = THIS_MODULE,
+ .type = NVMEM_TYPE_OTP,
+ .read_only = true,
+ .root_only = true,
+ .reg_read = k3_efuse_read,
+ .word_size = 1,
+ .stride = 1,
+ .size = K3_EFUSE_REG_SIZE,
+ .keepout = k3_efuse_keepouts,
+ .nkeepout = ARRAY_SIZE(k3_efuse_keepouts),
+ };
+ struct reset_control *reset;
+ struct nvmem_device *nvmem;
+ struct k3_efuse *efuse;
+ struct resource *res;
+ void __iomem *base;
+ struct clk *clk;
+ unsigned int bank, i;
+
+ base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ if (resource_size(res) != K3_EFUSE_REG_SIZE ||
+ res->start % sizeof(u32))
+ return dev_err_probe(dev, -EINVAL, "Invalid register window\n");
+
+ efuse = devm_kzalloc(dev, sizeof(*efuse), GFP_KERNEL);
+ if (!efuse)
+ return -ENOMEM;
+
+ clk = devm_clk_get_enabled(dev, NULL);
+ if (IS_ERR(clk))
+ return dev_err_probe(dev, PTR_ERR(clk), "Failed to enable clock\n");
+
+ reset = devm_reset_control_get_shared_deasserted(dev, NULL);
+ if (IS_ERR(reset))
+ return dev_err_probe(dev, PTR_ERR(reset), "Failed to deassert reset\n");
+
+ for (bank = 0; bank < ARRAY_SIZE(k3_efuse_bank_offsets); bank++) {
+ for (i = 0; i < K3_EFUSE_BANK_SIZE; i += sizeof(u32)) {
+ u32 val = readl(base + k3_efuse_bank_offsets[bank] + i);
+
+ put_unaligned_le32(val, efuse->data[bank] + i);
+ }
+ }
+
+ config.priv = efuse;
+
+ nvmem = devm_nvmem_register(dev, &config);
+ if (IS_ERR(nvmem))
+ return dev_err_probe(dev, PTR_ERR(nvmem), "Failed to register NVMEM\n");
+
+ return 0;
+}
+
+static const struct of_device_id k3_efuse_of_match[] = {
+ { .compatible = "spacemit,k3-efuse" },
+ { }
+};
+MODULE_DEVICE_TABLE(of, k3_efuse_of_match);
+
+static struct platform_driver k3_efuse_driver = {
+ .probe = k3_efuse_probe,
+ .driver = {
+ .name = "spacemit-k3-efuse",
+ .of_match_table = k3_efuse_of_match,
+ },
+};
+module_platform_driver(k3_efuse_driver);
+
+MODULE_AUTHOR("Jiayu Du <duge1256@gmail.com>");
+MODULE_DESCRIPTION("SpacemiT K3 read-only eFuse driver");
+MODULE_LICENSE("GPL");
--
2.43.0
^ permalink raw reply [flat|nested] 5+ messages in thread* [PATCH 3/3] riscv: dts: spacemit: Add K3 eFuse and temperature trim cells
2026-11-06 6:05 [PATCH 0/3] Add read-only SpacemiT K3 eFuse support Jiayu Du
2026-11-06 6:05 ` [PATCH 1/3] dt-bindings: nvmem: Add SpacemiT K3 eFuse controller Jiayu Du
2026-11-06 6:05 ` [PATCH 2/3] nvmem: Add read-only SpacemiT K3 eFuse support Jiayu Du
@ 2026-11-06 6:05 ` Jiayu Du
2 siblings, 0 replies; 5+ messages in thread
From: Jiayu Du @ 2026-11-06 6:05 UTC (permalink / raw)
To: srini
Cc: robh, krzk+dt, conor+dt, dlan, troy.mitchell, pjw, palmer, aou,
alex, p.zabel, devicetree, linux-riscv, spacemit, linux-kernel,
Jiayu Du
Add the K3 eFuse controller with its AES_WTM clock and reset. Describe
fixed-layout cells for the temperature calibration parameters stored in
bank 0 and bank 7, using controller-relative offsets.
Leave the controller disabled for board-level enablement.
Signed-off-by: Jiayu Du <duge1256@gmail.com>
---
arch/riscv/boot/dts/spacemit/k3.dtsi | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi
index e89d2cc5ca8c..51861fdc6a21 100644
--- a/arch/riscv/boot/dts/spacemit/k3.dtsi
+++ b/arch/riscv/boot/dts/spacemit/k3.dtsi
@@ -1439,6 +1439,31 @@ saplic: interrupt-controller@e0804000 {
/* sec_i2c3: 0xf0614000, not available from Linux */
+ efuse: efuse@f0702800 {
+ compatible = "spacemit,k3-efuse";
+ reg = <0x0 0xf0702800 0x0 0x400>;
+ clocks = <&syscon_apmu CLK_APMU_AES_WTM>;
+ resets = <&syscon_apmu RESET_APMU_AES_WTM>;
+
+ status = "disabled";
+
+ nvmem-layout {
+ compatible = "fixed-layout";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ soc_rtemp_trim1: temperature-trim@120 {
+ reg = <0x120 0x1>;
+ bits = <0 8>;
+ };
+
+ soc_rtemp_trim: temperature-trim@19a {
+ reg = <0x19a 0x2>;
+ bits = <4 8>;
+ };
+ };
+ };
+
mimsic: interrupt-controller@f1000000 {
compatible = "spacemit,k3-imsics", "riscv,imsics";
reg = <0x0 0xf1000000 0x0 0x10000>;
--
2.43.0
^ permalink raw reply [flat|nested] 5+ messages in thread