* [PATCH v11 2/5] clk: en7523: use devm variant for clk_hw_register and fixed clock
2026-11-06 11:58 [PATCH v11 0/5] clk: add support for Airoha AN7583 clock Christian Marangi
2026-11-06 11:58 ` [PATCH v11 1/5] dt-bindings: clock: airoha: Document support for " Christian Marangi
@ 2026-11-06 11:58 ` Christian Marangi
2026-11-06 11:58 ` [PATCH v11 3/5] clk: en7523: protect concurrent access to reset and PCI register Christian Marangi
` (2 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Christian Marangi @ 2026-11-06 11:58 UTC (permalink / raw)
To: Stephen Boyd, Brian Masney, Jerome Brunet, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Philipp Zabel, Felix Fietkau,
linux-clk, devicetree, linux-kernel
Cc: Christian Marangi
Use devm variant for clk_hw_register and clk_hw_register_fixed_rate
to correctly unregister the clocks on probe fails.
This should never happen under normal condition but it's better to
handle these cleanup.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
drivers/clk/clk-en7523.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/clk-en7523.c b/drivers/clk/clk-en7523.c
index 24fdec2e6198..2baec734df9f 100644
--- a/drivers/clk/clk-en7523.c
+++ b/drivers/clk/clk-en7523.c
@@ -651,7 +651,7 @@ static struct clk_hw *en7523_register_pcie_clk(struct device *dev,
if (init.ops->unprepare)
init.ops->unprepare(&cg->hw);
- if (clk_hw_register(dev, &cg->hw))
+ if (devm_clk_hw_register(dev, &cg->hw))
return NULL;
return &cg->hw;
@@ -708,7 +708,7 @@ static void en7523_register_clocks(struct device *dev, struct clk_hw_onecell_dat
val = readl(base + reg);
rate /= en7523_get_div(desc, val);
- hw = clk_hw_register_fixed_rate(dev, desc->name, NULL, 0, rate);
+ hw = devm_clk_hw_register_fixed_rate(dev, desc->name, NULL, 0, rate);
if (IS_ERR(hw)) {
pr_err("Failed to register clk %s: %ld\n",
desc->name, PTR_ERR(hw));
@@ -770,7 +770,7 @@ static void en7581_register_clocks(struct device *dev, struct clk_hw_onecell_dat
}
rate /= en7523_get_div(desc, val);
- hw = clk_hw_register_fixed_rate(dev, desc->name, NULL, 0, rate);
+ hw = devm_clk_hw_register_fixed_rate(dev, desc->name, NULL, 0, rate);
if (IS_ERR(hw)) {
pr_err("Failed to register clk %s: %ld\n",
desc->name, PTR_ERR(hw));
@@ -1105,7 +1105,7 @@ static void en751221_try_register_clk(struct device *dev, int key,
if (WARN_ON_ONCE(key >= EN751221_MAX_CLKS))
return;
- hw = clk_hw_register_fixed_rate(dev, name, NULL, 0, rate);
+ hw = devm_clk_hw_register_fixed_rate(dev, name, NULL, 0, rate);
if (IS_ERR(hw))
pr_err("Failed to register clk %s: %pe\n", name, hw);
else
--
2.55.0
^ permalink raw reply [flat|nested] 6+ messages in thread* [PATCH v11 3/5] clk: en7523: protect concurrent access to reset and PCI register
2026-11-06 11:58 [PATCH v11 0/5] clk: add support for Airoha AN7583 clock Christian Marangi
2026-11-06 11:58 ` [PATCH v11 1/5] dt-bindings: clock: airoha: Document support for " Christian Marangi
2026-11-06 11:58 ` [PATCH v11 2/5] clk: en7523: use devm variant for clk_hw_register and fixed clock Christian Marangi
@ 2026-11-06 11:58 ` Christian Marangi
2026-11-06 11:58 ` [PATCH v11 4/5] clk: en7523: generalize register clocks function Christian Marangi
2026-11-06 11:58 ` [PATCH v11 5/5] clk: en7523: add support for Airoha AN7583 clock Christian Marangi
4 siblings, 0 replies; 6+ messages in thread
From: Christian Marangi @ 2026-11-06 11:58 UTC (permalink / raw)
To: Stephen Boyd, Brian Masney, Jerome Brunet, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Philipp Zabel, Felix Fietkau,
linux-clk, devicetree, linux-kernel
Cc: Christian Marangi
Use spinlock for concurrent access to reset and PCI register to catch case
when clock is enabled/disabled while a reset is also operated at the same
time.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
drivers/clk/clk-en7523.c | 86 +++++++++++++++++++++++++++++++++++++++-
1 file changed, 84 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/clk-en7523.c b/drivers/clk/clk-en7523.c
index 2baec734df9f..e534a5c91e61 100644
--- a/drivers/clk/clk-en7523.c
+++ b/drivers/clk/clk-en7523.c
@@ -577,44 +577,87 @@ static u32 en7523_get_div(const struct en_clk_desc *desc, u32 val)
static int en7523_pci_is_enabled(struct clk_hw *hw)
{
struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw);
+ struct device *dev = clk_hw_get_dev(hw);
+ struct en_clk_priv *priv;
+ unsigned long flags;
+ u32 val;
- return !!(readl(cg->base + REG_PCI_CONTROL) & REG_PCI_CONTROL_REFCLK_EN1);
+ priv = dev_get_drvdata(dev);
+
+ spin_lock_irqsave(&priv->lock, flags);
+ val = readl(cg->base + REG_PCI_CONTROL);
+ spin_unlock_irqrestore(&priv->lock, flags);
+
+ return !!(val & REG_PCI_CONTROL_REFCLK_EN1);
}
static int en7523_pci_prepare(struct clk_hw *hw)
{
struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw);
+ struct device *dev = clk_hw_get_dev(hw);
void __iomem *np_base = cg->base;
+ struct en_clk_priv *priv;
+ unsigned long flags;
u32 val, mask;
+ priv = dev_get_drvdata(dev);
+
/* Need to pull device low before reset */
+ spin_lock_irqsave(&priv->lock, flags);
val = readl(np_base + REG_PCI_CONTROL);
val &= ~(REG_PCI_CONTROL_PERSTOUT1 | REG_PCI_CONTROL_PERSTOUT);
writel(val, np_base + REG_PCI_CONTROL);
+ spin_unlock_irqrestore(&priv->lock, flags);
+
usleep_range(1000, 2000);
/* Enable PCIe port 1 */
+ spin_lock_irqsave(&priv->lock, flags);
+ val = readl(np_base + REG_PCI_CONTROL);
val |= REG_PCI_CONTROL_REFCLK_EN1;
writel(val, np_base + REG_PCI_CONTROL);
+ spin_unlock_irqrestore(&priv->lock, flags);
+
usleep_range(1000, 2000);
/* Reset to default */
+ spin_lock_irqsave(&priv->lock, flags);
val = readl(np_base + REG_RESET_CONTROL1);
mask = REG_RESET_CONTROL_PCIE1 | REG_RESET_CONTROL_PCIE2 |
REG_RESET_CONTROL_PCIEHB;
writel(val & ~mask, np_base + REG_RESET_CONTROL1);
+ spin_unlock_irqrestore(&priv->lock, flags);
+
usleep_range(1000, 2000);
+
+ spin_lock_irqsave(&priv->lock, flags);
+ val = readl(np_base + REG_RESET_CONTROL1);
writel(val | mask, np_base + REG_RESET_CONTROL1);
+ spin_unlock_irqrestore(&priv->lock, flags);
+
msleep(100);
+
+ spin_lock_irqsave(&priv->lock, flags);
+ val = readl(np_base + REG_RESET_CONTROL1);
writel(val & ~mask, np_base + REG_RESET_CONTROL1);
+ spin_unlock_irqrestore(&priv->lock, flags);
+
usleep_range(5000, 10000);
/* Release device */
- mask = REG_PCI_CONTROL_PERSTOUT1 | REG_PCI_CONTROL_PERSTOUT;
+ spin_lock_irqsave(&priv->lock, flags);
val = readl(np_base + REG_PCI_CONTROL);
+ mask = REG_PCI_CONTROL_PERSTOUT1 | REG_PCI_CONTROL_PERSTOUT;
writel(val & ~mask, np_base + REG_PCI_CONTROL);
+ spin_unlock_irqrestore(&priv->lock, flags);
+
usleep_range(1000, 2000);
+
+ spin_lock_irqsave(&priv->lock, flags);
+ val = readl(np_base + REG_PCI_CONTROL);
writel(val | mask, np_base + REG_PCI_CONTROL);
+ spin_unlock_irqrestore(&priv->lock, flags);
+
msleep(250);
return 0;
@@ -623,12 +666,19 @@ static int en7523_pci_prepare(struct clk_hw *hw)
static void en7523_pci_unprepare(struct clk_hw *hw)
{
struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw);
+ struct device *dev = clk_hw_get_dev(hw);
void __iomem *np_base = cg->base;
+ struct en_clk_priv *priv;
+ unsigned long flags;
u32 val;
+ priv = dev_get_drvdata(dev);
+
+ spin_lock_irqsave(&priv->lock, flags);
val = readl(np_base + REG_PCI_CONTROL);
val &= ~REG_PCI_CONTROL_REFCLK_EN1;
writel(val, np_base + REG_PCI_CONTROL);
+ spin_unlock_irqrestore(&priv->lock, flags);
}
static struct clk_hw *en7523_register_pcie_clk(struct device *dev,
@@ -660,22 +710,37 @@ static struct clk_hw *en7523_register_pcie_clk(struct device *dev,
static int en7581_pci_is_enabled(struct clk_hw *hw)
{
struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw);
+ struct device *dev = clk_hw_get_dev(hw);
+ struct en_clk_priv *priv;
+ unsigned long flags;
u32 val, mask;
+ priv = dev_get_drvdata(dev);
mask = REG_PCI_CONTROL_REFCLK_EN0 | REG_PCI_CONTROL_REFCLK_EN1;
+
+ spin_lock_irqsave(&priv->lock, flags);
val = readl(cg->base + REG_PCI_CONTROL);
+ spin_unlock_irqrestore(&priv->lock, flags);
+
return (val & mask) == mask;
}
static int en7581_pci_enable(struct clk_hw *hw)
{
struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw);
+ struct device *dev = clk_hw_get_dev(hw);
void __iomem *np_base = cg->base;
+ struct en_clk_priv *priv;
+ unsigned long flags;
u32 val, mask;
+ priv = dev_get_drvdata(dev);
mask = REG_PCI_CONTROL_REFCLK_EN0 | REG_PCI_CONTROL_REFCLK_EN1;
+
+ spin_lock_irqsave(&priv->lock, flags);
val = readl(np_base + REG_PCI_CONTROL);
writel(val | mask, np_base + REG_PCI_CONTROL);
+ spin_unlock_irqrestore(&priv->lock, flags);
return 0;
}
@@ -683,12 +748,20 @@ static int en7581_pci_enable(struct clk_hw *hw)
static void en7581_pci_disable(struct clk_hw *hw)
{
struct en_clk_gate *cg = container_of(hw, struct en_clk_gate, hw);
+ struct device *dev = clk_hw_get_dev(hw);
void __iomem *np_base = cg->base;
+ struct en_clk_priv *priv;
+ unsigned long flags;
u32 val, mask;
+ priv = dev_get_drvdata(dev);
mask = REG_PCI_CONTROL_REFCLK_EN0 | REG_PCI_CONTROL_REFCLK_EN1;
+
+ spin_lock_irqsave(&priv->lock, flags);
val = readl(np_base + REG_PCI_CONTROL);
writel(val & ~mask, np_base + REG_PCI_CONTROL);
+ spin_unlock_irqrestore(&priv->lock, flags);
+
usleep_range(1000, 2000);
}
@@ -788,21 +861,25 @@ static int en7523_reset_update(struct reset_controller_dev *rcdev,
unsigned long id, bool assert)
{
struct en_rst_data *rst_data = container_of(rcdev, struct en_rst_data, rcdev);
+ struct en_clk_priv *priv = dev_get_drvdata(rcdev->dev);
u32 offset = rst_data->bank_ofs[id / RST_NR_PER_BANK];
void __iomem *addr = rst_data->base + offset;
bool inverted = false;
+ unsigned long flags;
u32 val;
/* For PCIC reset logic is inverted, 0:assert 1:deassert */
if (offset == REG_NP_SCU_PCIC)
inverted = true;
+ spin_lock_irqsave(&priv->lock, flags);
val = readl(addr);
if (assert ^ inverted)
val |= BIT(id % RST_NR_PER_BANK);
else
val &= ~BIT(id % RST_NR_PER_BANK);
writel(val, addr);
+ spin_unlock_irqrestore(&priv->lock, flags);
return 0;
}
@@ -823,16 +900,21 @@ static int en7523_reset_status(struct reset_controller_dev *rcdev,
unsigned long id)
{
struct en_rst_data *rst_data = container_of(rcdev, struct en_rst_data, rcdev);
+ struct en_clk_priv *priv = dev_get_drvdata(rcdev->dev);
u32 offset = rst_data->bank_ofs[id / RST_NR_PER_BANK];
void __iomem *addr = rst_data->base + offset;
bool inverted = false;
+ unsigned long flags;
u32 val;
/* For PCIC reset logic is inverted, 0:assert 1:deassert */
if (offset == REG_NP_SCU_PCIC)
inverted = true;
+ spin_lock_irqsave(&priv->lock, flags);
val = readl(addr) & BIT(id % RST_NR_PER_BANK);
+ spin_unlock_irqrestore(&priv->lock, flags);
+
return inverted ? !val : !!val;
}
--
2.55.0
^ permalink raw reply [flat|nested] 6+ messages in thread* [PATCH v11 5/5] clk: en7523: add support for Airoha AN7583 clock
2026-11-06 11:58 [PATCH v11 0/5] clk: add support for Airoha AN7583 clock Christian Marangi
` (3 preceding siblings ...)
2026-11-06 11:58 ` [PATCH v11 4/5] clk: en7523: generalize register clocks function Christian Marangi
@ 2026-11-06 11:58 ` Christian Marangi
4 siblings, 0 replies; 6+ messages in thread
From: Christian Marangi @ 2026-11-06 11:58 UTC (permalink / raw)
To: Stephen Boyd, Brian Masney, Jerome Brunet, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Philipp Zabel, Felix Fietkau,
linux-clk, devicetree, linux-kernel
Cc: Christian Marangi
Add support for Airoha AN7583 clock and reset.
Airoha AN7583 SoC have the same register address of EN7581 but implement
different bits and additional base clocks. Also reset are different with
the introduction of 2 dedicated MDIO line and drop of some reset lines.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
drivers/clk/clk-en7523.c | 249 +++++++++++++++++++++++++++++++++++++++
1 file changed, 249 insertions(+)
diff --git a/drivers/clk/clk-en7523.c b/drivers/clk/clk-en7523.c
index 8e24eef651a1..821a5f5ad4d8 100644
--- a/drivers/clk/clk-en7523.c
+++ b/drivers/clk/clk-en7523.c
@@ -13,6 +13,7 @@
#include <linux/reset-controller.h>
#include <linux/spinlock.h>
#include <dt-bindings/clock/en7523-clk.h>
+#include <dt-bindings/reset/airoha,an7583-reset.h>
#include <dt-bindings/reset/airoha,en7523-reset.h>
#include <dt-bindings/reset/airoha,en7581-reset.h>
#include <dt-bindings/clock/econet,en751221-scu.h>
@@ -166,6 +167,14 @@ static const u32 crypto_base[] = { 540000000, 480000000 };
static const u32 emmc7581_base[] = { 200000000, 150000000 };
/* EN751221 */
static const u32 gsw751221_base[] = { 500000000, 250000000, 400000000, 200000000 };
+/* AN7583 */
+static const u32 gsw7583_base[] = { 540672000, 270336000, 400000000, 200000000 };
+static const u32 emi7583_base[] = { 540672000, 480000000, 400000000, 300000000 };
+static const u32 bus7583_base[] = { 600000000, 540672000, 480000000, 400000000 };
+static const u32 spi7583_base[] = { 400000000, 12500000 };
+static const u32 npu7583_base[] = { 666000000, 800000000, 720000000, 600000000 };
+static const u32 crypto7583_base[] = { 540672000, 400000000 };
+static const u32 emmc7583_base[] = { 150000000, 200000000 };
static const struct en_clk_desc en7523_base_clks[] = {
{
@@ -368,6 +377,138 @@ static const struct en_clk_desc en7581_base_clks[] = {
}
};
+static const struct en_clk_desc an7583_base_clks[] = {
+ {
+ .id = EN7523_CLK_GSW,
+ .name = "gsw",
+
+ .base_reg = REG_GSW_CLK_DIV_SEL,
+ .base_bits = 2,
+ .base_shift = 8,
+ .base_values = gsw7583_base,
+ .n_base_values = ARRAY_SIZE(gsw7583_base),
+
+ .div_bits = 3,
+ .div_shift = 0,
+ .div_step = 1,
+ .div_offset = 1,
+ }, {
+ .id = EN7523_CLK_EMI,
+ .name = "emi",
+
+ .base_reg = REG_EMI_CLK_DIV_SEL,
+ .base_bits = 2,
+ .base_shift = 8,
+ .base_values = emi7583_base,
+ .n_base_values = ARRAY_SIZE(emi7583_base),
+
+ .div_bits = 3,
+ .div_shift = 0,
+ .div_step = 1,
+ .div_offset = 1,
+ }, {
+ .id = EN7523_CLK_BUS,
+ .name = "bus",
+
+ .base_reg = REG_BUS_CLK_DIV_SEL,
+ .base_bits = 2,
+ .base_shift = 8,
+ .base_values = bus7583_base,
+ .n_base_values = ARRAY_SIZE(bus7583_base),
+
+ .div_bits = 3,
+ .div_shift = 0,
+ .div_step = 1,
+ .div_offset = 1,
+ }, {
+ .id = EN7523_CLK_SLIC,
+ .name = "slic",
+
+ .base_reg = REG_SPI_CLK_FREQ_SEL,
+ .base_bits = 1,
+ .base_shift = 1,
+ .base_values = slic_base,
+ .n_base_values = ARRAY_SIZE(slic_base),
+
+ .div_reg = REG_SPI_CLK_DIV_SEL,
+ .div_bits = 5,
+ .div_shift = 24,
+ .div_val0 = 20,
+ .div_step = 2,
+ }, {
+ .id = EN7523_CLK_SPI,
+ .name = "spi",
+
+ .base_reg = REG_SPI_CLK_FREQ_SEL,
+ .base_bits = 1,
+ .base_shift = 0,
+ .base_values = spi7583_base,
+ .n_base_values = ARRAY_SIZE(spi7583_base),
+
+ .div_reg = REG_SPI_CLK_DIV_SEL,
+ .div_bits = 5,
+ .div_shift = 8,
+ .div_val0 = 40,
+ .div_step = 2,
+ }, {
+ .id = EN7523_CLK_NPU,
+ .name = "npu",
+
+ .base_reg = REG_NPU_CLK_DIV_SEL,
+ .base_bits = 2,
+ .base_shift = 9,
+ .base_values = npu7583_base,
+ .n_base_values = ARRAY_SIZE(npu7583_base),
+
+ .div_bits = 3,
+ .div_shift = 0,
+ .div_step = 1,
+ .div_offset = 1,
+ }, {
+ .id = EN7523_CLK_CRYPTO,
+ .name = "crypto",
+
+ .base_reg = REG_CRYPTO_CLKSRC2,
+ .base_bits = 1,
+ .base_shift = 0,
+ .base_values = crypto7583_base,
+ .n_base_values = ARRAY_SIZE(crypto7583_base),
+ }, {
+ .id = EN7581_CLK_EMMC,
+ .name = "emmc",
+
+ .base_reg = REG_CRYPTO_CLKSRC2,
+ .base_bits = 1,
+ .base_shift = 13,
+ .base_values = emmc7583_base,
+ .n_base_values = ARRAY_SIZE(emmc7583_base),
+ }, {
+ .id = AN7583_CLK_MDIO0,
+ .name = "mdio0",
+
+ .base_reg = REG_CRYPTO_CLKSRC2,
+
+ .base_value = 25000000,
+
+ .div_bits = 4,
+ .div_shift = 15,
+ .div_step = 1,
+ .div_offset = 1,
+ }, {
+ .id = AN7583_CLK_MDIO1,
+ .name = "mdio1",
+
+ .base_reg = REG_CRYPTO_CLKSRC2,
+
+ .base_value = 25000000,
+
+ .div_bits = 4,
+ .div_shift = 19,
+ .div_step = 1,
+ .div_offset = 1,
+ }
+};
+
static const u16 en7581_rst_ofs[] = {
REG_RST_CTRL2,
REG_RST_CTRL1,
@@ -543,6 +684,64 @@ static const u16 en751221_rst_map[] = {
[EN751221_USB_PHY_P1_RST] = 3 * RST_NR_PER_BANK + 7,
};
+static const u16 an7583_rst_map[] = {
+ /* RST_CTRL2 */
+ [AN7583_XPON_PHY_RST] = 0,
+ [AN7583_GPON_OLT_RST] = 1,
+ [AN7583_CPU_TIMER2_RST] = 2,
+ [AN7583_HSUART_RST] = 3,
+ [AN7583_UART4_RST] = 4,
+ [AN7583_UART5_RST] = 5,
+ [AN7583_I2C2_RST] = 6,
+ [AN7583_XSI_MAC_RST] = 7,
+ [AN7583_XSI_PHY_RST] = 8,
+ [AN7583_NPU_RST] = 9,
+ [AN7583_TRNG_MSTART_RST] = 12,
+ [AN7583_DUAL_HSI0_RST] = 13,
+ [AN7583_DUAL_HSI1_RST] = 14,
+ [AN7583_DUAL_HSI0_MAC_RST] = 16,
+ [AN7583_DUAL_HSI1_MAC_RST] = 17,
+ [AN7583_XPON_XFI_RST] = 18,
+ [AN7583_WDMA_RST] = 19,
+ [AN7583_WOE0_RST] = 20,
+ [AN7583_HSDMA_RST] = 22,
+ [AN7583_TDMA_RST] = 24,
+ [AN7583_EMMC_RST] = 25,
+ [AN7583_SOE_RST] = 26,
+ [AN7583_XFP_MAC_RST] = 28,
+ [AN7583_MDIO0_RST] = 30,
+ [AN7583_MDIO1_RST] = 31,
+ /* RST_CTRL1 */
+ [AN7583_PCM1_ZSI_ISI_RST] = RST_NR_PER_BANK + 0,
+ [AN7583_FE_PDMA_RST] = RST_NR_PER_BANK + 1,
+ [AN7583_FE_QDMA_RST] = RST_NR_PER_BANK + 2,
+ [AN7583_PCM_SPIWP_RST] = RST_NR_PER_BANK + 4,
+ [AN7583_CRYPTO_RST] = RST_NR_PER_BANK + 6,
+ [AN7583_TIMER_RST] = RST_NR_PER_BANK + 8,
+ [AN7583_PCM1_RST] = RST_NR_PER_BANK + 11,
+ [AN7583_UART_RST] = RST_NR_PER_BANK + 12,
+ [AN7583_GPIO_RST] = RST_NR_PER_BANK + 13,
+ [AN7583_GDMA_RST] = RST_NR_PER_BANK + 14,
+ [AN7583_I2C_MASTER_RST] = RST_NR_PER_BANK + 16,
+ [AN7583_PCM2_ZSI_ISI_RST] = RST_NR_PER_BANK + 17,
+ [AN7583_SFC_RST] = RST_NR_PER_BANK + 18,
+ [AN7583_UART2_RST] = RST_NR_PER_BANK + 19,
+ [AN7583_GDMP_RST] = RST_NR_PER_BANK + 20,
+ [AN7583_FE_RST] = RST_NR_PER_BANK + 21,
+ [AN7583_USB_HOST_P0_RST] = RST_NR_PER_BANK + 22,
+ [AN7583_GSW_RST] = RST_NR_PER_BANK + 23,
+ [AN7583_SFC2_PCM_RST] = RST_NR_PER_BANK + 25,
+ [AN7583_PCIE0_RST] = RST_NR_PER_BANK + 26,
+ [AN7583_PCIE1_RST] = RST_NR_PER_BANK + 27,
+ [AN7583_CPU_TIMER_RST] = RST_NR_PER_BANK + 28,
+ [AN7583_PCIE_HB_RST] = RST_NR_PER_BANK + 29,
+ [AN7583_XPON_MAC_RST] = RST_NR_PER_BANK + 31,
+
+ /* RST_PCIC */
+ [AN7583_PCIC_PERSTOUT0_RST] = 2 * RST_NR_PER_BANK + 29,
+ [AN7583_PCIC_PERSTOUT1_RST] = 2 * RST_NR_PER_BANK + 26,
+};
+
static int en7581_reset_register(struct device *dev, void __iomem *base,
const u16 *rst_map, int nr_resets,
const u16 *rst_reg_ofs);
@@ -1170,6 +1369,43 @@ static int en7581_clk_hw_init(struct platform_device *pdev,
return en7581_serdes_phy_register(&pdev->dev);
}
+static int an7583_clk_hw_init(struct platform_device *pdev,
+ struct clk_hw_onecell_data *clk_data)
+{
+ struct en_clk_priv *priv = platform_get_drvdata(pdev);
+ struct device *dev = &pdev->dev;
+ struct regmap *map;
+ void __iomem *base;
+ u32 val;
+ int ret;
+
+ map = syscon_regmap_lookup_by_phandle(dev->of_node, "airoha,chip-scu");
+ if (IS_ERR(map))
+ return PTR_ERR(map);
+
+ base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ priv->base = base;
+
+ en7581_register_clocks(dev, clk_data, map, base);
+
+ val = readl(base + REG_RST_CTRL1);
+ val |= REG_PCIE_HB_RST;
+ writel(val, base + REG_RST_CTRL1);
+ val &= ~REG_PCIE_HB_RST;
+ writel(val, base + REG_RST_CTRL1);
+
+ ret = en7581_reset_register(dev, base, an7583_rst_map,
+ ARRAY_SIZE(an7583_rst_map),
+ en7581_rst_ofs);
+ if (ret)
+ return ret;
+
+ return en7581_serdes_phy_register(dev);
+}
+
static enum en_hir get_hw_id(void __iomem *np_base)
{
u32 val = FIELD_GET(REG_HIR_MASK, readl(np_base + REG_HIR));
@@ -1323,6 +1559,18 @@ static const struct en_clk_soc_data en7581_data = {
.hw_init = en7581_clk_hw_init,
};
+static const struct en_clk_soc_data an7583_data = {
+ .base_clks = an7583_base_clks,
+ /* We increment num_clocks by 1 to account for additional PCIe clock */
+ .num_clocks = ARRAY_SIZE(an7583_base_clks) + 1,
+ .pcie_ops = {
+ .is_enabled = en7581_pci_is_enabled,
+ .prepare = en7581_pci_enable,
+ .unprepare = en7581_pci_disable,
+ },
+ .hw_init = an7583_clk_hw_init,
+};
+
static const struct en_clk_soc_data en751221_data = {
.num_clocks = EN751221_MAX_CLKS,
.pcie_ops = {
@@ -1336,6 +1584,7 @@ static const struct en_clk_soc_data en751221_data = {
static const struct of_device_id of_match_clk_en7523[] = {
{ .compatible = "airoha,en7523-scu", .data = &en7523_data },
{ .compatible = "airoha,en7581-scu", .data = &en7581_data },
+ { .compatible = "airoha,an7583-scu", .data = &an7583_data },
{ .compatible = "econet,en751221-scu", .data = &en751221_data },
{ /* sentinel */ }
};
--
2.55.0
^ permalink raw reply [flat|nested] 6+ messages in thread