* [PATCH 1/3] dt-bindings: cpufreq: cpufreq-qcom-hw: Add SM6125 compatible
2026-11-15 0:31 [PATCH 0/3] arm64: dts: qcom: sm6125: Add cpufreq-hw and CPU idle states Majid Hajiheidari
@ 2026-11-15 0:31 ` Majid Hajiheidari
2026-11-15 0:31 ` [PATCH 2/3] arm64: dts: qcom: sm6125: Add cpufreq-hw node Majid Hajiheidari
2026-11-15 0:31 ` [PATCH 3/3] arm64: dts: qcom: sm6125: Add CPU idle states Majid Hajiheidari
2 siblings, 0 replies; 4+ messages in thread
From: Majid Hajiheidari @ 2026-11-15 0:31 UTC (permalink / raw)
To: andersson, konradybcio
Cc: rafael, viresh.kumar, robh, krzk+dt, conor+dt, abelvesa, mani,
admin, linux-arm-msm, linux-pm, devicetree, linux-kernel
Document the cpufreq-hw (OSM) block on SM6125. Like SM6115 it has two
frequency domains with one register region each, so add it to both the
compatible list and the two-region constraint.
Signed-off-by: Majid Hajiheidari <majidhhdri@gmail.com>
---
Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml
index 98eb36bff..8dfe77d08 100644
--- a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml
+++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml
@@ -28,6 +28,7 @@ properties:
- qcom,sdm670-cpufreq-hw
- qcom,sdm845-cpufreq-hw
- qcom,sm6115-cpufreq-hw
+ - qcom,sm6125-cpufreq-hw
- qcom,sm6350-cpufreq-hw
- qcom,sm8150-cpufreq-hw
- const: qcom,cpufreq-hw
@@ -146,6 +147,7 @@ allOf:
- qcom,sdm845-cpufreq-hw
- qcom,sm4450-cpufreq-epss
- qcom,sm6115-cpufreq-hw
+ - qcom,sm6125-cpufreq-hw
- qcom,sm6350-cpufreq-hw
- qcom,sm6375-cpufreq-epss
then:
--
2.56.1
^ permalink raw reply [flat|nested] 4+ messages in thread* [PATCH 2/3] arm64: dts: qcom: sm6125: Add cpufreq-hw node
2026-11-15 0:31 [PATCH 0/3] arm64: dts: qcom: sm6125: Add cpufreq-hw and CPU idle states Majid Hajiheidari
2026-11-15 0:31 ` [PATCH 1/3] dt-bindings: cpufreq: cpufreq-qcom-hw: Add SM6125 compatible Majid Hajiheidari
@ 2026-11-15 0:31 ` Majid Hajiheidari
2026-11-15 0:31 ` [PATCH 3/3] arm64: dts: qcom: sm6125: Add CPU idle states Majid Hajiheidari
2 siblings, 0 replies; 4+ messages in thread
From: Majid Hajiheidari @ 2026-11-15 0:31 UTC (permalink / raw)
To: andersson, konradybcio
Cc: rafael, viresh.kumar, robh, krzk+dt, conor+dt, abelvesa, mani,
admin, linux-arm-msm, linux-pm, devicetree, linux-kernel
SM6125 has the same cpufreq-hw (OSM) blocks as SM6115, at 0xf521000
(silver cluster) and 0xf523000 (gold cluster), per the downstream
"trinket" device tree. Describe them and hook up the CPUs so the
frequency can scale instead of staying at the bootloader setting.
GCC on SM6125 has no plain GPLL0 output; GPLL0_OUT_EARLY is the PLL
itself and is used as the alternate source.
Tested on a Xiaomi Mi A3: policy0 300 MHz - 1.80 GHz, policy4
300 MHz - 2.02 GHz, scaling with schedutil; a single gold core holds
1998 MHz under 7-Zip.
Signed-off-by: Majid Hajiheidari <majidhhdri@gmail.com>
---
arch/arm64/boot/dts/qcom/sm6125.dtsi | 29 ++++++++++++++++++++++++++++
1 file changed, 29 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi
index 5f558b548..1b148e453 100644
--- a/arch/arm64/boot/dts/qcom/sm6125.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi
@@ -43,6 +43,8 @@ cpu0: cpu@0 {
compatible = "qcom,kryo260";
reg = <0x0 0x0>;
enable-method = "psci";
+ clocks = <&cpufreq_hw 0>;
+ qcom,freq-domain = <&cpufreq_hw 0>;
capacity-dmips-mhz = <1024>;
next-level-cache = <&l2_0>;
l2_0: l2-cache {
@@ -57,6 +59,8 @@ cpu1: cpu@1 {
compatible = "qcom,kryo260";
reg = <0x0 0x1>;
enable-method = "psci";
+ clocks = <&cpufreq_hw 0>;
+ qcom,freq-domain = <&cpufreq_hw 0>;
capacity-dmips-mhz = <1024>;
next-level-cache = <&l2_0>;
};
@@ -66,6 +70,8 @@ cpu2: cpu@2 {
compatible = "qcom,kryo260";
reg = <0x0 0x2>;
enable-method = "psci";
+ clocks = <&cpufreq_hw 0>;
+ qcom,freq-domain = <&cpufreq_hw 0>;
capacity-dmips-mhz = <1024>;
next-level-cache = <&l2_0>;
};
@@ -75,6 +81,8 @@ cpu3: cpu@3 {
compatible = "qcom,kryo260";
reg = <0x0 0x3>;
enable-method = "psci";
+ clocks = <&cpufreq_hw 0>;
+ qcom,freq-domain = <&cpufreq_hw 0>;
capacity-dmips-mhz = <1024>;
next-level-cache = <&l2_0>;
};
@@ -84,6 +92,8 @@ cpu4: cpu@100 {
compatible = "qcom,kryo260";
reg = <0x0 0x100>;
enable-method = "psci";
+ clocks = <&cpufreq_hw 1>;
+ qcom,freq-domain = <&cpufreq_hw 1>;
capacity-dmips-mhz = <1638>;
next-level-cache = <&l2_1>;
l2_1: l2-cache {
@@ -98,6 +108,8 @@ cpu5: cpu@101 {
compatible = "qcom,kryo260";
reg = <0x0 0x101>;
enable-method = "psci";
+ clocks = <&cpufreq_hw 1>;
+ qcom,freq-domain = <&cpufreq_hw 1>;
capacity-dmips-mhz = <1638>;
next-level-cache = <&l2_1>;
};
@@ -107,6 +119,8 @@ cpu6: cpu@102 {
compatible = "qcom,kryo260";
reg = <0x0 0x102>;
enable-method = "psci";
+ clocks = <&cpufreq_hw 1>;
+ qcom,freq-domain = <&cpufreq_hw 1>;
capacity-dmips-mhz = <1638>;
next-level-cache = <&l2_1>;
};
@@ -116,6 +130,8 @@ cpu7: cpu@103 {
compatible = "qcom,kryo260";
reg = <0x0 0x103>;
enable-method = "psci";
+ clocks = <&cpufreq_hw 1>;
+ qcom,freq-domain = <&cpufreq_hw 1>;
capacity-dmips-mhz = <1638>;
next-level-cache = <&l2_1>;
};
@@ -1633,6 +1649,19 @@ intc: interrupt-controller@f200000 {
interrupt-controller;
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
};
+
+ cpufreq_hw: cpufreq@f521000 {
+ compatible = "qcom,sm6125-cpufreq-hw", "qcom,cpufreq-hw";
+ reg = <0x0 0x0f521000 0x0 0x1000>,
+ <0x0 0x0f523000 0x0 0x1000>;
+ reg-names = "freq-domain0", "freq-domain1";
+
+ clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0_OUT_EARLY>;
+ clock-names = "xo", "alternate";
+
+ #freq-domain-cells = <1>;
+ #clock-cells = <1>;
+ };
};
timer {
--
2.56.1
^ permalink raw reply [flat|nested] 4+ messages in thread* [PATCH 3/3] arm64: dts: qcom: sm6125: Add CPU idle states
2026-11-15 0:31 [PATCH 0/3] arm64: dts: qcom: sm6125: Add cpufreq-hw and CPU idle states Majid Hajiheidari
2026-11-15 0:31 ` [PATCH 1/3] dt-bindings: cpufreq: cpufreq-qcom-hw: Add SM6125 compatible Majid Hajiheidari
2026-11-15 0:31 ` [PATCH 2/3] arm64: dts: qcom: sm6125: Add cpufreq-hw node Majid Hajiheidari
@ 2026-11-15 0:31 ` Majid Hajiheidari
2 siblings, 0 replies; 4+ messages in thread
From: Majid Hajiheidari @ 2026-11-15 0:31 UTC (permalink / raw)
To: andersson, konradybcio
Cc: rafael, viresh.kumar, robh, krzk+dt, conor+dt, abelvesa, mani,
admin, linux-arm-msm, linux-pm, devicetree, linux-kernel
Add per-CPU power collapse states. The downstream "trinket" low power
levels use exactly the SM6115 numbers (silver: entry 290 us, exit
376 us, min residency 1182 us; gold: 297/324/1110 us; PSCI CPU mode 3),
so reuse them in platform-coordinated mode.
Cluster (domain) idle states are left for later; their PSCI parameters
still need to be checked against the downstream levels.
Tested on a Xiaomi Mi A3: WFI and cpu-sleep-N-0 show up in cpuidle and
the usage counters increase.
Signed-off-by: Majid Hajiheidari <majidhhdri@gmail.com>
---
arch/arm64/boot/dts/qcom/sm6125.dtsi | 32 ++++++++++++++++++++++++++++
1 file changed, 32 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm6125.dtsi b/arch/arm64/boot/dts/qcom/sm6125.dtsi
index 1b148e453..c06842c0c 100644
--- a/arch/arm64/boot/dts/qcom/sm6125.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6125.dtsi
@@ -44,6 +44,7 @@ cpu0: cpu@0 {
reg = <0x0 0x0>;
enable-method = "psci";
clocks = <&cpufreq_hw 0>;
+ cpu-idle-states = <&little_cpu_sleep_0>;
qcom,freq-domain = <&cpufreq_hw 0>;
capacity-dmips-mhz = <1024>;
next-level-cache = <&l2_0>;
@@ -60,6 +61,7 @@ cpu1: cpu@1 {
reg = <0x0 0x1>;
enable-method = "psci";
clocks = <&cpufreq_hw 0>;
+ cpu-idle-states = <&little_cpu_sleep_0>;
qcom,freq-domain = <&cpufreq_hw 0>;
capacity-dmips-mhz = <1024>;
next-level-cache = <&l2_0>;
@@ -71,6 +73,7 @@ cpu2: cpu@2 {
reg = <0x0 0x2>;
enable-method = "psci";
clocks = <&cpufreq_hw 0>;
+ cpu-idle-states = <&little_cpu_sleep_0>;
qcom,freq-domain = <&cpufreq_hw 0>;
capacity-dmips-mhz = <1024>;
next-level-cache = <&l2_0>;
@@ -82,6 +85,7 @@ cpu3: cpu@3 {
reg = <0x0 0x3>;
enable-method = "psci";
clocks = <&cpufreq_hw 0>;
+ cpu-idle-states = <&little_cpu_sleep_0>;
qcom,freq-domain = <&cpufreq_hw 0>;
capacity-dmips-mhz = <1024>;
next-level-cache = <&l2_0>;
@@ -93,6 +97,7 @@ cpu4: cpu@100 {
reg = <0x0 0x100>;
enable-method = "psci";
clocks = <&cpufreq_hw 1>;
+ cpu-idle-states = <&big_cpu_sleep_0>;
qcom,freq-domain = <&cpufreq_hw 1>;
capacity-dmips-mhz = <1638>;
next-level-cache = <&l2_1>;
@@ -109,6 +114,7 @@ cpu5: cpu@101 {
reg = <0x0 0x101>;
enable-method = "psci";
clocks = <&cpufreq_hw 1>;
+ cpu-idle-states = <&big_cpu_sleep_0>;
qcom,freq-domain = <&cpufreq_hw 1>;
capacity-dmips-mhz = <1638>;
next-level-cache = <&l2_1>;
@@ -120,6 +126,7 @@ cpu6: cpu@102 {
reg = <0x0 0x102>;
enable-method = "psci";
clocks = <&cpufreq_hw 1>;
+ cpu-idle-states = <&big_cpu_sleep_0>;
qcom,freq-domain = <&cpufreq_hw 1>;
capacity-dmips-mhz = <1638>;
next-level-cache = <&l2_1>;
@@ -131,6 +138,7 @@ cpu7: cpu@103 {
reg = <0x0 0x103>;
enable-method = "psci";
clocks = <&cpufreq_hw 1>;
+ cpu-idle-states = <&big_cpu_sleep_0>;
qcom,freq-domain = <&cpufreq_hw 1>;
capacity-dmips-mhz = <1638>;
next-level-cache = <&l2_1>;
@@ -173,6 +181,30 @@ core3 {
};
};
};
+
+ idle-states {
+ entry-method = "psci";
+
+ little_cpu_sleep_0: cpu-sleep-0-0 {
+ compatible = "arm,idle-state";
+ idle-state-name = "silver-rail-power-collapse";
+ arm,psci-suspend-param = <0x40000003>;
+ entry-latency-us = <290>;
+ exit-latency-us = <376>;
+ min-residency-us = <1182>;
+ local-timer-stop;
+ };
+
+ big_cpu_sleep_0: cpu-sleep-1-0 {
+ compatible = "arm,idle-state";
+ idle-state-name = "gold-rail-power-collapse";
+ arm,psci-suspend-param = <0x40000003>;
+ entry-latency-us = <297>;
+ exit-latency-us = <324>;
+ min-residency-us = <1110>;
+ local-timer-stop;
+ };
+ };
};
firmware {
--
2.56.1
^ permalink raw reply [flat|nested] 4+ messages in thread