Re: [PATCH 1/4] mmc: sdhci-cadence6: add PHY settle delay after tuning DLL re-lock

["NG, TZE YEE" <tze.yee.ng@altera.com>]

On 24/9/2026 2:41 pm, Adrian Hunter wrote:
> On 22/09/2026 14:12, tze.yee.ng@altera.com wrote:
>> From: Tze Yee Ng <tze.yee.ng@altera.com>
>>
>> After re-locking the DLL, allow the same 5 to 5.5 ms for the clock and
>> PHY signals to stabilize as sdhci_cdns6_phy_init() does. Without this
>> settle time the command issued immediately after tuning (e.g. the R1b
>> CMD6 that switches eMMC from HS200 down to HS during HS400 selection)
>> can time out.
>>
>> Signed-off-by: Tze Yee Ng <tze.yee.ng@altera.com>
> 
> Presume you realize the delay is inside the tuning loop, so 40x 5ms
> is 200ms total.
> 
> Nevertheless:
> 
> Acked-by: Adrian Hunter <adrian.hunter@intel.com>
> 

Thanks for the Ack, and you are right about the cost. The v1 placement 
put the 5 ms inside the tuning scan, so ~40x ≈ 200 ms. In v2, I will 
move it to a single settle after the winning tap in 
sdhci_cdns_execute_tuning() (5 ms once, success path only) and reworks 
the rationale per Tanmay's comments.

Since v2 changes both the placement and the file it touches, I won't
carry your Acked-by forward automatically - please let me know if it
still stands on the reworked patch.

Thanks,
Tze Yee

>> ---
>>   drivers/mmc/host/sdhci-cadence-phy-v6.c | 3 +++
>>   1 file changed, 3 insertions(+)
>>
>> diff --git a/drivers/mmc/host/sdhci-cadence-phy-v6.c b/drivers/mmc/host/sdhci-cadence-phy-v6.c
>> index 22d56bb46d75..35f35ef9c710 100644
>> --- a/drivers/mmc/host/sdhci-cadence-phy-v6.c
>> +++ b/drivers/mmc/host/sdhci-cadence-phy-v6.c
>> @@ -811,6 +811,9 @@ int sdhci_cdns6_set_tune_val(struct sdhci_host *host, unsigned int val)
>>   	if (ret)
>>   		dev_warn(mmc_dev(host->mmc), "%s: DLL reset release failed: %d\n", __func__, ret);
>>   
>> +	/* Allow 5 to 5.5 ms for clock and PHY signals to stabilize after configuration */
>> +	usleep_range(5000, 5500);
>> +
>>   	return ret;
>>   }
>>   
>