Re: [PATCH 1/4] mmc: sdhci-cadence6: add PHY settle delay after tuning DLL re-lock

["NG, TZE YEE" <tze.yee.ng@altera.com>]

On 26/9/2026 6:44 pm, Kathpalia, Tanmay wrote:
> 
> On 22-09-2026 16:42, tze.yee.ng@altera.com wrote:
>> From: Tze Yee Ng<tze.yee.ng@altera.com>
>>
>> After re-locking the DLL, allow the same 5 to 5.5 ms for the clock and
>> PHY signals to stabilize as sdhci_cdns6_phy_init() does. Without this
>> settle time the command issued immediately after tuning (e.g. the R1b
>> CMD6 that switches eMMC from HS200 down to HS during HS400 selection)
>> can time out.
> 
> One additional concern is that the testing listed in the cover letter 
> does not
> exercise the paths described here. The series reports testing SD DDR50 
> and eMMC
> DDR52, but neither mode performs tuning through sdhci_cdns6_set_tune_val().
> 

Correct. DDR50/DDR52 don't run execute_tuning(). This path is only hit 
by eMMC HS200/HS400 and SD SDR104, so I'll rescope the cover letter.

> Please test this change with eMMC HS200 and HS400. The same function is 
> also
> used during SD SDR104 tuning, so SDR104 should be covered as well.

eMMC HS200/HS400 is covered: HS400 selection runs HS200 tuning first, 
and the retest goes through that path - "mmc0: new HS400 MMC card", with 
the HS200->HS CMD6 that used to return -110 now passing.

Thanks,
Tze Yee