* [PATCH v2 1/7] arm64: dts: ti: k3-am64-main: switch to 64-bit address space for PCIe0
2025-04-22 12:00 [PATCH v2 0/7] AM64 and J7X DT: Enable PCIe 64-bit Address Space Siddharth Vadapalli
@ 2025-04-22 12:00 ` Siddharth Vadapalli
2025-04-22 12:00 ` [PATCH v2 2/7] arm64: dts: ti: k3-j7200-main: switch to 64-bit address space for PCIe1 Siddharth Vadapalli
` (7 subsequent siblings)
8 siblings, 0 replies; 12+ messages in thread
From: Siddharth Vadapalli @ 2025-04-22 12:00 UTC (permalink / raw)
To: nm, vigneshr, kristo, robh, krzk+dt, conor+dt, u-kumar1
Cc: devicetree, linux-kernel, linux-arm-kernel, srk, s-vadapalli
The PCIe0 instance of PCIe in AM64 SoC supports:
1. 128 MB address region in the 32-bit address space
2. 4 GB address region in the 64-bit address space
The default configuration is that of a 128 MB address region in the
32-bit address space. While this might be sufficient for most use-cases,
it is insufficient for supporting use-cases which require larger address
spaces. Therefore, switch to using the 64-bit address space with a 4 GB
address region.
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
---
Link to v1 patch:
https://lore.kernel.org/r/20250417120407.2646929-2-s-vadapalli@ti.com/
Changes since v1:
- Based on Udit's feedback and offline discussion as described at:
https://lore.kernel.org/r/7f6ea98c-df6d-4c94-8f42-76cc8306b6c4@ti.com/
the address region of 4 GB is split as:
0. 4 KB ECAM
1. 1 MB IO
2. (4 GB - 1 MB - 4 KB) 32-bit Non-Prefetchable MEM
instead of the previous split of:
0. 4 KB ECAM
1. 1 MB IO
2. 128 MB 32-bit Non-Prefetchable MEM
3. (4 GB - 129 MB - 4 KB) 64-bit Prefetchable MEM
Regards,
Siddharth.
arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
index 324eb44c258d..a22295ab4f9e 100644
--- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
@@ -1031,7 +1031,7 @@ pcie0_rc: pcie@f102000 {
reg = <0x00 0x0f102000 0x00 0x1000>,
<0x00 0x0f100000 0x00 0x400>,
<0x00 0x0d000000 0x00 0x00800000>,
- <0x00 0x68000000 0x00 0x00001000>;
+ <0x06 0x00000000 0x00 0x00001000>; /* ECAM (4 KB) */
reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
interrupt-names = "link_state";
interrupts = <GIC_SPI 203 IRQ_TYPE_EDGE_RISING>;
@@ -1049,8 +1049,8 @@ pcie0_rc: pcie@f102000 {
vendor-id = <0x104c>;
device-id = <0xb010>;
msi-map = <0x0 &gic_its 0x0 0x10000>;
- ranges = <0x01000000 0x00 0x68001000 0x00 0x68001000 0x00 0x0010000>,
- <0x02000000 0x00 0x68011000 0x00 0x68011000 0x00 0x7fef000>;
+ ranges = <0x01000000 0x00 0x00001000 0x06 0x00001000 0x00 0x00100000>, /* IO (1 MB) */
+ <0x02000000 0x00 0x00101000 0x06 0x00101000 0x00 0xffeff000>; /* 32-bit Non-Prefetchable MEM (4 GB - 1 MB - 4 KB) */
dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x00000010 0x0>;
status = "disabled";
};
--
2.34.1
^ permalink raw reply [flat|nested] 12+ messages in thread* [PATCH v2 2/7] arm64: dts: ti: k3-j7200-main: switch to 64-bit address space for PCIe1
2025-04-22 12:00 [PATCH v2 0/7] AM64 and J7X DT: Enable PCIe 64-bit Address Space Siddharth Vadapalli
2025-04-22 12:00 ` [PATCH v2 1/7] arm64: dts: ti: k3-am64-main: switch to 64-bit address space for PCIe0 Siddharth Vadapalli
@ 2025-04-22 12:00 ` Siddharth Vadapalli
2025-04-22 12:00 ` [PATCH v2 3/7] arm64: dts: ti: k3-j721e: add ranges for PCIe0 DAT1 and PCIe1 DAT1 Siddharth Vadapalli
` (6 subsequent siblings)
8 siblings, 0 replies; 12+ messages in thread
From: Siddharth Vadapalli @ 2025-04-22 12:00 UTC (permalink / raw)
To: nm, vigneshr, kristo, robh, krzk+dt, conor+dt, u-kumar1
Cc: devicetree, linux-kernel, linux-arm-kernel, srk, s-vadapalli
The PCIe0 instance of PCIe in J7200 SoC supports:
1. 128 MB address region in the 32-bit address space
2. 4 GB address region in the 64-bit address space
The default configuration is that of a 128 MB address region in the
32-bit address space. While this might be sufficient for most use-cases,
it is insufficient for supporting use-cases which require larger address
spaces. Therefore, switch to using the 64-bit address space with a 4 GB
address region.
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
---
Link to v1 patch:
https://lore.kernel.org/r/20250417120407.2646929-3-s-vadapalli@ti.com/
Changes since v1:
- Based on Udit's feedback and offline discussion as described at:
https://lore.kernel.org/r/7f6ea98c-df6d-4c94-8f42-76cc8306b6c4@ti.com/
the address region of 4 GB is split as:
0. 4 KB ECAM
1. 1 MB IO
2. (4 GB - 1 MB - 4 KB) 32-bit Non-Prefetchable MEM
instead of the previous split of:
0. 4 KB ECAM
1. 1 MB IO
2. 128 MB 32-bit Non-Prefetchable MEM
3. (4 GB - 129 MB - 4 KB) 64-bit Prefetchable MEM
Regards,
Siddharth.
arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
index 5ab510a0605f..21c3e574277c 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
@@ -759,7 +759,7 @@ pcie1_rc: pcie@2910000 {
reg = <0x00 0x02910000 0x00 0x1000>,
<0x00 0x02917000 0x00 0x400>,
<0x00 0x0d800000 0x00 0x00800000>,
- <0x00 0x18000000 0x00 0x00001000>;
+ <0x41 0x00000000 0x00 0x00001000>; /* ECAM (4 KB) */
reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
interrupt-names = "link_state";
interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
@@ -778,8 +778,8 @@ pcie1_rc: pcie@2910000 {
device-id = <0xb00f>;
msi-map = <0x0 &gic_its 0x0 0x10000>;
dma-coherent;
- ranges = <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>,
- <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>;
+ ranges = <0x01000000 0x00 0x00001000 0x41 0x00001000 0x00 0x00100000>, /* IO (1 MB) */
+ <0x02000000 0x00 0x00101000 0x41 0x00101000 0x00 0xffeff000>; /* 32-bit Non-Prefetchable MEM (4 GB - 1 MB - 4 KB) */
dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
status = "disabled";
};
--
2.34.1
^ permalink raw reply [flat|nested] 12+ messages in thread* [PATCH v2 3/7] arm64: dts: ti: k3-j721e: add ranges for PCIe0 DAT1 and PCIe1 DAT1
2025-04-22 12:00 [PATCH v2 0/7] AM64 and J7X DT: Enable PCIe 64-bit Address Space Siddharth Vadapalli
2025-04-22 12:00 ` [PATCH v2 1/7] arm64: dts: ti: k3-am64-main: switch to 64-bit address space for PCIe0 Siddharth Vadapalli
2025-04-22 12:00 ` [PATCH v2 2/7] arm64: dts: ti: k3-j7200-main: switch to 64-bit address space for PCIe1 Siddharth Vadapalli
@ 2025-04-22 12:00 ` Siddharth Vadapalli
2025-04-22 14:11 ` Kumar, Udit
2025-04-22 12:00 ` [PATCH v2 4/7] arm64: dts: ti: k3-j721e-main: switch to 64-bit address space for PCIe0 and PCIe1 Siddharth Vadapalli
` (5 subsequent siblings)
8 siblings, 1 reply; 12+ messages in thread
From: Siddharth Vadapalli @ 2025-04-22 12:00 UTC (permalink / raw)
To: nm, vigneshr, kristo, robh, krzk+dt, conor+dt, u-kumar1
Cc: devicetree, linux-kernel, linux-arm-kernel, srk, s-vadapalli
The PCIe0 DAT1 and PCIe1 DAT1 are 4 GB address regions in the 64-bit
address space of the respective PCIe Controllers. Hence, update the
ranges to include them.
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
---
Link to v1 patch:
https://lore.kernel.org/r/20250417120407.2646929-4-s-vadapalli@ti.com/
Changes since v1:
- Fixed the 'ranges' to set the size as 4 GB instead of the incorrect
value of 128 MB.
Regards,
Siddharth.
arch/arm64/boot/dts/ti/k3-j721e.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j721e.dtsi b/arch/arm64/boot/dts/ti/k3-j721e.dtsi
index a7f2f52f42f7..b6e22c242951 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e.dtsi
@@ -126,6 +126,8 @@ cbass_main: bus@100000 {
<0x00 0x10000000 0x00 0x10000000 0x00 0x10000000>, /* PCIe DAT */
<0x00 0x64800000 0x00 0x64800000 0x00 0x00800000>, /* C71 */
<0x00 0x6f000000 0x00 0x6f000000 0x00 0x00310000>, /* A72 PERIPHBASE */
+ <0x40 0x00000000 0x40 0x00000000 0x01 0x00000000>, /* PCIe0 DAT1 */
+ <0x41 0x00000000 0x41 0x00000000 0x01 0x00000000>, /* PCIe1 DAT1 */
<0x44 0x00000000 0x44 0x00000000 0x00 0x08000000>, /* PCIe2 DAT */
<0x44 0x10000000 0x44 0x10000000 0x00 0x08000000>, /* PCIe3 DAT */
<0x4d 0x80800000 0x4d 0x80800000 0x00 0x00800000>, /* C66_0 */
--
2.34.1
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH v2 3/7] arm64: dts: ti: k3-j721e: add ranges for PCIe0 DAT1 and PCIe1 DAT1
2025-04-22 12:00 ` [PATCH v2 3/7] arm64: dts: ti: k3-j721e: add ranges for PCIe0 DAT1 and PCIe1 DAT1 Siddharth Vadapalli
@ 2025-04-22 14:11 ` Kumar, Udit
0 siblings, 0 replies; 12+ messages in thread
From: Kumar, Udit @ 2025-04-22 14:11 UTC (permalink / raw)
To: Siddharth Vadapalli, nm, vigneshr, kristo, robh, krzk+dt, conor+dt
Cc: devicetree, linux-kernel, linux-arm-kernel, srk, u-kumar1
Thanks Siddharth
On 4/22/2025 5:30 PM, Siddharth Vadapalli wrote:
> The PCIe0 DAT1 and PCIe1 DAT1 are 4 GB address regions in the 64-bit
> address space of the respective PCIe Controllers. Hence, update the
> ranges to include them.
>
> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
> ---
>
> Link to v1 patch:
> https://lore.kernel.org/r/20250417120407.2646929-4-s-vadapalli@ti.com/
> Changes since v1:
> - Fixed the 'ranges' to set the size as 4 GB instead of the incorrect
> value of 128 MB.
>
> Regards,
> Siddharth.
>
> arch/arm64/boot/dts/ti/k3-j721e.dtsi | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-j721e.dtsi b/arch/arm64/boot/dts/ti/k3-j721e.dtsi
> index a7f2f52f42f7..b6e22c242951 100644
> --- a/arch/arm64/boot/dts/ti/k3-j721e.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j721e.dtsi
> @@ -126,6 +126,8 @@ cbass_main: bus@100000 {
> <0x00 0x10000000 0x00 0x10000000 0x00 0x10000000>, /* PCIe DAT */
> <0x00 0x64800000 0x00 0x64800000 0x00 0x00800000>, /* C71 */
> <0x00 0x6f000000 0x00 0x6f000000 0x00 0x00310000>, /* A72 PERIPHBASE */
> + <0x40 0x00000000 0x40 0x00000000 0x01 0x00000000>, /* PCIe0 DAT1 */
> + <0x41 0x00000000 0x41 0x00000000 0x01 0x00000000>, /* PCIe1 DAT1 *
Reviewed-by: Udit Kumar <u-kumar1@ti.com>
> /
> <0x44 0x00000000 0x44 0x00000000 0x00 0x08000000>, /* PCIe2 DAT */
> <0x44 0x10000000 0x44 0x10000000 0x00 0x08000000>, /* PCIe3 DAT */
> <0x4d 0x80800000 0x4d 0x80800000 0x00 0x00800000>, /* C66_0 */
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v2 4/7] arm64: dts: ti: k3-j721e-main: switch to 64-bit address space for PCIe0 and PCIe1
2025-04-22 12:00 [PATCH v2 0/7] AM64 and J7X DT: Enable PCIe 64-bit Address Space Siddharth Vadapalli
` (2 preceding siblings ...)
2025-04-22 12:00 ` [PATCH v2 3/7] arm64: dts: ti: k3-j721e: add ranges for PCIe0 DAT1 and PCIe1 DAT1 Siddharth Vadapalli
@ 2025-04-22 12:00 ` Siddharth Vadapalli
2025-04-22 12:00 ` [PATCH v2 5/7] arm64: dts: ti: k3-j721s2-main: switch to 64-bit address space for PCIe1 Siddharth Vadapalli
` (4 subsequent siblings)
8 siblings, 0 replies; 12+ messages in thread
From: Siddharth Vadapalli @ 2025-04-22 12:00 UTC (permalink / raw)
To: nm, vigneshr, kristo, robh, krzk+dt, conor+dt, u-kumar1
Cc: devicetree, linux-kernel, linux-arm-kernel, srk, s-vadapalli
The PCIe0 and PCIe1 instances of PCIe in J721E SoC support:
1. 128 MB address region in the 32-bit address space
2. 4 GB address region in the 64-bit address space
The default configuration is that of a 128 MB address region in the
32-bit address space. While this might be sufficient for most use-cases,
it is insufficient for supporting use-cases which require larger address
spaces. Therefore, switch to using the 64-bit address space with a 4 GB
address region.
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
---
Link to v1 patch:
https://lore.kernel.org/r/20250417120407.2646929-5-s-vadapalli@ti.com/
Changes since v1:
- Based on Udit's feedback and offline discussion as described at:
https://lore.kernel.org/r/7f6ea98c-df6d-4c94-8f42-76cc8306b6c4@ti.com/
the address region of 4 GB is split as:
0. 4 KB ECAM
1. 1 MB IO
2. (4 GB - 1 MB - 4 KB) 32-bit Non-Prefetchable MEM
instead of the previous split of:
0. 4 KB ECAM
1. 1 MB IO
2. 128 MB 32-bit Non-Prefetchable MEM
3. (4 GB - 129 MB - 4 KB) 64-bit Prefetchable MEM
Regards,
Siddharth.
arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
index af3d730154ac..6e1bd1dac6e5 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
@@ -941,7 +941,7 @@ pcie0_rc: pcie@2900000 {
reg = <0x00 0x02900000 0x00 0x1000>,
<0x00 0x02907000 0x00 0x400>,
<0x00 0x0d000000 0x00 0x00800000>,
- <0x00 0x10000000 0x00 0x00001000>;
+ <0x40 0x00000000 0x00 0x00001000>; /* ECAM (4 KB) */
reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
interrupt-names = "link_state";
interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>;
@@ -959,8 +959,8 @@ pcie0_rc: pcie@2900000 {
device-id = <0xb00d>;
msi-map = <0x0 &gic_its 0x0 0x10000>;
dma-coherent;
- ranges = <0x01000000 0x0 0x10001000 0x0 0x10001000 0x0 0x0010000>,
- <0x02000000 0x0 0x10011000 0x0 0x10011000 0x0 0x7fef000>;
+ ranges = <0x01000000 0x00 0x00001000 0x40 0x00001000 0x00 0x00100000>, /* IO (1 MB) */
+ <0x02000000 0x00 0x00101000 0x40 0x00101000 0x00 0xffeff000>; /* 32-bit Non-Prefetchable MEM (4 GB - 1 MB - 4 KB) */
dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
status = "disabled";
};
@@ -970,7 +970,7 @@ pcie1_rc: pcie@2910000 {
reg = <0x00 0x02910000 0x00 0x1000>,
<0x00 0x02917000 0x00 0x400>,
<0x00 0x0d800000 0x00 0x00800000>,
- <0x00 0x18000000 0x00 0x00001000>;
+ <0x41 0x00000000 0x00 0x00001000>; /* ECAM (4 KB) */
reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
interrupt-names = "link_state";
interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
@@ -988,8 +988,8 @@ pcie1_rc: pcie@2910000 {
device-id = <0xb00d>;
msi-map = <0x0 &gic_its 0x10000 0x10000>;
dma-coherent;
- ranges = <0x01000000 0x0 0x18001000 0x0 0x18001000 0x0 0x0010000>,
- <0x02000000 0x0 0x18011000 0x0 0x18011000 0x0 0x7fef000>;
+ ranges = <0x01000000 0x00 0x00001000 0x41 0x00001000 0x00 0x00100000>, /* IO (1 MB) */
+ <0x02000000 0x00 0x00101000 0x41 0x00101000 0x00 0xffeff000>; /* 32-bit Non-Prefetchable MEM (4 GB - 1 MB - 4 KB) */
dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
status = "disabled";
};
--
2.34.1
^ permalink raw reply [flat|nested] 12+ messages in thread* [PATCH v2 5/7] arm64: dts: ti: k3-j721s2-main: switch to 64-bit address space for PCIe1
2025-04-22 12:00 [PATCH v2 0/7] AM64 and J7X DT: Enable PCIe 64-bit Address Space Siddharth Vadapalli
` (3 preceding siblings ...)
2025-04-22 12:00 ` [PATCH v2 4/7] arm64: dts: ti: k3-j721e-main: switch to 64-bit address space for PCIe0 and PCIe1 Siddharth Vadapalli
@ 2025-04-22 12:00 ` Siddharth Vadapalli
2025-04-22 12:00 ` [PATCH v2 6/7] arm64: dts: ti: k3-j722s-main: switch to 64-bit address space for PCIe0 Siddharth Vadapalli
` (3 subsequent siblings)
8 siblings, 0 replies; 12+ messages in thread
From: Siddharth Vadapalli @ 2025-04-22 12:00 UTC (permalink / raw)
To: nm, vigneshr, kristo, robh, krzk+dt, conor+dt, u-kumar1
Cc: devicetree, linux-kernel, linux-arm-kernel, srk, s-vadapalli
The PCIe1 instance of PCIe in J721S2 SoC supports:
1. 128 MB address region in the 32-bit address space
2. 4 GB address region in the 64-bit address space
The default configuration is that of a 128 MB address region in the
32-bit address space. While this might be sufficient for most use-cases,
it is insufficient for supporting use-cases which require larger address
spaces. Therefore, switch to using the 64-bit address space with a 4 GB
address region.
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
---
Link to v1 patch:
https://lore.kernel.org/r/20250417120407.2646929-6-s-vadapalli@ti.com/
Changes since v1:
- Based on Udit's feedback and offline discussion as described at:
https://lore.kernel.org/r/7f6ea98c-df6d-4c94-8f42-76cc8306b6c4@ti.com/
the address region of 4 GB is split as:
0. 4 KB ECAM
1. 1 MB IO
2. (4 GB - 1 MB - 4 KB) 32-bit Non-Prefetchable MEM
instead of the previous split of:
0. 4 KB ECAM
1. 1 MB IO
2. 128 MB 32-bit Non-Prefetchable MEM
3. (4 GB - 129 MB - 4 KB) 64-bit Prefetchable MEM
Regards,
Siddharth.
arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
index 92bf48fdbeba..bfc7edf64764 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
@@ -1394,7 +1394,7 @@ pcie1_rc: pcie@2910000 {
reg = <0x00 0x02910000 0x00 0x1000>,
<0x00 0x02917000 0x00 0x400>,
<0x00 0x0d800000 0x00 0x800000>,
- <0x00 0x18000000 0x00 0x1000>;
+ <0x41 0x00000000 0x00 0x1000>; /* ECAM (4 KB) */
reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
interrupt-names = "link_state";
interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
@@ -1412,8 +1412,8 @@ pcie1_rc: pcie@2910000 {
device-id = <0xb013>;
msi-map = <0x0 &gic_its 0x0 0x10000>;
dma-coherent;
- ranges = <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>,
- <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>;
+ ranges = <0x01000000 0x00 0x00001000 0x41 0x00001000 0x00 0x00100000>, /* IO (1 MB) */
+ <0x02000000 0x00 0x00101000 0x41 0x00101000 0x00 0xffeff000>; /* 32-bit Non-Prefetchable MEM (4 GB - 1 MB - 4 KB) */
dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 7>;
--
2.34.1
^ permalink raw reply [flat|nested] 12+ messages in thread* [PATCH v2 6/7] arm64: dts: ti: k3-j722s-main: switch to 64-bit address space for PCIe0
2025-04-22 12:00 [PATCH v2 0/7] AM64 and J7X DT: Enable PCIe 64-bit Address Space Siddharth Vadapalli
` (4 preceding siblings ...)
2025-04-22 12:00 ` [PATCH v2 5/7] arm64: dts: ti: k3-j721s2-main: switch to 64-bit address space for PCIe1 Siddharth Vadapalli
@ 2025-04-22 12:00 ` Siddharth Vadapalli
2025-04-22 12:00 ` [PATCH v2 7/7] arm64: dts: ti: k3-j784s4-j742s2-main-common: switch to 64-bit address space for PCIe0 and PCIe1 Siddharth Vadapalli
` (2 subsequent siblings)
8 siblings, 0 replies; 12+ messages in thread
From: Siddharth Vadapalli @ 2025-04-22 12:00 UTC (permalink / raw)
To: nm, vigneshr, kristo, robh, krzk+dt, conor+dt, u-kumar1
Cc: devicetree, linux-kernel, linux-arm-kernel, srk, s-vadapalli
The PCIe0 instance of PCIe in J722S SoC supports:
1. 128 MB address region in the 32-bit address space
2. 4 GB address region in the 64-bit address space
The default configuration is that of a 128 MB address region in the
32-bit address space. While this might be sufficient for most use-cases,
it is insufficient for supporting use-cases which require larger address
spaces. Therefore, switch to using the 64-bit address space with a 4 GB
address region.
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
---
Link to v1 patch:
https://lore.kernel.org/r/20250417120407.2646929-7-s-vadapalli@ti.com/
Changes since v1:
- Based on Udit's feedback and offline discussion as described at:
https://lore.kernel.org/r/7f6ea98c-df6d-4c94-8f42-76cc8306b6c4@ti.com/
the address region of 4 GB is split as:
0. 4 KB ECAM
1. 1 MB IO
2. (4 GB - 1 MB - 4 KB) 32-bit Non-Prefetchable MEM
instead of the previous split of:
0. 4 KB ECAM
1. 1 MB IO
2. 128 MB 32-bit Non-Prefetchable MEM
3. (4 GB - 129 MB - 4 KB) 64-bit Prefetchable MEM
Regards,
Siddharth.
arch/arm64/boot/dts/ti/k3-j722s-main.dtsi | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi
index 6850f50530f1..da22988ff9db 100644
--- a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi
@@ -98,10 +98,10 @@ pcie0_rc: pcie@f102000 {
reg = <0x00 0x0f102000 0x00 0x1000>,
<0x00 0x0f100000 0x00 0x400>,
<0x00 0x0d000000 0x00 0x00800000>,
- <0x00 0x68000000 0x00 0x00001000>;
+ <0x06 0x00000000 0x00 0x00001000>; /* ECAM (4 KB) */
reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
- ranges = <0x01000000 0x00 0x68001000 0x00 0x68001000 0x00 0x0010000>,
- <0x02000000 0x00 0x68011000 0x00 0x68011000 0x00 0x7fef000>;
+ ranges = <0x01000000 0x00 0x00001000 0x06 0x00001000 0x00 0x00100000>, /* IO (1 MB) */
+ <0x02000000 0x00 0x00101000 0x06 0x00101000 0x00 0xffeff000>; /* 32-bit Non-Prefetchable MEM (4 GB - 1 MB - 4 KB) */
dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
interrupt-names = "link_state";
interrupts = <GIC_SPI 99 IRQ_TYPE_EDGE_RISING>;
--
2.34.1
^ permalink raw reply [flat|nested] 12+ messages in thread* [PATCH v2 7/7] arm64: dts: ti: k3-j784s4-j742s2-main-common: switch to 64-bit address space for PCIe0 and PCIe1
2025-04-22 12:00 [PATCH v2 0/7] AM64 and J7X DT: Enable PCIe 64-bit Address Space Siddharth Vadapalli
` (5 preceding siblings ...)
2025-04-22 12:00 ` [PATCH v2 6/7] arm64: dts: ti: k3-j722s-main: switch to 64-bit address space for PCIe0 Siddharth Vadapalli
@ 2025-04-22 12:00 ` Siddharth Vadapalli
2025-04-23 4:07 ` Kumar, Udit
2025-04-28 14:32 ` [PATCH v2 0/7] AM64 and J7X DT: Enable PCIe 64-bit Address Space Kumar, Udit
2025-05-02 14:44 ` Nishanth Menon
8 siblings, 1 reply; 12+ messages in thread
From: Siddharth Vadapalli @ 2025-04-22 12:00 UTC (permalink / raw)
To: nm, vigneshr, kristo, robh, krzk+dt, conor+dt, u-kumar1
Cc: devicetree, linux-kernel, linux-arm-kernel, srk, s-vadapalli
The PCIe0 and PCIe1 instances of PCIe in J742S2 and J784S4 SoCs support:
1. 128 MB address region in the 32-bit address space
2. 4 GB address region in the 64-bit address space
The default configuration is that of a 128 MB address region in the
32-bit address space. While this might be sufficient for most use-cases,
it is insufficient for supporting use-cases which require larger address
spaces. Therefore, switch to using the 64-bit address space with a 4 GB
address region.
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
---
Link to v1 patch:
https://lore.kernel.org/r/20250417120407.2646929-8-s-vadapalli@ti.com/
Changes since v1:
- Based on Udit's feedback and offline discussion as described at:
https://lore.kernel.org/r/7f6ea98c-df6d-4c94-8f42-76cc8306b6c4@ti.com/
the address region of 4 GB is split as:
0. 4 KB ECAM
1. 1 MB IO
2. (4 GB - 1 MB - 4 KB) 32-bit Non-Prefetchable MEM
instead of the previous split of:
0. 4 KB ECAM
1. 1 MB IO
2. 128 MB 32-bit Non-Prefetchable MEM
3. (4 GB - 129 MB - 4 KB) 64-bit Prefetchable MEM
Regards,
Siddharth.
.../boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi
index 1944616ab357..e6c9080d80b0 100644
--- a/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi
@@ -1055,7 +1055,7 @@ pcie0_rc: pcie@2900000 {
reg = <0x00 0x02900000 0x00 0x1000>,
<0x00 0x02907000 0x00 0x400>,
<0x00 0x0d000000 0x00 0x00800000>,
- <0x00 0x10000000 0x00 0x00001000>;
+ <0x40 0x00000000 0x00 0x00001000>; /* ECAM (4 KB) */
reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
interrupt-names = "link_state";
interrupts = <GIC_SPI 318 IRQ_TYPE_EDGE_RISING>;
@@ -1073,8 +1073,8 @@ pcie0_rc: pcie@2900000 {
device-id = <0xb012>;
msi-map = <0x0 &gic_its 0x0 0x10000>;
dma-coherent;
- ranges = <0x01000000 0x0 0x10001000 0x0 0x10001000 0x0 0x0010000>,
- <0x02000000 0x0 0x10011000 0x0 0x10011000 0x0 0x7fef000>;
+ ranges = <0x01000000 0x00 0x00001000 0x40 0x00001000 0x00 0x00100000>, /* IO (1 MB) */
+ <0x02000000 0x00 0x00101000 0x40 0x00101000 0x00 0xffeff000>; /* 32-bit Non-Prefetchable MEM (4 GB - 1 MB - 4 KB) */
dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
status = "disabled";
};
@@ -1084,7 +1084,7 @@ pcie1_rc: pcie@2910000 {
reg = <0x00 0x02910000 0x00 0x1000>,
<0x00 0x02917000 0x00 0x400>,
<0x00 0x0d800000 0x00 0x00800000>,
- <0x00 0x18000000 0x00 0x00001000>;
+ <0x41 0x00000000 0x00 0x00001000>; /* ECAM (4 KB) */
reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
interrupt-names = "link_state";
interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
@@ -1102,8 +1102,8 @@ pcie1_rc: pcie@2910000 {
device-id = <0xb012>;
msi-map = <0x0 &gic_its 0x10000 0x10000>;
dma-coherent;
- ranges = <0x01000000 0x0 0x18001000 0x00 0x18001000 0x0 0x0010000>,
- <0x02000000 0x0 0x18011000 0x00 0x18011000 0x0 0x7fef000>;
+ ranges = <0x01000000 0x00 0x00001000 0x41 0x00001000 0x00 0x00100000>, /* IO (1 MB) */
+ <0x02000000 0x00 0x00101000 0x41 0x00101000 0x00 0xffeff000>; /* 32-bit Non-Prefetchable MEM (4 GB - 1 MB - 4 KB) */
dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
status = "disabled";
};
--
2.34.1
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH v2 7/7] arm64: dts: ti: k3-j784s4-j742s2-main-common: switch to 64-bit address space for PCIe0 and PCIe1
2025-04-22 12:00 ` [PATCH v2 7/7] arm64: dts: ti: k3-j784s4-j742s2-main-common: switch to 64-bit address space for PCIe0 and PCIe1 Siddharth Vadapalli
@ 2025-04-23 4:07 ` Kumar, Udit
0 siblings, 0 replies; 12+ messages in thread
From: Kumar, Udit @ 2025-04-23 4:07 UTC (permalink / raw)
To: Siddharth Vadapalli, nm, vigneshr, kristo, robh, krzk+dt, conor+dt
Cc: devicetree, linux-kernel, linux-arm-kernel, srk
On 4/22/2025 5:30 PM, Siddharth Vadapalli wrote:
> The PCIe0 and PCIe1 instances of PCIe in J742S2 and J784S4 SoCs support:
> 1. 128 MB address region in the 32-bit address space
> 2. 4 GB address region in the 64-bit address space
>
> The default configuration is that of a 128 MB address region in the
> 32-bit address space. While this might be sufficient for most use-cases,
> it is insufficient for supporting use-cases which require larger address
> spaces. Therefore, switch to using the 64-bit address space with a 4 GB
> address region.
>
> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
> ---
>
> [..]
> + <0x02000000 0x00 0x00101000 0x41 0x00101000 0x00 0xffeff000>; /* 32-bit Non-Prefetchable MEM (4 GB - 1 MB - 4 KB) */
Reviewed-by: Udit Kumar <u-kumar1@ti.com>
> dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
> status = "disabled";
> };
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v2 0/7] AM64 and J7X DT: Enable PCIe 64-bit Address Space
2025-04-22 12:00 [PATCH v2 0/7] AM64 and J7X DT: Enable PCIe 64-bit Address Space Siddharth Vadapalli
` (6 preceding siblings ...)
2025-04-22 12:00 ` [PATCH v2 7/7] arm64: dts: ti: k3-j784s4-j742s2-main-common: switch to 64-bit address space for PCIe0 and PCIe1 Siddharth Vadapalli
@ 2025-04-28 14:32 ` Kumar, Udit
2025-05-02 14:44 ` Nishanth Menon
8 siblings, 0 replies; 12+ messages in thread
From: Kumar, Udit @ 2025-04-28 14:32 UTC (permalink / raw)
To: Siddharth Vadapalli, nm, vigneshr, kristo, robh, krzk+dt, conor+dt
Cc: devicetree, linux-kernel, linux-arm-kernel, srk, u-kumar1
On 4/22/2025 5:30 PM, Siddharth Vadapalli wrote:
> Hello,
>
> The Cadence PCIe Controllers in TI's K3 SoCs namely:
> AM64, J7200, J721E, J721S2 (AM68), J722S, J742S2 and J784S4 (AM69)
> support two address regions:
> 1. 128 MB address region in the 32-bit address space
> 2. 4 GB address region in the 64-bit address space
>
> Currently, the 128 MB region in the 32-bit address space is enabled in
> the device-tree. This might be suitable for most of the use-cases, but
> for those use-cases requiring larger address regions than 128 MB it is
> necessary to switch to the 64-bit address space with the 4 GB address
> region. This series implements the corresponding device-tree changes to
> support the 4 GB address region as the default configuration. Existing
> use-cases should continue to work without any regression.
>
> Series is based on linux-next tagged next-20250417.
For series
Reviewed-by: Udit Kumar <u-kumar1@ti.com>
>
> Link to v1 series:
> https://lore.kernel.org/r/20250417120407.2646929-1-s-vadapalli@ti.com/
>
> Changes since v1 series:
> - Fixed the 'ranges' in k3-j721e.dtsi which is the third patch of the
> series to set the size as 4 GB instead of the incorrect value of 128 MB.
> - Based on Udit's feedback and offline discussion as described at:
> https://lore.kernel.org/r/7f6ea98c-df6d-4c94-8f42-76cc8306b6c4@ti.com/
> the address region of 4 GB is split as:
> 0. 4 KB ECAM
> 1. 1 MB IO
> 2. (4 GB - 1 MB - 4 KB) 32-bit Non-Prefetchable MEM
> instead of the previous split of:
> 0. 4 KB ECAM
> 1. 1 MB IO
> 2. 128 MB 32-bit Non-Prefetchable MEM
> 3. (4 GB - 129 MB - 4 KB) 64-bit Prefetchable MEM
>
> Series has been tested on AM642-EVM, J7200-EVM, J721E-EVM, J721S2-EVM,
> J722S-EVM and J784S4-EVM using an NVMe SSD connected to the PCIe
> Connector on the EVMs.
>
> Test Logs:
> 1. AM642-EVM PCIe0
> https://gist.github.com/Siddharth-Vadapalli-at-TI/5d1814ee2e0857dac0ac08a6cf8759da
> 2. J7200-EVM PCIe1
> https://gist.github.com/Siddharth-Vadapalli-at-TI/9927faab7615b9c1c101854a213f30f5
> 3. J721E-EVM PCIe0
> https://gist.github.com/Siddharth-Vadapalli-at-TI/e6545e31f45077fe59c896f8875bf1b9
> 4. J721E-EVM PCIe1
> https://gist.github.com/Siddharth-Vadapalli-at-TI/5c0b64f339f89139797d8346c40b1ee9
> 5. J721S2-EVM PCIe1
> https://gist.github.com/Siddharth-Vadapalli-at-TI/67b03c441d53ef0d27837e615371efbd
> 6. J722S-EVM PCIe0
> https://gist.github.com/Siddharth-Vadapalli-at-TI/7625f47b57d45aada4c125ac4f60ebd6
> 7. J784S4-EVM PCIe0
> https://gist.github.com/Siddharth-Vadapalli-at-TI/edf2af424fc7d5905832d536a1171a1a
>
> Regards,
> Siddharth.
>
> Siddharth Vadapalli (7):
> arm64: dts: ti: k3-am64-main: switch to 64-bit address space for PCIe0
> arm64: dts: ti: k3-j7200-main: switch to 64-bit address space for
> PCIe1
> arm64: dts: ti: k3-j721e: add ranges for PCIe0 DAT1 and PCIe1 DAT1
> arm64: dts: ti: k3-j721e-main: switch to 64-bit address space for
> PCIe0 and PCIe1
> arm64: dts: ti: k3-j721s2-main: switch to 64-bit address space for
> PCIe1
> arm64: dts: ti: k3-j722s-main: switch to 64-bit address space for
> PCIe0
> arm64: dts: ti: k3-j784s4-j742s2-main-common: switch to 64-bit address
> space for PCIe0 and PCIe1
>
> arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 6 +++---
> arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 6 +++---
> arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 12 ++++++------
> arch/arm64/boot/dts/ti/k3-j721e.dtsi | 2 ++
> arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 6 +++---
> arch/arm64/boot/dts/ti/k3-j722s-main.dtsi | 6 +++---
> .../boot/dts/ti/k3-j784s4-j742s2-main-common.dtsi | 12 ++++++------
> 7 files changed, 26 insertions(+), 24 deletions(-)
>
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH v2 0/7] AM64 and J7X DT: Enable PCIe 64-bit Address Space
2025-04-22 12:00 [PATCH v2 0/7] AM64 and J7X DT: Enable PCIe 64-bit Address Space Siddharth Vadapalli
` (7 preceding siblings ...)
2025-04-28 14:32 ` [PATCH v2 0/7] AM64 and J7X DT: Enable PCIe 64-bit Address Space Kumar, Udit
@ 2025-05-02 14:44 ` Nishanth Menon
8 siblings, 0 replies; 12+ messages in thread
From: Nishanth Menon @ 2025-05-02 14:44 UTC (permalink / raw)
To: vigneshr, kristo, robh, krzk+dt, conor+dt, u-kumar1, Siddharth Vadapalli
Cc: Nishanth Menon, devicetree, linux-kernel, linux-arm-kernel, srk
Hi Siddharth Vadapalli,
On Tue, 22 Apr 2025 17:30:35 +0530, Siddharth Vadapalli wrote:
> The Cadence PCIe Controllers in TI's K3 SoCs namely:
> AM64, J7200, J721E, J721S2 (AM68), J722S, J742S2 and J784S4 (AM69)
> support two address regions:
> 1. 128 MB address region in the 32-bit address space
> 2. 4 GB address region in the 64-bit address space
>
> Currently, the 128 MB region in the 32-bit address space is enabled in
> the device-tree. This might be suitable for most of the use-cases, but
> for those use-cases requiring larger address regions than 128 MB it is
> necessary to switch to the 64-bit address space with the 4 GB address
> region. This series implements the corresponding device-tree changes to
> support the 4 GB address region as the default configuration. Existing
> use-cases should continue to work without any regression.
>
> [...]
I have applied the following to branch ti-k3-dts-next on [1].
NOTE: I have ignored the checkpatch warning on long lines since the
documentation added in the context of the line makes more sense than splitting
it up.
Thank you!
[1/7] arm64: dts: ti: k3-am64-main: switch to 64-bit address space for PCIe0
commit: 1159f911435b9371575d9956bb5aef579265d29a
[2/7] arm64: dts: ti: k3-j7200-main: switch to 64-bit address space for PCIe1
commit: 46e3d7d7048872ffb90aa25e360b975dc1c3e28b
[3/7] arm64: dts: ti: k3-j721e: add ranges for PCIe0 DAT1 and PCIe1 DAT1
commit: 1025003a1e068a25b35e1dbb39cad18e23278c0f
[4/7] arm64: dts: ti: k3-j721e-main: switch to 64-bit address space for PCIe0 and PCIe1
commit: f0f78192d3b3b3c3c935de0d681e7bf2117bbb13
[5/7] arm64: dts: ti: k3-j721s2-main: switch to 64-bit address space for PCIe1
commit: 5a765365c689b90ea81f651a43bc30cd9c9c4ed8
[6/7] arm64: dts: ti: k3-j722s-main: switch to 64-bit address space for PCIe0
commit: 0fde00328cf8245bf498349a696ba22d6a4a1916
[7/7] arm64: dts: ti: k3-j784s4-j742s2-main-common: switch to 64-bit address space for PCIe0 and PCIe1
commit: b1f9ec6545c6423e106f0aeddc3b8651b5ad116c
All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent up the chain during
the next merge window (or sooner if it is a relevant bug fix), however if
problems are discovered then the patch may be dropped or reverted.
You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.
If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.
Please add any relevant lists and maintainers to the CCs when replying
to this mail.
[1] https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux.git
--
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D
^ permalink raw reply [flat|nested] 12+ messages in thread