* [PATCH v1 01/20] drm/amdgpu: give each kernel job a unique id
2025-11-04 8:35 [PATCH v1 00/20] drm/amdgpu: use all SDMA instances for TTM clears and moves Pierre-Eric Pelloux-Prayer
@ 2025-11-04 8:35 ` Pierre-Eric Pelloux-Prayer
2025-11-04 13:58 ` Christian König
2025-11-04 8:35 ` [PATCH v1 02/20] drm/ttm: rework pipelined eviction fence handling Pierre-Eric Pelloux-Prayer
` (18 subsequent siblings)
19 siblings, 1 reply; 40+ messages in thread
From: Pierre-Eric Pelloux-Prayer @ 2025-11-04 8:35 UTC (permalink / raw)
To: Alex Deucher, Christian König, David Airlie, Simona Vetter,
Felix Kuehling
Cc: Pierre-Eric Pelloux-Prayer, Arunpravin Paneer Selvam, amd-gfx,
dri-devel, linux-kernel
Userspace jobs have drm_file.client_id as a unique identifier
as job's owners. For kernel jobs, we can allocate arbitrary
values - the risk of overlap with userspace ids is small (given
that it's a u64 value).
In the unlikely case the overlap happens, it'll only impact
trace events.
Since this ID is traced in the gpu_scheduler trace events, this
allows to determine the source of each job sent to the hardware.
To make grepping easier, the IDs are defined as they will appear
in the trace output.
Signed-off-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Arunpravin Paneer Selvam <Arunpravin.PaneerSelvam@amd.com>
Link: https://lore.kernel.org/r/20250604122827.2191-1-pierre-eric.pelloux-prayer@amd.com
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 3 ++-
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_job.c | 5 ++--
drivers/gpu/drm/amd/amdgpu/amdgpu_job.h | 19 +++++++++++++-
drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c | 3 ++-
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 3 ++-
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 28 +++++++++++++--------
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 3 ++-
drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 3 ++-
drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c | 5 ++--
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 8 +++---
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 6 +++--
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c | 4 ++-
drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c | 4 ++-
drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c | 12 +++++----
drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 6 +++--
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 6 +++--
drivers/gpu/drm/amd/amdkfd/kfd_migrate.c | 3 ++-
19 files changed, 84 insertions(+), 41 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
index 3d24f9cd750a..29c927f4d6df 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
@@ -1549,7 +1549,8 @@ static int amdgpu_gfx_run_cleaner_shader_job(struct amdgpu_ring *ring)
owner = (void *)(unsigned long)atomic_inc_return(&counter);
r = amdgpu_job_alloc_with_ib(ring->adev, &entity, owner,
- 64, 0, &job);
+ 64, 0, &job,
+ AMDGPU_KERNEL_JOB_ID_CLEANER_SHADER);
if (r)
goto err;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
index 97b562a79ea8..9dcf51991b5b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
@@ -690,7 +690,7 @@ void amdgpu_gmc_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
r = amdgpu_job_alloc_with_ib(ring->adev, &adev->mman.high_pr,
AMDGPU_FENCE_OWNER_UNDEFINED,
16 * 4, AMDGPU_IB_POOL_IMMEDIATE,
- &job);
+ &job, AMDGPU_KERNEL_JOB_ID_FLUSH_GPU_TLB);
if (r)
goto error_alloc;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
index 55c7e104d5ca..3457bd649623 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
@@ -234,11 +234,12 @@ int amdgpu_job_alloc(struct amdgpu_device *adev, struct amdgpu_vm *vm,
int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev,
struct drm_sched_entity *entity, void *owner,
size_t size, enum amdgpu_ib_pool_type pool_type,
- struct amdgpu_job **job)
+ struct amdgpu_job **job, u64 k_job_id)
{
int r;
- r = amdgpu_job_alloc(adev, NULL, entity, owner, 1, job, 0);
+ r = amdgpu_job_alloc(adev, NULL, entity, owner, 1, job,
+ k_job_id);
if (r)
return r;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h
index d25f1fcf0242..7abf069d17d4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h
@@ -44,6 +44,22 @@
struct amdgpu_fence;
enum amdgpu_ib_pool_type;
+/* Internal kernel job ids. (decreasing values, starting from U64_MAX). */
+#define AMDGPU_KERNEL_JOB_ID_VM_UPDATE (18446744073709551615ULL)
+#define AMDGPU_KERNEL_JOB_ID_VM_UPDATE_PDES (18446744073709551614ULL)
+#define AMDGPU_KERNEL_JOB_ID_VM_UPDATE_RANGE (18446744073709551613ULL)
+#define AMDGPU_KERNEL_JOB_ID_VM_PT_CLEAR (18446744073709551612ULL)
+#define AMDGPU_KERNEL_JOB_ID_TTM_MAP_BUFFER (18446744073709551611ULL)
+#define AMDGPU_KERNEL_JOB_ID_TTM_ACCESS_MEMORY_SDMA (18446744073709551610ULL)
+#define AMDGPU_KERNEL_JOB_ID_TTM_COPY_BUFFER (18446744073709551609ULL)
+#define AMDGPU_KERNEL_JOB_ID_CLEAR_ON_RELEASE (18446744073709551608ULL)
+#define AMDGPU_KERNEL_JOB_ID_MOVE_BLIT (18446744073709551607ULL)
+#define AMDGPU_KERNEL_JOB_ID_TTM_CLEAR_BUFFER (18446744073709551606ULL)
+#define AMDGPU_KERNEL_JOB_ID_CLEANER_SHADER (18446744073709551605ULL)
+#define AMDGPU_KERNEL_JOB_ID_FLUSH_GPU_TLB (18446744073709551604ULL)
+#define AMDGPU_KERNEL_JOB_ID_KFD_GART_MAP (18446744073709551603ULL)
+#define AMDGPU_KERNEL_JOB_ID_VCN_RING_TEST (18446744073709551602ULL)
+
struct amdgpu_job {
struct drm_sched_job base;
struct amdgpu_vm *vm;
@@ -97,7 +113,8 @@ int amdgpu_job_alloc(struct amdgpu_device *adev, struct amdgpu_vm *vm,
int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev,
struct drm_sched_entity *entity, void *owner,
size_t size, enum amdgpu_ib_pool_type pool_type,
- struct amdgpu_job **job);
+ struct amdgpu_job **job,
+ u64 k_job_id);
void amdgpu_job_set_resources(struct amdgpu_job *job, struct amdgpu_bo *gds,
struct amdgpu_bo *gws, struct amdgpu_bo *oa);
void amdgpu_job_free_resources(struct amdgpu_job *job);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c
index 91678621f1ff..63ee6ba6a931 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c
@@ -196,7 +196,8 @@ static int amdgpu_jpeg_dec_set_reg(struct amdgpu_ring *ring, uint32_t handle,
int i, r;
r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL, ib_size_dw * 4,
- AMDGPU_IB_POOL_DIRECT, &job);
+ AMDGPU_IB_POOL_DIRECT, &job,
+ AMDGPU_KERNEL_JOB_ID_VCN_RING_TEST);
if (r)
return r;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index fe486988a738..e08f58de4b17 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -1321,7 +1321,8 @@ void amdgpu_bo_release_notify(struct ttm_buffer_object *bo)
if (r)
goto out;
- r = amdgpu_fill_buffer(abo, 0, &bo->base._resv, &fence, true);
+ r = amdgpu_fill_buffer(abo, 0, &bo->base._resv, &fence, true,
+ AMDGPU_KERNEL_JOB_ID_CLEAR_ON_RELEASE);
if (WARN_ON(r))
goto out;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index e226c3aff7d7..326476089db3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -227,7 +227,8 @@ static int amdgpu_ttm_map_buffer(struct ttm_buffer_object *bo,
r = amdgpu_job_alloc_with_ib(adev, &adev->mman.high_pr,
AMDGPU_FENCE_OWNER_UNDEFINED,
num_dw * 4 + num_bytes,
- AMDGPU_IB_POOL_DELAYED, &job);
+ AMDGPU_IB_POOL_DELAYED, &job,
+ AMDGPU_KERNEL_JOB_ID_TTM_MAP_BUFFER);
if (r)
return r;
@@ -406,7 +407,7 @@ static int amdgpu_move_blit(struct ttm_buffer_object *bo,
struct dma_fence *wipe_fence = NULL;
r = amdgpu_fill_buffer(abo, 0, NULL, &wipe_fence,
- false);
+ false, AMDGPU_KERNEL_JOB_ID_MOVE_BLIT);
if (r) {
goto error;
} else if (wipe_fence) {
@@ -1488,7 +1489,8 @@ static int amdgpu_ttm_access_memory_sdma(struct ttm_buffer_object *bo,
r = amdgpu_job_alloc_with_ib(adev, &adev->mman.high_pr,
AMDGPU_FENCE_OWNER_UNDEFINED,
num_dw * 4, AMDGPU_IB_POOL_DELAYED,
- &job);
+ &job,
+ AMDGPU_KERNEL_JOB_ID_TTM_ACCESS_MEMORY_SDMA);
if (r)
goto out;
@@ -2212,7 +2214,7 @@ static int amdgpu_ttm_prepare_job(struct amdgpu_device *adev,
struct dma_resv *resv,
bool vm_needs_flush,
struct amdgpu_job **job,
- bool delayed)
+ bool delayed, u64 k_job_id)
{
enum amdgpu_ib_pool_type pool = direct_submit ?
AMDGPU_IB_POOL_DIRECT :
@@ -2222,7 +2224,7 @@ static int amdgpu_ttm_prepare_job(struct amdgpu_device *adev,
&adev->mman.high_pr;
r = amdgpu_job_alloc_with_ib(adev, entity,
AMDGPU_FENCE_OWNER_UNDEFINED,
- num_dw * 4, pool, job);
+ num_dw * 4, pool, job, k_job_id);
if (r)
return r;
@@ -2262,7 +2264,8 @@ int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
num_loops = DIV_ROUND_UP(byte_count, max_bytes);
num_dw = ALIGN(num_loops * adev->mman.buffer_funcs->copy_num_dw, 8);
r = amdgpu_ttm_prepare_job(adev, direct_submit, num_dw,
- resv, vm_needs_flush, &job, false);
+ resv, vm_needs_flush, &job, false,
+ AMDGPU_KERNEL_JOB_ID_TTM_COPY_BUFFER);
if (r)
return r;
@@ -2297,7 +2300,8 @@ static int amdgpu_ttm_fill_mem(struct amdgpu_ring *ring, uint32_t src_data,
uint64_t dst_addr, uint32_t byte_count,
struct dma_resv *resv,
struct dma_fence **fence,
- bool vm_needs_flush, bool delayed)
+ bool vm_needs_flush, bool delayed,
+ u64 k_job_id)
{
struct amdgpu_device *adev = ring->adev;
unsigned int num_loops, num_dw;
@@ -2310,7 +2314,7 @@ static int amdgpu_ttm_fill_mem(struct amdgpu_ring *ring, uint32_t src_data,
num_loops = DIV_ROUND_UP_ULL(byte_count, max_bytes);
num_dw = ALIGN(num_loops * adev->mman.buffer_funcs->fill_num_dw, 8);
r = amdgpu_ttm_prepare_job(adev, false, num_dw, resv, vm_needs_flush,
- &job, delayed);
+ &job, delayed, k_job_id);
if (r)
return r;
@@ -2380,7 +2384,8 @@ int amdgpu_ttm_clear_buffer(struct amdgpu_bo *bo,
goto err;
r = amdgpu_ttm_fill_mem(ring, 0, addr, size, resv,
- &next, true, true);
+ &next, true, true,
+ AMDGPU_KERNEL_JOB_ID_TTM_CLEAR_BUFFER);
if (r)
goto err;
@@ -2399,7 +2404,8 @@ int amdgpu_fill_buffer(struct amdgpu_bo *bo,
uint32_t src_data,
struct dma_resv *resv,
struct dma_fence **f,
- bool delayed)
+ bool delayed,
+ u64 k_job_id)
{
struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
@@ -2429,7 +2435,7 @@ int amdgpu_fill_buffer(struct amdgpu_bo *bo,
goto error;
r = amdgpu_ttm_fill_mem(ring, src_data, to, cur_size, resv,
- &next, true, delayed);
+ &next, true, delayed, k_job_id);
if (r)
goto error;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
index 054d48823d5f..577ee04ce0bf 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
@@ -175,7 +175,8 @@ int amdgpu_fill_buffer(struct amdgpu_bo *bo,
uint32_t src_data,
struct dma_resv *resv,
struct dma_fence **fence,
- bool delayed);
+ bool delayed,
+ u64 k_job_id);
int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo);
void amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
index 74758b5ffc6c..5c38f0d30c87 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
@@ -1136,7 +1136,8 @@ static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo,
r = amdgpu_job_alloc_with_ib(ring->adev, &adev->uvd.entity,
AMDGPU_FENCE_OWNER_UNDEFINED,
64, direct ? AMDGPU_IB_POOL_DIRECT :
- AMDGPU_IB_POOL_DELAYED, &job);
+ AMDGPU_IB_POOL_DELAYED, &job,
+ AMDGPU_KERNEL_JOB_ID_VCN_RING_TEST);
if (r)
return r;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
index b9060bcd4806..ce318f5de047 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
@@ -449,7 +449,7 @@ static int amdgpu_vce_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
r = amdgpu_job_alloc_with_ib(ring->adev, &ring->adev->vce.entity,
AMDGPU_FENCE_OWNER_UNDEFINED,
ib_size_dw * 4, AMDGPU_IB_POOL_DIRECT,
- &job);
+ &job, AMDGPU_KERNEL_JOB_ID_VCN_RING_TEST);
if (r)
return r;
@@ -540,7 +540,8 @@ static int amdgpu_vce_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
AMDGPU_FENCE_OWNER_UNDEFINED,
ib_size_dw * 4,
direct ? AMDGPU_IB_POOL_DIRECT :
- AMDGPU_IB_POOL_DELAYED, &job);
+ AMDGPU_IB_POOL_DELAYED, &job,
+ AMDGPU_KERNEL_JOB_ID_VCN_RING_TEST);
if (r)
return r;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
index 5ae7cc0d5f57..5e0786ea911b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
@@ -626,7 +626,7 @@ static int amdgpu_vcn_dec_send_msg(struct amdgpu_ring *ring,
r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL,
64, AMDGPU_IB_POOL_DIRECT,
- &job);
+ &job, AMDGPU_KERNEL_JOB_ID_VCN_RING_TEST);
if (r)
goto err;
@@ -806,7 +806,7 @@ static int amdgpu_vcn_dec_sw_send_msg(struct amdgpu_ring *ring,
r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL,
ib_size_dw * 4, AMDGPU_IB_POOL_DIRECT,
- &job);
+ &job, AMDGPU_KERNEL_JOB_ID_VCN_RING_TEST);
if (r)
goto err;
@@ -936,7 +936,7 @@ static int amdgpu_vcn_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t hand
r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL,
ib_size_dw * 4, AMDGPU_IB_POOL_DIRECT,
- &job);
+ &job, AMDGPU_KERNEL_JOB_ID_VCN_RING_TEST);
if (r)
return r;
@@ -1003,7 +1003,7 @@ static int amdgpu_vcn_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t han
r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL,
ib_size_dw * 4, AMDGPU_IB_POOL_DIRECT,
- &job);
+ &job, AMDGPU_KERNEL_JOB_ID_VCN_RING_TEST);
if (r)
return r;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index db66b4232de0..2f8e83f840a8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -983,7 +983,8 @@ int amdgpu_vm_update_pdes(struct amdgpu_device *adev,
params.vm = vm;
params.immediate = immediate;
- r = vm->update_funcs->prepare(¶ms, NULL);
+ r = vm->update_funcs->prepare(¶ms, NULL,
+ AMDGPU_KERNEL_JOB_ID_VM_UPDATE_PDES);
if (r)
goto error;
@@ -1152,7 +1153,8 @@ int amdgpu_vm_update_range(struct amdgpu_device *adev, struct amdgpu_vm *vm,
dma_fence_put(tmp);
}
- r = vm->update_funcs->prepare(¶ms, sync);
+ r = vm->update_funcs->prepare(¶ms, sync,
+ AMDGPU_KERNEL_JOB_ID_VM_UPDATE_RANGE);
if (r)
goto error_free;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
index 77207f4e448e..cf0ec94e8a07 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
@@ -308,7 +308,7 @@ struct amdgpu_vm_update_params {
struct amdgpu_vm_update_funcs {
int (*map_table)(struct amdgpu_bo_vm *bo);
int (*prepare)(struct amdgpu_vm_update_params *p,
- struct amdgpu_sync *sync);
+ struct amdgpu_sync *sync, u64 k_job_id);
int (*update)(struct amdgpu_vm_update_params *p,
struct amdgpu_bo_vm *bo, uint64_t pe, uint64_t addr,
unsigned count, uint32_t incr, uint64_t flags);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c
index 0c1ef5850a5e..22e2e5b47341 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c
@@ -40,12 +40,14 @@ static int amdgpu_vm_cpu_map_table(struct amdgpu_bo_vm *table)
*
* @p: see amdgpu_vm_update_params definition
* @sync: sync obj with fences to wait on
+ * @k_job_id: the id for tracing/debug purposes
*
* Returns:
* Negativ errno, 0 for success.
*/
static int amdgpu_vm_cpu_prepare(struct amdgpu_vm_update_params *p,
- struct amdgpu_sync *sync)
+ struct amdgpu_sync *sync,
+ u64 k_job_id)
{
if (!sync)
return 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c
index 30022123b0bf..f794fb1cc06e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c
@@ -26,6 +26,7 @@
#include "amdgpu.h"
#include "amdgpu_trace.h"
#include "amdgpu_vm.h"
+#include "amdgpu_job.h"
/*
* amdgpu_vm_pt_cursor - state for for_each_amdgpu_vm_pt
@@ -395,7 +396,8 @@ int amdgpu_vm_pt_clear(struct amdgpu_device *adev, struct amdgpu_vm *vm,
params.vm = vm;
params.immediate = immediate;
- r = vm->update_funcs->prepare(¶ms, NULL);
+ r = vm->update_funcs->prepare(¶ms, NULL,
+ AMDGPU_KERNEL_JOB_ID_VM_PT_CLEAR);
if (r)
goto exit;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
index 46d9fb433ab2..36805dcfa159 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
@@ -40,7 +40,7 @@ static int amdgpu_vm_sdma_map_table(struct amdgpu_bo_vm *table)
/* Allocate a new job for @count PTE updates */
static int amdgpu_vm_sdma_alloc_job(struct amdgpu_vm_update_params *p,
- unsigned int count)
+ unsigned int count, u64 k_job_id)
{
enum amdgpu_ib_pool_type pool = p->immediate ? AMDGPU_IB_POOL_IMMEDIATE
: AMDGPU_IB_POOL_DELAYED;
@@ -56,7 +56,7 @@ static int amdgpu_vm_sdma_alloc_job(struct amdgpu_vm_update_params *p,
ndw = min(ndw, AMDGPU_VM_SDMA_MAX_NUM_DW);
r = amdgpu_job_alloc_with_ib(p->adev, entity, AMDGPU_FENCE_OWNER_VM,
- ndw * 4, pool, &p->job);
+ ndw * 4, pool, &p->job, k_job_id);
if (r)
return r;
@@ -69,16 +69,17 @@ static int amdgpu_vm_sdma_alloc_job(struct amdgpu_vm_update_params *p,
*
* @p: see amdgpu_vm_update_params definition
* @sync: amdgpu_sync object with fences to wait for
+ * @k_job_id: identifier of the job, for tracing purpose
*
* Returns:
* Negativ errno, 0 for success.
*/
static int amdgpu_vm_sdma_prepare(struct amdgpu_vm_update_params *p,
- struct amdgpu_sync *sync)
+ struct amdgpu_sync *sync, u64 k_job_id)
{
int r;
- r = amdgpu_vm_sdma_alloc_job(p, 0);
+ r = amdgpu_vm_sdma_alloc_job(p, 0, k_job_id);
if (r)
return r;
@@ -249,7 +250,8 @@ static int amdgpu_vm_sdma_update(struct amdgpu_vm_update_params *p,
if (r)
return r;
- r = amdgpu_vm_sdma_alloc_job(p, count);
+ r = amdgpu_vm_sdma_alloc_job(p, count,
+ AMDGPU_KERNEL_JOB_ID_VM_UPDATE);
if (r)
return r;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
index 1c07b701d0e4..ceb94bbb03a4 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
@@ -217,7 +217,8 @@ static int uvd_v6_0_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle
int i, r;
r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL, ib_size_dw * 4,
- AMDGPU_IB_POOL_DIRECT, &job);
+ AMDGPU_IB_POOL_DIRECT, &job,
+ AMDGPU_KERNEL_JOB_ID_VCN_RING_TEST);
if (r)
return r;
@@ -281,7 +282,8 @@ static int uvd_v6_0_enc_get_destroy_msg(struct amdgpu_ring *ring,
int i, r;
r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL, ib_size_dw * 4,
- AMDGPU_IB_POOL_DIRECT, &job);
+ AMDGPU_IB_POOL_DIRECT, &job,
+ AMDGPU_KERNEL_JOB_ID_VCN_RING_TEST);
if (r)
return r;
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
index 9d237b5937fb..1f8866f3f63c 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
@@ -225,7 +225,8 @@ static int uvd_v7_0_enc_get_create_msg(struct amdgpu_ring *ring, u32 handle,
int i, r;
r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL, ib_size_dw * 4,
- AMDGPU_IB_POOL_DIRECT, &job);
+ AMDGPU_IB_POOL_DIRECT, &job,
+ AMDGPU_KERNEL_JOB_ID_VCN_RING_TEST);
if (r)
return r;
@@ -288,7 +289,8 @@ static int uvd_v7_0_enc_get_destroy_msg(struct amdgpu_ring *ring, u32 handle,
int i, r;
r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL, ib_size_dw * 4,
- AMDGPU_IB_POOL_DIRECT, &job);
+ AMDGPU_IB_POOL_DIRECT, &job,
+ AMDGPU_KERNEL_JOB_ID_VCN_RING_TEST);
if (r)
return r;
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
index 3653c563ee9a..46c84fc60af1 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
@@ -67,7 +67,8 @@ svm_migrate_gart_map(struct amdgpu_ring *ring, u64 npages,
AMDGPU_FENCE_OWNER_UNDEFINED,
num_dw * 4 + num_bytes,
AMDGPU_IB_POOL_DELAYED,
- &job);
+ &job,
+ AMDGPU_KERNEL_JOB_ID_KFD_GART_MAP);
if (r)
return r;
--
2.43.0
^ permalink raw reply [flat|nested] 40+ messages in thread* Re: [PATCH v1 01/20] drm/amdgpu: give each kernel job a unique id
2025-11-04 8:35 ` [PATCH v1 01/20] drm/amdgpu: give each kernel job a unique id Pierre-Eric Pelloux-Prayer
@ 2025-11-04 13:58 ` Christian König
0 siblings, 0 replies; 40+ messages in thread
From: Christian König @ 2025-11-04 13:58 UTC (permalink / raw)
To: Pierre-Eric Pelloux-Prayer, Alex Deucher, David Airlie,
Simona Vetter, Felix Kuehling
Cc: Arunpravin Paneer Selvam, amd-gfx, dri-devel, linux-kernel
On 11/4/25 09:35, Pierre-Eric Pelloux-Prayer wrote:
> Userspace jobs have drm_file.client_id as a unique identifier
> as job's owners. For kernel jobs, we can allocate arbitrary
> values - the risk of overlap with userspace ids is small (given
> that it's a u64 value).
> In the unlikely case the overlap happens, it'll only impact
> trace events.
>
> Since this ID is traced in the gpu_scheduler trace events, this
> allows to determine the source of each job sent to the hardware.
>
> To make grepping easier, the IDs are defined as they will appear
> in the trace output.
>
> Signed-off-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
> Acked-by: Alex Deucher <alexander.deucher@amd.com>
> Signed-off-by: Arunpravin Paneer Selvam <Arunpravin.PaneerSelvam@amd.com>
> Link: https://lore.kernel.org/r/20250604122827.2191-1-pierre-eric.pelloux-prayer@amd.com
Acked-by: Christian König <christian.koenig@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c | 3 ++-
> drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_job.c | 5 ++--
> drivers/gpu/drm/amd/amdgpu/amdgpu_job.h | 19 +++++++++++++-
> drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c | 3 ++-
> drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 3 ++-
> drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 28 +++++++++++++--------
> drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 3 ++-
> drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c | 3 ++-
> drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c | 5 ++--
> drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c | 8 +++---
> drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 6 +++--
> drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 2 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c | 4 ++-
> drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c | 4 ++-
> drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c | 12 +++++----
> drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c | 6 +++--
> drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 6 +++--
> drivers/gpu/drm/amd/amdkfd/kfd_migrate.c | 3 ++-
> 19 files changed, 84 insertions(+), 41 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> index 3d24f9cd750a..29c927f4d6df 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
> @@ -1549,7 +1549,8 @@ static int amdgpu_gfx_run_cleaner_shader_job(struct amdgpu_ring *ring)
> owner = (void *)(unsigned long)atomic_inc_return(&counter);
>
> r = amdgpu_job_alloc_with_ib(ring->adev, &entity, owner,
> - 64, 0, &job);
> + 64, 0, &job,
> + AMDGPU_KERNEL_JOB_ID_CLEANER_SHADER);
> if (r)
> goto err;
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
> index 97b562a79ea8..9dcf51991b5b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
> @@ -690,7 +690,7 @@ void amdgpu_gmc_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
> r = amdgpu_job_alloc_with_ib(ring->adev, &adev->mman.high_pr,
> AMDGPU_FENCE_OWNER_UNDEFINED,
> 16 * 4, AMDGPU_IB_POOL_IMMEDIATE,
> - &job);
> + &job, AMDGPU_KERNEL_JOB_ID_FLUSH_GPU_TLB);
> if (r)
> goto error_alloc;
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
> index 55c7e104d5ca..3457bd649623 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
> @@ -234,11 +234,12 @@ int amdgpu_job_alloc(struct amdgpu_device *adev, struct amdgpu_vm *vm,
> int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev,
> struct drm_sched_entity *entity, void *owner,
> size_t size, enum amdgpu_ib_pool_type pool_type,
> - struct amdgpu_job **job)
> + struct amdgpu_job **job, u64 k_job_id)
> {
> int r;
>
> - r = amdgpu_job_alloc(adev, NULL, entity, owner, 1, job, 0);
> + r = amdgpu_job_alloc(adev, NULL, entity, owner, 1, job,
> + k_job_id);
> if (r)
> return r;
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h
> index d25f1fcf0242..7abf069d17d4 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h
> @@ -44,6 +44,22 @@
> struct amdgpu_fence;
> enum amdgpu_ib_pool_type;
>
> +/* Internal kernel job ids. (decreasing values, starting from U64_MAX). */
> +#define AMDGPU_KERNEL_JOB_ID_VM_UPDATE (18446744073709551615ULL)
> +#define AMDGPU_KERNEL_JOB_ID_VM_UPDATE_PDES (18446744073709551614ULL)
> +#define AMDGPU_KERNEL_JOB_ID_VM_UPDATE_RANGE (18446744073709551613ULL)
> +#define AMDGPU_KERNEL_JOB_ID_VM_PT_CLEAR (18446744073709551612ULL)
> +#define AMDGPU_KERNEL_JOB_ID_TTM_MAP_BUFFER (18446744073709551611ULL)
> +#define AMDGPU_KERNEL_JOB_ID_TTM_ACCESS_MEMORY_SDMA (18446744073709551610ULL)
> +#define AMDGPU_KERNEL_JOB_ID_TTM_COPY_BUFFER (18446744073709551609ULL)
> +#define AMDGPU_KERNEL_JOB_ID_CLEAR_ON_RELEASE (18446744073709551608ULL)
> +#define AMDGPU_KERNEL_JOB_ID_MOVE_BLIT (18446744073709551607ULL)
> +#define AMDGPU_KERNEL_JOB_ID_TTM_CLEAR_BUFFER (18446744073709551606ULL)
> +#define AMDGPU_KERNEL_JOB_ID_CLEANER_SHADER (18446744073709551605ULL)
> +#define AMDGPU_KERNEL_JOB_ID_FLUSH_GPU_TLB (18446744073709551604ULL)
> +#define AMDGPU_KERNEL_JOB_ID_KFD_GART_MAP (18446744073709551603ULL)
> +#define AMDGPU_KERNEL_JOB_ID_VCN_RING_TEST (18446744073709551602ULL)
> +
> struct amdgpu_job {
> struct drm_sched_job base;
> struct amdgpu_vm *vm;
> @@ -97,7 +113,8 @@ int amdgpu_job_alloc(struct amdgpu_device *adev, struct amdgpu_vm *vm,
> int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev,
> struct drm_sched_entity *entity, void *owner,
> size_t size, enum amdgpu_ib_pool_type pool_type,
> - struct amdgpu_job **job);
> + struct amdgpu_job **job,
> + u64 k_job_id);
> void amdgpu_job_set_resources(struct amdgpu_job *job, struct amdgpu_bo *gds,
> struct amdgpu_bo *gws, struct amdgpu_bo *oa);
> void amdgpu_job_free_resources(struct amdgpu_job *job);
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c
> index 91678621f1ff..63ee6ba6a931 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.c
> @@ -196,7 +196,8 @@ static int amdgpu_jpeg_dec_set_reg(struct amdgpu_ring *ring, uint32_t handle,
> int i, r;
>
> r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL, ib_size_dw * 4,
> - AMDGPU_IB_POOL_DIRECT, &job);
> + AMDGPU_IB_POOL_DIRECT, &job,
> + AMDGPU_KERNEL_JOB_ID_VCN_RING_TEST);
> if (r)
> return r;
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> index fe486988a738..e08f58de4b17 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> @@ -1321,7 +1321,8 @@ void amdgpu_bo_release_notify(struct ttm_buffer_object *bo)
> if (r)
> goto out;
>
> - r = amdgpu_fill_buffer(abo, 0, &bo->base._resv, &fence, true);
> + r = amdgpu_fill_buffer(abo, 0, &bo->base._resv, &fence, true,
> + AMDGPU_KERNEL_JOB_ID_CLEAR_ON_RELEASE);
> if (WARN_ON(r))
> goto out;
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> index e226c3aff7d7..326476089db3 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> @@ -227,7 +227,8 @@ static int amdgpu_ttm_map_buffer(struct ttm_buffer_object *bo,
> r = amdgpu_job_alloc_with_ib(adev, &adev->mman.high_pr,
> AMDGPU_FENCE_OWNER_UNDEFINED,
> num_dw * 4 + num_bytes,
> - AMDGPU_IB_POOL_DELAYED, &job);
> + AMDGPU_IB_POOL_DELAYED, &job,
> + AMDGPU_KERNEL_JOB_ID_TTM_MAP_BUFFER);
> if (r)
> return r;
>
> @@ -406,7 +407,7 @@ static int amdgpu_move_blit(struct ttm_buffer_object *bo,
> struct dma_fence *wipe_fence = NULL;
>
> r = amdgpu_fill_buffer(abo, 0, NULL, &wipe_fence,
> - false);
> + false, AMDGPU_KERNEL_JOB_ID_MOVE_BLIT);
> if (r) {
> goto error;
> } else if (wipe_fence) {
> @@ -1488,7 +1489,8 @@ static int amdgpu_ttm_access_memory_sdma(struct ttm_buffer_object *bo,
> r = amdgpu_job_alloc_with_ib(adev, &adev->mman.high_pr,
> AMDGPU_FENCE_OWNER_UNDEFINED,
> num_dw * 4, AMDGPU_IB_POOL_DELAYED,
> - &job);
> + &job,
> + AMDGPU_KERNEL_JOB_ID_TTM_ACCESS_MEMORY_SDMA);
> if (r)
> goto out;
>
> @@ -2212,7 +2214,7 @@ static int amdgpu_ttm_prepare_job(struct amdgpu_device *adev,
> struct dma_resv *resv,
> bool vm_needs_flush,
> struct amdgpu_job **job,
> - bool delayed)
> + bool delayed, u64 k_job_id)
> {
> enum amdgpu_ib_pool_type pool = direct_submit ?
> AMDGPU_IB_POOL_DIRECT :
> @@ -2222,7 +2224,7 @@ static int amdgpu_ttm_prepare_job(struct amdgpu_device *adev,
> &adev->mman.high_pr;
> r = amdgpu_job_alloc_with_ib(adev, entity,
> AMDGPU_FENCE_OWNER_UNDEFINED,
> - num_dw * 4, pool, job);
> + num_dw * 4, pool, job, k_job_id);
> if (r)
> return r;
>
> @@ -2262,7 +2264,8 @@ int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
> num_loops = DIV_ROUND_UP(byte_count, max_bytes);
> num_dw = ALIGN(num_loops * adev->mman.buffer_funcs->copy_num_dw, 8);
> r = amdgpu_ttm_prepare_job(adev, direct_submit, num_dw,
> - resv, vm_needs_flush, &job, false);
> + resv, vm_needs_flush, &job, false,
> + AMDGPU_KERNEL_JOB_ID_TTM_COPY_BUFFER);
> if (r)
> return r;
>
> @@ -2297,7 +2300,8 @@ static int amdgpu_ttm_fill_mem(struct amdgpu_ring *ring, uint32_t src_data,
> uint64_t dst_addr, uint32_t byte_count,
> struct dma_resv *resv,
> struct dma_fence **fence,
> - bool vm_needs_flush, bool delayed)
> + bool vm_needs_flush, bool delayed,
> + u64 k_job_id)
> {
> struct amdgpu_device *adev = ring->adev;
> unsigned int num_loops, num_dw;
> @@ -2310,7 +2314,7 @@ static int amdgpu_ttm_fill_mem(struct amdgpu_ring *ring, uint32_t src_data,
> num_loops = DIV_ROUND_UP_ULL(byte_count, max_bytes);
> num_dw = ALIGN(num_loops * adev->mman.buffer_funcs->fill_num_dw, 8);
> r = amdgpu_ttm_prepare_job(adev, false, num_dw, resv, vm_needs_flush,
> - &job, delayed);
> + &job, delayed, k_job_id);
> if (r)
> return r;
>
> @@ -2380,7 +2384,8 @@ int amdgpu_ttm_clear_buffer(struct amdgpu_bo *bo,
> goto err;
>
> r = amdgpu_ttm_fill_mem(ring, 0, addr, size, resv,
> - &next, true, true);
> + &next, true, true,
> + AMDGPU_KERNEL_JOB_ID_TTM_CLEAR_BUFFER);
> if (r)
> goto err;
>
> @@ -2399,7 +2404,8 @@ int amdgpu_fill_buffer(struct amdgpu_bo *bo,
> uint32_t src_data,
> struct dma_resv *resv,
> struct dma_fence **f,
> - bool delayed)
> + bool delayed,
> + u64 k_job_id)
> {
> struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
> struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
> @@ -2429,7 +2435,7 @@ int amdgpu_fill_buffer(struct amdgpu_bo *bo,
> goto error;
>
> r = amdgpu_ttm_fill_mem(ring, src_data, to, cur_size, resv,
> - &next, true, delayed);
> + &next, true, delayed, k_job_id);
> if (r)
> goto error;
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
> index 054d48823d5f..577ee04ce0bf 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
> @@ -175,7 +175,8 @@ int amdgpu_fill_buffer(struct amdgpu_bo *bo,
> uint32_t src_data,
> struct dma_resv *resv,
> struct dma_fence **fence,
> - bool delayed);
> + bool delayed,
> + u64 k_job_id);
>
> int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo);
> void amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo);
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
> index 74758b5ffc6c..5c38f0d30c87 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
> @@ -1136,7 +1136,8 @@ static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo,
> r = amdgpu_job_alloc_with_ib(ring->adev, &adev->uvd.entity,
> AMDGPU_FENCE_OWNER_UNDEFINED,
> 64, direct ? AMDGPU_IB_POOL_DIRECT :
> - AMDGPU_IB_POOL_DELAYED, &job);
> + AMDGPU_IB_POOL_DELAYED, &job,
> + AMDGPU_KERNEL_JOB_ID_VCN_RING_TEST);
> if (r)
> return r;
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
> index b9060bcd4806..ce318f5de047 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
> @@ -449,7 +449,7 @@ static int amdgpu_vce_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
> r = amdgpu_job_alloc_with_ib(ring->adev, &ring->adev->vce.entity,
> AMDGPU_FENCE_OWNER_UNDEFINED,
> ib_size_dw * 4, AMDGPU_IB_POOL_DIRECT,
> - &job);
> + &job, AMDGPU_KERNEL_JOB_ID_VCN_RING_TEST);
> if (r)
> return r;
>
> @@ -540,7 +540,8 @@ static int amdgpu_vce_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
> AMDGPU_FENCE_OWNER_UNDEFINED,
> ib_size_dw * 4,
> direct ? AMDGPU_IB_POOL_DIRECT :
> - AMDGPU_IB_POOL_DELAYED, &job);
> + AMDGPU_IB_POOL_DELAYED, &job,
> + AMDGPU_KERNEL_JOB_ID_VCN_RING_TEST);
> if (r)
> return r;
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
> index 5ae7cc0d5f57..5e0786ea911b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
> @@ -626,7 +626,7 @@ static int amdgpu_vcn_dec_send_msg(struct amdgpu_ring *ring,
>
> r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL,
> 64, AMDGPU_IB_POOL_DIRECT,
> - &job);
> + &job, AMDGPU_KERNEL_JOB_ID_VCN_RING_TEST);
> if (r)
> goto err;
>
> @@ -806,7 +806,7 @@ static int amdgpu_vcn_dec_sw_send_msg(struct amdgpu_ring *ring,
>
> r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL,
> ib_size_dw * 4, AMDGPU_IB_POOL_DIRECT,
> - &job);
> + &job, AMDGPU_KERNEL_JOB_ID_VCN_RING_TEST);
> if (r)
> goto err;
>
> @@ -936,7 +936,7 @@ static int amdgpu_vcn_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t hand
>
> r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL,
> ib_size_dw * 4, AMDGPU_IB_POOL_DIRECT,
> - &job);
> + &job, AMDGPU_KERNEL_JOB_ID_VCN_RING_TEST);
> if (r)
> return r;
>
> @@ -1003,7 +1003,7 @@ static int amdgpu_vcn_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t han
>
> r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL,
> ib_size_dw * 4, AMDGPU_IB_POOL_DIRECT,
> - &job);
> + &job, AMDGPU_KERNEL_JOB_ID_VCN_RING_TEST);
> if (r)
> return r;
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> index db66b4232de0..2f8e83f840a8 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> @@ -983,7 +983,8 @@ int amdgpu_vm_update_pdes(struct amdgpu_device *adev,
> params.vm = vm;
> params.immediate = immediate;
>
> - r = vm->update_funcs->prepare(¶ms, NULL);
> + r = vm->update_funcs->prepare(¶ms, NULL,
> + AMDGPU_KERNEL_JOB_ID_VM_UPDATE_PDES);
> if (r)
> goto error;
>
> @@ -1152,7 +1153,8 @@ int amdgpu_vm_update_range(struct amdgpu_device *adev, struct amdgpu_vm *vm,
> dma_fence_put(tmp);
> }
>
> - r = vm->update_funcs->prepare(¶ms, sync);
> + r = vm->update_funcs->prepare(¶ms, sync,
> + AMDGPU_KERNEL_JOB_ID_VM_UPDATE_RANGE);
> if (r)
> goto error_free;
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
> index 77207f4e448e..cf0ec94e8a07 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
> @@ -308,7 +308,7 @@ struct amdgpu_vm_update_params {
> struct amdgpu_vm_update_funcs {
> int (*map_table)(struct amdgpu_bo_vm *bo);
> int (*prepare)(struct amdgpu_vm_update_params *p,
> - struct amdgpu_sync *sync);
> + struct amdgpu_sync *sync, u64 k_job_id);
> int (*update)(struct amdgpu_vm_update_params *p,
> struct amdgpu_bo_vm *bo, uint64_t pe, uint64_t addr,
> unsigned count, uint32_t incr, uint64_t flags);
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c
> index 0c1ef5850a5e..22e2e5b47341 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.c
> @@ -40,12 +40,14 @@ static int amdgpu_vm_cpu_map_table(struct amdgpu_bo_vm *table)
> *
> * @p: see amdgpu_vm_update_params definition
> * @sync: sync obj with fences to wait on
> + * @k_job_id: the id for tracing/debug purposes
> *
> * Returns:
> * Negativ errno, 0 for success.
> */
> static int amdgpu_vm_cpu_prepare(struct amdgpu_vm_update_params *p,
> - struct amdgpu_sync *sync)
> + struct amdgpu_sync *sync,
> + u64 k_job_id)
> {
> if (!sync)
> return 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c
> index 30022123b0bf..f794fb1cc06e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.c
> @@ -26,6 +26,7 @@
> #include "amdgpu.h"
> #include "amdgpu_trace.h"
> #include "amdgpu_vm.h"
> +#include "amdgpu_job.h"
>
> /*
> * amdgpu_vm_pt_cursor - state for for_each_amdgpu_vm_pt
> @@ -395,7 +396,8 @@ int amdgpu_vm_pt_clear(struct amdgpu_device *adev, struct amdgpu_vm *vm,
> params.vm = vm;
> params.immediate = immediate;
>
> - r = vm->update_funcs->prepare(¶ms, NULL);
> + r = vm->update_funcs->prepare(¶ms, NULL,
> + AMDGPU_KERNEL_JOB_ID_VM_PT_CLEAR);
> if (r)
> goto exit;
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
> index 46d9fb433ab2..36805dcfa159 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.c
> @@ -40,7 +40,7 @@ static int amdgpu_vm_sdma_map_table(struct amdgpu_bo_vm *table)
>
> /* Allocate a new job for @count PTE updates */
> static int amdgpu_vm_sdma_alloc_job(struct amdgpu_vm_update_params *p,
> - unsigned int count)
> + unsigned int count, u64 k_job_id)
> {
> enum amdgpu_ib_pool_type pool = p->immediate ? AMDGPU_IB_POOL_IMMEDIATE
> : AMDGPU_IB_POOL_DELAYED;
> @@ -56,7 +56,7 @@ static int amdgpu_vm_sdma_alloc_job(struct amdgpu_vm_update_params *p,
> ndw = min(ndw, AMDGPU_VM_SDMA_MAX_NUM_DW);
>
> r = amdgpu_job_alloc_with_ib(p->adev, entity, AMDGPU_FENCE_OWNER_VM,
> - ndw * 4, pool, &p->job);
> + ndw * 4, pool, &p->job, k_job_id);
> if (r)
> return r;
>
> @@ -69,16 +69,17 @@ static int amdgpu_vm_sdma_alloc_job(struct amdgpu_vm_update_params *p,
> *
> * @p: see amdgpu_vm_update_params definition
> * @sync: amdgpu_sync object with fences to wait for
> + * @k_job_id: identifier of the job, for tracing purpose
> *
> * Returns:
> * Negativ errno, 0 for success.
> */
> static int amdgpu_vm_sdma_prepare(struct amdgpu_vm_update_params *p,
> - struct amdgpu_sync *sync)
> + struct amdgpu_sync *sync, u64 k_job_id)
> {
> int r;
>
> - r = amdgpu_vm_sdma_alloc_job(p, 0);
> + r = amdgpu_vm_sdma_alloc_job(p, 0, k_job_id);
> if (r)
> return r;
>
> @@ -249,7 +250,8 @@ static int amdgpu_vm_sdma_update(struct amdgpu_vm_update_params *p,
> if (r)
> return r;
>
> - r = amdgpu_vm_sdma_alloc_job(p, count);
> + r = amdgpu_vm_sdma_alloc_job(p, count,
> + AMDGPU_KERNEL_JOB_ID_VM_UPDATE);
> if (r)
> return r;
> }
> diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
> index 1c07b701d0e4..ceb94bbb03a4 100644
> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
> @@ -217,7 +217,8 @@ static int uvd_v6_0_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle
> int i, r;
>
> r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL, ib_size_dw * 4,
> - AMDGPU_IB_POOL_DIRECT, &job);
> + AMDGPU_IB_POOL_DIRECT, &job,
> + AMDGPU_KERNEL_JOB_ID_VCN_RING_TEST);
> if (r)
> return r;
>
> @@ -281,7 +282,8 @@ static int uvd_v6_0_enc_get_destroy_msg(struct amdgpu_ring *ring,
> int i, r;
>
> r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL, ib_size_dw * 4,
> - AMDGPU_IB_POOL_DIRECT, &job);
> + AMDGPU_IB_POOL_DIRECT, &job,
> + AMDGPU_KERNEL_JOB_ID_VCN_RING_TEST);
> if (r)
> return r;
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
> index 9d237b5937fb..1f8866f3f63c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
> @@ -225,7 +225,8 @@ static int uvd_v7_0_enc_get_create_msg(struct amdgpu_ring *ring, u32 handle,
> int i, r;
>
> r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL, ib_size_dw * 4,
> - AMDGPU_IB_POOL_DIRECT, &job);
> + AMDGPU_IB_POOL_DIRECT, &job,
> + AMDGPU_KERNEL_JOB_ID_VCN_RING_TEST);
> if (r)
> return r;
>
> @@ -288,7 +289,8 @@ static int uvd_v7_0_enc_get_destroy_msg(struct amdgpu_ring *ring, u32 handle,
> int i, r;
>
> r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL, ib_size_dw * 4,
> - AMDGPU_IB_POOL_DIRECT, &job);
> + AMDGPU_IB_POOL_DIRECT, &job,
> + AMDGPU_KERNEL_JOB_ID_VCN_RING_TEST);
> if (r)
> return r;
>
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
> index 3653c563ee9a..46c84fc60af1 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
> @@ -67,7 +67,8 @@ svm_migrate_gart_map(struct amdgpu_ring *ring, u64 npages,
> AMDGPU_FENCE_OWNER_UNDEFINED,
> num_dw * 4 + num_bytes,
> AMDGPU_IB_POOL_DELAYED,
> - &job);
> + &job,
> + AMDGPU_KERNEL_JOB_ID_KFD_GART_MAP);
> if (r)
> return r;
>
^ permalink raw reply [flat|nested] 40+ messages in thread
* [PATCH v1 02/20] drm/ttm: rework pipelined eviction fence handling
2025-11-04 8:35 [PATCH v1 00/20] drm/amdgpu: use all SDMA instances for TTM clears and moves Pierre-Eric Pelloux-Prayer
2025-11-04 8:35 ` [PATCH v1 01/20] drm/amdgpu: give each kernel job a unique id Pierre-Eric Pelloux-Prayer
@ 2025-11-04 8:35 ` Pierre-Eric Pelloux-Prayer
2025-11-04 14:12 ` Christian König
2025-11-04 8:35 ` [PATCH v1 03/20] drm/amdgpu: remove direct_submit arg from amdgpu_copy_buffer Pierre-Eric Pelloux-Prayer
` (17 subsequent siblings)
19 siblings, 1 reply; 40+ messages in thread
From: Pierre-Eric Pelloux-Prayer @ 2025-11-04 8:35 UTC (permalink / raw)
To: Alex Deucher, Christian König, David Airlie, Simona Vetter,
Huang Rui, Matthew Auld, Matthew Brost, Maarten Lankhorst,
Maxime Ripard, Thomas Zimmermann, Sumit Semwal
Cc: Pierre-Eric Pelloux-Prayer, amd-gfx, dri-devel, linux-kernel,
linux-media, linaro-mm-sig
Until now ttm stored a single pipelined eviction fence which means
drivers had to use a single entity for these evictions.
To lift this requirement, this commit allows up to 8 entities to
be used.
Ideally a dma_resv object would have been used as a container of
the eviction fences, but the locking rules makes it complex.
dma_resv all have the same ww_class, which means "Attempting to
lock more mutexes after ww_acquire_done." is an error.
One alternative considered was to introduced a 2nd ww_class for
specific resv to hold a single "transient" lock (= the resv lock
would only be held for a short period, without taking any other
locks).
The other option, is to statically reserve a fence array, and
extend the existing code to deal with N fences, instead of 1.
The driver is still responsible to reserve the correct number
of fence slots.
Lastly ttm_resource_manager.pipelined_eviction.n_fences is
initialized to 1, so the new behavior is opt-in.
Signed-off-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 8 ++-
.../gpu/drm/ttm/tests/ttm_bo_validate_test.c | 13 +++--
drivers/gpu/drm/ttm/tests/ttm_resource_test.c | 5 +-
drivers/gpu/drm/ttm/ttm_bo.c | 56 ++++++++++++-------
drivers/gpu/drm/ttm/ttm_bo_util.c | 36 ++++++++++--
drivers/gpu/drm/ttm/ttm_resource.c | 45 ++++++++++-----
include/drm/ttm/ttm_resource.h | 34 ++++++++---
7 files changed, 139 insertions(+), 58 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 326476089db3..c66f00434991 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -2156,7 +2156,7 @@ void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable)
{
struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM);
uint64_t size;
- int r;
+ int r, i;
if (!adev->mman.initialized || amdgpu_in_reset(adev) ||
adev->mman.buffer_funcs_enabled == enable || adev->gmc.is_app_apu)
@@ -2190,8 +2190,10 @@ void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable)
} else {
drm_sched_entity_destroy(&adev->mman.high_pr);
drm_sched_entity_destroy(&adev->mman.low_pr);
- dma_fence_put(man->move);
- man->move = NULL;
+ for (i = 0; i < TTM_FENCES_MAX_SLOT_COUNT; i++) {
+ dma_fence_put(man->pipelined_eviction.fences[i]);
+ man->pipelined_eviction.fences[i] = NULL;
+ }
}
/* this just adjusts TTM size idea, which sets lpfn to the correct value */
diff --git a/drivers/gpu/drm/ttm/tests/ttm_bo_validate_test.c b/drivers/gpu/drm/ttm/tests/ttm_bo_validate_test.c
index 3148f5d3dbd6..1396674e1923 100644
--- a/drivers/gpu/drm/ttm/tests/ttm_bo_validate_test.c
+++ b/drivers/gpu/drm/ttm/tests/ttm_bo_validate_test.c
@@ -651,7 +651,8 @@ static void ttm_bo_validate_move_fence_signaled(struct kunit *test)
int err;
man = ttm_manager_type(priv->ttm_dev, mem_type);
- man->move = dma_fence_get_stub();
+ man->pipelined_eviction.n_fences = 1;
+ man->pipelined_eviction.fences[0] = dma_fence_get_stub();
bo = ttm_bo_kunit_init(test, test->priv, size, NULL);
bo->type = bo_type;
@@ -668,7 +669,7 @@ static void ttm_bo_validate_move_fence_signaled(struct kunit *test)
KUNIT_EXPECT_EQ(test, ctx.bytes_moved, size);
ttm_bo_put(bo);
- dma_fence_put(man->move);
+ dma_fence_put(man->pipelined_eviction.fences[0]);
}
static const struct ttm_bo_validate_test_case ttm_bo_validate_wait_cases[] = {
@@ -732,9 +733,10 @@ static void ttm_bo_validate_move_fence_not_signaled(struct kunit *test)
spin_lock_init(&fence_lock);
man = ttm_manager_type(priv->ttm_dev, fst_mem);
- man->move = alloc_mock_fence(test);
+ man->pipelined_eviction.n_fences = 1;
+ man->pipelined_eviction.fences[0] = alloc_mock_fence(test);
- task = kthread_create(threaded_fence_signal, man->move, "move-fence-signal");
+ task = kthread_create(threaded_fence_signal, man->pipelined_eviction.fences[0], "move-fence-signal");
if (IS_ERR(task))
KUNIT_FAIL(test, "Couldn't create move fence signal task\n");
@@ -742,7 +744,8 @@ static void ttm_bo_validate_move_fence_not_signaled(struct kunit *test)
err = ttm_bo_validate(bo, placement_val, &ctx_val);
dma_resv_unlock(bo->base.resv);
- dma_fence_wait_timeout(man->move, false, MAX_SCHEDULE_TIMEOUT);
+ dma_fence_wait_timeout(man->pipelined_eviction.fences[0], false, MAX_SCHEDULE_TIMEOUT);
+ man->pipelined_eviction.fences[0] = NULL;
KUNIT_EXPECT_EQ(test, err, 0);
KUNIT_EXPECT_EQ(test, ctx_val.bytes_moved, size);
diff --git a/drivers/gpu/drm/ttm/tests/ttm_resource_test.c b/drivers/gpu/drm/ttm/tests/ttm_resource_test.c
index e6ea2bd01f07..6dfdf759a491 100644
--- a/drivers/gpu/drm/ttm/tests/ttm_resource_test.c
+++ b/drivers/gpu/drm/ttm/tests/ttm_resource_test.c
@@ -207,6 +207,7 @@ static void ttm_resource_manager_init_basic(struct kunit *test)
struct ttm_resource_test_priv *priv = test->priv;
struct ttm_resource_manager *man;
size_t size = SZ_16K;
+ int i;
man = kunit_kzalloc(test, sizeof(*man), GFP_KERNEL);
KUNIT_ASSERT_NOT_NULL(test, man);
@@ -216,8 +217,8 @@ static void ttm_resource_manager_init_basic(struct kunit *test)
KUNIT_ASSERT_PTR_EQ(test, man->bdev, priv->devs->ttm_dev);
KUNIT_ASSERT_EQ(test, man->size, size);
KUNIT_ASSERT_EQ(test, man->usage, 0);
- KUNIT_ASSERT_NULL(test, man->move);
- KUNIT_ASSERT_NOT_NULL(test, &man->move_lock);
+ for (i = 0; i < TTM_FENCES_MAX_SLOT_COUNT; i++)
+ KUNIT_ASSERT_NULL(test, man->pipelined_eviction.fences[i]);
for (int i = 0; i < TTM_MAX_BO_PRIORITY; ++i)
KUNIT_ASSERT_TRUE(test, list_empty(&man->lru[i]));
diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c
index f4d9e68b21e7..bc6d4a6c6d70 100644
--- a/drivers/gpu/drm/ttm/ttm_bo.c
+++ b/drivers/gpu/drm/ttm/ttm_bo.c
@@ -658,34 +658,48 @@ void ttm_bo_unpin(struct ttm_buffer_object *bo)
EXPORT_SYMBOL(ttm_bo_unpin);
/*
- * Add the last move fence to the BO as kernel dependency and reserve a new
- * fence slot.
+ * Add the pipelined eviction fencesto the BO as kernel dependency and reserve new
+ * fence slots.
*/
-static int ttm_bo_add_move_fence(struct ttm_buffer_object *bo,
- struct ttm_resource_manager *man,
- bool no_wait_gpu)
+static int ttm_bo_add_pipelined_eviction_fences(struct ttm_buffer_object *bo,
+ struct ttm_resource_manager *man,
+ bool no_wait_gpu)
{
+ struct dma_fence *fences_to_add[TTM_FENCES_MAX_SLOT_COUNT] = {};
struct dma_fence *fence;
- int ret;
+ bool all_signaled = true, signaled;
+ int i, n = 0;
- spin_lock(&man->move_lock);
- fence = dma_fence_get(man->move);
- spin_unlock(&man->move_lock);
+ spin_lock(&man->pipelined_eviction.lock);
+ for (i = 0; i < man->pipelined_eviction.n_fences; i++) {
+ fence = man->pipelined_eviction.fences[i];
+ if (!fence)
+ continue;
+ signaled = dma_fence_is_signaled(fence);
- if (!fence)
+ if (signaled) {
+ dma_fence_put(man->pipelined_eviction.fences[i]);
+ man->pipelined_eviction.fences[i] = NULL;
+ } else {
+ all_signaled = false;
+ if (no_wait_gpu) {
+ spin_unlock(&man->pipelined_eviction.lock);
+ return -EBUSY;
+ }
+ fences_to_add[n++] = dma_fence_get(fence);
+ }
+ }
+ spin_unlock(&man->pipelined_eviction.lock);
+
+ if (all_signaled)
return 0;
- if (no_wait_gpu) {
- ret = dma_fence_is_signaled(fence) ? 0 : -EBUSY;
- dma_fence_put(fence);
- return ret;
+ for (i = 0; i < n; i++) {
+ dma_resv_add_fence(bo->base.resv, fences_to_add[i], DMA_RESV_USAGE_KERNEL);
+ dma_fence_put(fences_to_add[i]);
}
- dma_resv_add_fence(bo->base.resv, fence, DMA_RESV_USAGE_KERNEL);
-
- ret = dma_resv_reserve_fences(bo->base.resv, 1);
- dma_fence_put(fence);
- return ret;
+ return dma_resv_reserve_fences(bo->base.resv, TTM_FENCES_MAX_SLOT_COUNT);
}
/**
@@ -718,7 +732,7 @@ static int ttm_bo_alloc_resource(struct ttm_buffer_object *bo,
int i, ret;
ticket = dma_resv_locking_ctx(bo->base.resv);
- ret = dma_resv_reserve_fences(bo->base.resv, 1);
+ ret = dma_resv_reserve_fences(bo->base.resv, TTM_FENCES_MAX_SLOT_COUNT);
if (unlikely(ret))
return ret;
@@ -757,7 +771,7 @@ static int ttm_bo_alloc_resource(struct ttm_buffer_object *bo,
return ret;
}
- ret = ttm_bo_add_move_fence(bo, man, ctx->no_wait_gpu);
+ ret = ttm_bo_add_pipelined_eviction_fences(bo, man, ctx->no_wait_gpu);
if (unlikely(ret)) {
ttm_resource_free(bo, res);
if (ret == -EBUSY)
diff --git a/drivers/gpu/drm/ttm/ttm_bo_util.c b/drivers/gpu/drm/ttm/ttm_bo_util.c
index acbbca9d5c92..ada8af965acf 100644
--- a/drivers/gpu/drm/ttm/ttm_bo_util.c
+++ b/drivers/gpu/drm/ttm/ttm_bo_util.c
@@ -258,7 +258,7 @@ static int ttm_buffer_object_transfer(struct ttm_buffer_object *bo,
ret = dma_resv_trylock(&fbo->base.base._resv);
WARN_ON(!ret);
- ret = dma_resv_reserve_fences(&fbo->base.base._resv, 1);
+ ret = dma_resv_reserve_fences(&fbo->base.base._resv, TTM_FENCES_MAX_SLOT_COUNT);
if (ret) {
dma_resv_unlock(&fbo->base.base._resv);
kfree(fbo);
@@ -646,6 +646,8 @@ static void ttm_bo_move_pipeline_evict(struct ttm_buffer_object *bo,
{
struct ttm_device *bdev = bo->bdev;
struct ttm_resource_manager *from;
+ struct dma_fence *tmp;
+ int i, free_slot = -1;
from = ttm_manager_type(bdev, bo->resource->mem_type);
@@ -653,13 +655,35 @@ static void ttm_bo_move_pipeline_evict(struct ttm_buffer_object *bo,
* BO doesn't have a TTM we need to bind/unbind. Just remember
* this eviction and free up the allocation
*/
- spin_lock(&from->move_lock);
- if (!from->move || dma_fence_is_later(fence, from->move)) {
- dma_fence_put(from->move);
- from->move = dma_fence_get(fence);
+ spin_lock(&from->pipelined_eviction.lock);
+ for (i = 0; i < from->pipelined_eviction.n_fences; i++) {
+ tmp = from->pipelined_eviction.fences[i];
+ if (!tmp) {
+ if (free_slot < 0)
+ free_slot = i;
+ continue;
+ }
+ if (fence->context != tmp->context)
+ continue;
+ if (dma_fence_is_later(fence, tmp)) {
+ dma_fence_put(tmp);
+ free_slot = i;
+ break;
+ }
+ goto unlock;
+ }
+ if (free_slot >= 0) {
+ from->pipelined_eviction.fences[free_slot] = dma_fence_get(fence);
+ } else {
+ WARN(1, "not enough fence slots for all fence contexts");
+ spin_unlock(&from->pipelined_eviction.lock);
+ dma_fence_wait(fence, false);
+ goto end;
}
- spin_unlock(&from->move_lock);
+unlock:
+ spin_unlock(&from->pipelined_eviction.lock);
+end:
ttm_resource_free(bo, &bo->resource);
}
diff --git a/drivers/gpu/drm/ttm/ttm_resource.c b/drivers/gpu/drm/ttm/ttm_resource.c
index e2c82ad07eb4..ae0d4621cc55 100644
--- a/drivers/gpu/drm/ttm/ttm_resource.c
+++ b/drivers/gpu/drm/ttm/ttm_resource.c
@@ -523,14 +523,19 @@ void ttm_resource_manager_init(struct ttm_resource_manager *man,
{
unsigned i;
- spin_lock_init(&man->move_lock);
man->bdev = bdev;
man->size = size;
man->usage = 0;
for (i = 0; i < TTM_MAX_BO_PRIORITY; ++i)
INIT_LIST_HEAD(&man->lru[i]);
- man->move = NULL;
+ spin_lock_init(&man->pipelined_eviction.lock);
+ for (i = 0; i < TTM_FENCES_MAX_SLOT_COUNT; i++)
+ man->pipelined_eviction.fences[i] = NULL;
+ /* Can be overridden by drivers that wants to use more than 1 entity
+ * for moves and evictions (limited to TTM_FENCES_MAX_SLOT_COUNT).
+ */
+ man->pipelined_eviction.n_fences = 1;
}
EXPORT_SYMBOL(ttm_resource_manager_init);
@@ -551,7 +556,7 @@ int ttm_resource_manager_evict_all(struct ttm_device *bdev,
.no_wait_gpu = false,
};
struct dma_fence *fence;
- int ret;
+ int ret, i;
do {
ret = ttm_bo_evict_first(bdev, man, &ctx);
@@ -561,18 +566,32 @@ int ttm_resource_manager_evict_all(struct ttm_device *bdev,
if (ret && ret != -ENOENT)
return ret;
- spin_lock(&man->move_lock);
- fence = dma_fence_get(man->move);
- spin_unlock(&man->move_lock);
+ ret = 0;
- if (fence) {
- ret = dma_fence_wait(fence, false);
- dma_fence_put(fence);
- if (ret)
- return ret;
- }
+ do {
+ fence = NULL;
- return 0;
+ spin_lock(&man->pipelined_eviction.lock);
+ for (i = 0; i < man->pipelined_eviction.n_fences; i++) {
+ fence = man->pipelined_eviction.fences[i];
+ man->pipelined_eviction.fences[i] = NULL;
+ if (fence)
+ break;
+ }
+ spin_unlock(&man->pipelined_eviction.lock);
+
+ if (fence) {
+ ret = dma_fence_wait(fence, false);
+ dma_fence_put(fence);
+
+ if (ret)
+ break;
+ } else {
+ break;
+ }
+ } while (1);
+
+ return ret;
}
EXPORT_SYMBOL(ttm_resource_manager_evict_all);
diff --git a/include/drm/ttm/ttm_resource.h b/include/drm/ttm/ttm_resource.h
index f49daa504c36..898c429b37ad 100644
--- a/include/drm/ttm/ttm_resource.h
+++ b/include/drm/ttm/ttm_resource.h
@@ -50,6 +50,15 @@ struct io_mapping;
struct sg_table;
struct scatterlist;
+/**
+ * define TTM_FENCES_MAX_SLOT_COUNT - How many entities can be used for evictions
+ *
+ * Pipelined evictions can be spread on multiple entities. This
+ * is the max number of entities that can be used by the driver
+ * for that purpose.
+ */
+#define TTM_FENCES_MAX_SLOT_COUNT 8
+
/**
* enum ttm_lru_item_type - enumerate ttm_lru_item subclasses
*/
@@ -180,8 +189,10 @@ struct ttm_resource_manager_func {
* @size: Size of the managed region.
* @bdev: ttm device this manager belongs to
* @func: structure pointer implementing the range manager. See above
- * @move_lock: lock for move fence
- * @move: The fence of the last pipelined move operation.
+ * @pipelined_eviction.lock: lock for eviction fences
+ * @pipelined_eviction.n_fences: The number of fences allowed in the array. If
+ * 0, pipelined evictions aren't used.
+ * @pipelined_eviction.fences: The fences of the last pipelined move operation.
* @lru: The lru list for this memory type.
*
* This structure is used to identify and manage memory types for a device.
@@ -195,12 +206,15 @@ struct ttm_resource_manager {
struct ttm_device *bdev;
uint64_t size;
const struct ttm_resource_manager_func *func;
- spinlock_t move_lock;
- /*
- * Protected by @move_lock.
+ /* This is very similar to a dma_resv object, but locking rules make
+ * it difficult to use a it in this context.
*/
- struct dma_fence *move;
+ struct {
+ spinlock_t lock;
+ int n_fences;
+ struct dma_fence *fences[TTM_FENCES_MAX_SLOT_COUNT];
+ } pipelined_eviction;
/*
* Protected by the bdev->lru_lock.
@@ -421,8 +435,12 @@ static inline bool ttm_resource_manager_used(struct ttm_resource_manager *man)
static inline void
ttm_resource_manager_cleanup(struct ttm_resource_manager *man)
{
- dma_fence_put(man->move);
- man->move = NULL;
+ int i;
+
+ for (i = 0; i < TTM_FENCES_MAX_SLOT_COUNT; i++) {
+ dma_fence_put(man->pipelined_eviction.fences[i]);
+ man->pipelined_eviction.fences[i] = NULL;
+ }
}
void ttm_lru_bulk_move_init(struct ttm_lru_bulk_move *bulk);
--
2.43.0
^ permalink raw reply [flat|nested] 40+ messages in thread* Re: [PATCH v1 02/20] drm/ttm: rework pipelined eviction fence handling
2025-11-04 8:35 ` [PATCH v1 02/20] drm/ttm: rework pipelined eviction fence handling Pierre-Eric Pelloux-Prayer
@ 2025-11-04 14:12 ` Christian König
2025-11-05 10:34 ` Pierre-Eric Pelloux-Prayer
0 siblings, 1 reply; 40+ messages in thread
From: Christian König @ 2025-11-04 14:12 UTC (permalink / raw)
To: Pierre-Eric Pelloux-Prayer, Alex Deucher, David Airlie,
Simona Vetter, Huang Rui, Matthew Auld, Matthew Brost,
Maarten Lankhorst, Maxime Ripard, Thomas Zimmermann,
Sumit Semwal
Cc: amd-gfx, dri-devel, linux-kernel, linux-media, linaro-mm-sig
On 11/4/25 09:35, Pierre-Eric Pelloux-Prayer wrote:
> Until now ttm stored a single pipelined eviction fence which means
> drivers had to use a single entity for these evictions.
>
> To lift this requirement, this commit allows up to 8 entities to
> be used.
>
> Ideally a dma_resv object would have been used as a container of
> the eviction fences, but the locking rules makes it complex.
> dma_resv all have the same ww_class, which means "Attempting to
> lock more mutexes after ww_acquire_done." is an error.
>
> One alternative considered was to introduced a 2nd ww_class for
> specific resv to hold a single "transient" lock (= the resv lock
> would only be held for a short period, without taking any other
> locks).
>
> The other option, is to statically reserve a fence array, and
> extend the existing code to deal with N fences, instead of 1.
>
> The driver is still responsible to reserve the correct number
> of fence slots.
>
> Lastly ttm_resource_manager.pipelined_eviction.n_fences is
> initialized to 1, so the new behavior is opt-in.
>
> Signed-off-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 8 ++-
> .../gpu/drm/ttm/tests/ttm_bo_validate_test.c | 13 +++--
> drivers/gpu/drm/ttm/tests/ttm_resource_test.c | 5 +-
> drivers/gpu/drm/ttm/ttm_bo.c | 56 ++++++++++++-------
> drivers/gpu/drm/ttm/ttm_bo_util.c | 36 ++++++++++--
> drivers/gpu/drm/ttm/ttm_resource.c | 45 ++++++++++-----
> include/drm/ttm/ttm_resource.h | 34 ++++++++---
> 7 files changed, 139 insertions(+), 58 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> index 326476089db3..c66f00434991 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> @@ -2156,7 +2156,7 @@ void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable)
> {
> struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM);
> uint64_t size;
> - int r;
> + int r, i;
>
> if (!adev->mman.initialized || amdgpu_in_reset(adev) ||
> adev->mman.buffer_funcs_enabled == enable || adev->gmc.is_app_apu)
> @@ -2190,8 +2190,10 @@ void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable)
> } else {
> drm_sched_entity_destroy(&adev->mman.high_pr);
> drm_sched_entity_destroy(&adev->mman.low_pr);
> - dma_fence_put(man->move);
> - man->move = NULL;
> + for (i = 0; i < TTM_FENCES_MAX_SLOT_COUNT; i++) {
> + dma_fence_put(man->pipelined_eviction.fences[i]);
> + man->pipelined_eviction.fences[i] = NULL;
> + }
> }
>
> /* this just adjusts TTM size idea, which sets lpfn to the correct value */
> diff --git a/drivers/gpu/drm/ttm/tests/ttm_bo_validate_test.c b/drivers/gpu/drm/ttm/tests/ttm_bo_validate_test.c
> index 3148f5d3dbd6..1396674e1923 100644
> --- a/drivers/gpu/drm/ttm/tests/ttm_bo_validate_test.c
> +++ b/drivers/gpu/drm/ttm/tests/ttm_bo_validate_test.c
> @@ -651,7 +651,8 @@ static void ttm_bo_validate_move_fence_signaled(struct kunit *test)
> int err;
>
> man = ttm_manager_type(priv->ttm_dev, mem_type);
> - man->move = dma_fence_get_stub();
> + man->pipelined_eviction.n_fences = 1;
> + man->pipelined_eviction.fences[0] = dma_fence_get_stub();
>
> bo = ttm_bo_kunit_init(test, test->priv, size, NULL);
> bo->type = bo_type;
> @@ -668,7 +669,7 @@ static void ttm_bo_validate_move_fence_signaled(struct kunit *test)
> KUNIT_EXPECT_EQ(test, ctx.bytes_moved, size);
>
> ttm_bo_put(bo);
> - dma_fence_put(man->move);
> + dma_fence_put(man->pipelined_eviction.fences[0]);
> }
>
> static const struct ttm_bo_validate_test_case ttm_bo_validate_wait_cases[] = {
> @@ -732,9 +733,10 @@ static void ttm_bo_validate_move_fence_not_signaled(struct kunit *test)
>
> spin_lock_init(&fence_lock);
> man = ttm_manager_type(priv->ttm_dev, fst_mem);
> - man->move = alloc_mock_fence(test);
> + man->pipelined_eviction.n_fences = 1;
> + man->pipelined_eviction.fences[0] = alloc_mock_fence(test);
>
> - task = kthread_create(threaded_fence_signal, man->move, "move-fence-signal");
> + task = kthread_create(threaded_fence_signal, man->pipelined_eviction.fences[0], "move-fence-signal");
> if (IS_ERR(task))
> KUNIT_FAIL(test, "Couldn't create move fence signal task\n");
>
> @@ -742,7 +744,8 @@ static void ttm_bo_validate_move_fence_not_signaled(struct kunit *test)
> err = ttm_bo_validate(bo, placement_val, &ctx_val);
> dma_resv_unlock(bo->base.resv);
>
> - dma_fence_wait_timeout(man->move, false, MAX_SCHEDULE_TIMEOUT);
> + dma_fence_wait_timeout(man->pipelined_eviction.fences[0], false, MAX_SCHEDULE_TIMEOUT);
> + man->pipelined_eviction.fences[0] = NULL;
>
> KUNIT_EXPECT_EQ(test, err, 0);
> KUNIT_EXPECT_EQ(test, ctx_val.bytes_moved, size);
> diff --git a/drivers/gpu/drm/ttm/tests/ttm_resource_test.c b/drivers/gpu/drm/ttm/tests/ttm_resource_test.c
> index e6ea2bd01f07..6dfdf759a491 100644
> --- a/drivers/gpu/drm/ttm/tests/ttm_resource_test.c
> +++ b/drivers/gpu/drm/ttm/tests/ttm_resource_test.c
> @@ -207,6 +207,7 @@ static void ttm_resource_manager_init_basic(struct kunit *test)
> struct ttm_resource_test_priv *priv = test->priv;
> struct ttm_resource_manager *man;
> size_t size = SZ_16K;
> + int i;
>
> man = kunit_kzalloc(test, sizeof(*man), GFP_KERNEL);
> KUNIT_ASSERT_NOT_NULL(test, man);
> @@ -216,8 +217,8 @@ static void ttm_resource_manager_init_basic(struct kunit *test)
> KUNIT_ASSERT_PTR_EQ(test, man->bdev, priv->devs->ttm_dev);
> KUNIT_ASSERT_EQ(test, man->size, size);
> KUNIT_ASSERT_EQ(test, man->usage, 0);
> - KUNIT_ASSERT_NULL(test, man->move);
> - KUNIT_ASSERT_NOT_NULL(test, &man->move_lock);
> + for (i = 0; i < TTM_FENCES_MAX_SLOT_COUNT; i++)
> + KUNIT_ASSERT_NULL(test, man->pipelined_eviction.fences[i]);
>
> for (int i = 0; i < TTM_MAX_BO_PRIORITY; ++i)
> KUNIT_ASSERT_TRUE(test, list_empty(&man->lru[i]));
> diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c
> index f4d9e68b21e7..bc6d4a6c6d70 100644
> --- a/drivers/gpu/drm/ttm/ttm_bo.c
> +++ b/drivers/gpu/drm/ttm/ttm_bo.c
> @@ -658,34 +658,48 @@ void ttm_bo_unpin(struct ttm_buffer_object *bo)
> EXPORT_SYMBOL(ttm_bo_unpin);
>
> /*
> - * Add the last move fence to the BO as kernel dependency and reserve a new
> - * fence slot.
> + * Add the pipelined eviction fencesto the BO as kernel dependency and reserve new
> + * fence slots.
> */
> -static int ttm_bo_add_move_fence(struct ttm_buffer_object *bo,
> - struct ttm_resource_manager *man,
> - bool no_wait_gpu)
> +static int ttm_bo_add_pipelined_eviction_fences(struct ttm_buffer_object *bo,
> + struct ttm_resource_manager *man,
> + bool no_wait_gpu)
> {
> + struct dma_fence *fences_to_add[TTM_FENCES_MAX_SLOT_COUNT] = {};
> struct dma_fence *fence;
> - int ret;
> + bool all_signaled = true, signaled;
> + int i, n = 0;
>
> - spin_lock(&man->move_lock);
> - fence = dma_fence_get(man->move);
> - spin_unlock(&man->move_lock);
> + spin_lock(&man->pipelined_eviction.lock);
> + for (i = 0; i < man->pipelined_eviction.n_fences; i++) {
> + fence = man->pipelined_eviction.fences[i];
> + if (!fence)
> + continue;
> + signaled = dma_fence_is_signaled(fence);
>
> - if (!fence)
> + if (signaled) {
> + dma_fence_put(man->pipelined_eviction.fences[i]);
> + man->pipelined_eviction.fences[i] = NULL;
Please completely drop that, only check if the fences are signaled when the no_wait_gpu flag is set.
> + } else {
> + all_signaled = false;
> + if (no_wait_gpu) {
> + spin_unlock(&man->pipelined_eviction.lock);
> + return -EBUSY;
> + }
> + fences_to_add[n++] = dma_fence_get(fence);
> + }
> + }
> + spin_unlock(&man->pipelined_eviction.lock);
> +
> + if (all_signaled)
> return 0;
>
> - if (no_wait_gpu) {
> - ret = dma_fence_is_signaled(fence) ? 0 : -EBUSY;
> - dma_fence_put(fence);
> - return ret;
> + for (i = 0; i < n; i++) {
> + dma_resv_add_fence(bo->base.resv, fences_to_add[i], DMA_RESV_USAGE_KERNEL);
> + dma_fence_put(fences_to_add[i]);
> }
>
> - dma_resv_add_fence(bo->base.resv, fence, DMA_RESV_USAGE_KERNEL);
> -
> - ret = dma_resv_reserve_fences(bo->base.resv, 1);
> - dma_fence_put(fence);
> - return ret;
> + return dma_resv_reserve_fences(bo->base.resv, TTM_FENCES_MAX_SLOT_COUNT);
Please separate out a patch where the call to dma_resv_reserve_fences() is removed here.
> }
>
> /**
> @@ -718,7 +732,7 @@ static int ttm_bo_alloc_resource(struct ttm_buffer_object *bo,
> int i, ret;
>
> ticket = dma_resv_locking_ctx(bo->base.resv);
> - ret = dma_resv_reserve_fences(bo->base.resv, 1);
> + ret = dma_resv_reserve_fences(bo->base.resv, TTM_FENCES_MAX_SLOT_COUNT);
> if (unlikely(ret))
> return ret;
>
> @@ -757,7 +771,7 @@ static int ttm_bo_alloc_resource(struct ttm_buffer_object *bo,
> return ret;
> }
>
> - ret = ttm_bo_add_move_fence(bo, man, ctx->no_wait_gpu);
> + ret = ttm_bo_add_pipelined_eviction_fences(bo, man, ctx->no_wait_gpu);
> if (unlikely(ret)) {
> ttm_resource_free(bo, res);
> if (ret == -EBUSY)
> diff --git a/drivers/gpu/drm/ttm/ttm_bo_util.c b/drivers/gpu/drm/ttm/ttm_bo_util.c
> index acbbca9d5c92..ada8af965acf 100644
> --- a/drivers/gpu/drm/ttm/ttm_bo_util.c
> +++ b/drivers/gpu/drm/ttm/ttm_bo_util.c
> @@ -258,7 +258,7 @@ static int ttm_buffer_object_transfer(struct ttm_buffer_object *bo,
> ret = dma_resv_trylock(&fbo->base.base._resv);
> WARN_ON(!ret);
>
> - ret = dma_resv_reserve_fences(&fbo->base.base._resv, 1);
> + ret = dma_resv_reserve_fences(&fbo->base.base._resv, TTM_FENCES_MAX_SLOT_COUNT);
> if (ret) {
> dma_resv_unlock(&fbo->base.base._resv);
> kfree(fbo);
> @@ -646,6 +646,8 @@ static void ttm_bo_move_pipeline_evict(struct ttm_buffer_object *bo,
> {
> struct ttm_device *bdev = bo->bdev;
> struct ttm_resource_manager *from;
> + struct dma_fence *tmp;
> + int i, free_slot = -1;
>
> from = ttm_manager_type(bdev, bo->resource->mem_type);
>
> @@ -653,13 +655,35 @@ static void ttm_bo_move_pipeline_evict(struct ttm_buffer_object *bo,
> * BO doesn't have a TTM we need to bind/unbind. Just remember
> * this eviction and free up the allocation
> */
> - spin_lock(&from->move_lock);
> - if (!from->move || dma_fence_is_later(fence, from->move)) {
> - dma_fence_put(from->move);
> - from->move = dma_fence_get(fence);
> + spin_lock(&from->pipelined_eviction.lock);
> + for (i = 0; i < from->pipelined_eviction.n_fences; i++) {
> + tmp = from->pipelined_eviction.fences[i];
> + if (!tmp) {
> + if (free_slot < 0)
> + free_slot = i;
> + continue;
Just break here.
> + }
> + if (fence->context != tmp->context)
> + continue;
> + if (dma_fence_is_later(fence, tmp)) {
> + dma_fence_put(tmp);
> + free_slot = i;
> + break;
> + }
> + goto unlock;
> + }
> + if (free_slot >= 0) {
Drop free_slot and check i here.
> + from->pipelined_eviction.fences[free_slot] = dma_fence_get(fence);
> + } else {
> + WARN(1, "not enough fence slots for all fence contexts");
> + spin_unlock(&from->pipelined_eviction.lock);
> + dma_fence_wait(fence, false);
> + goto end;
> }
> - spin_unlock(&from->move_lock);
>
> +unlock:
> + spin_unlock(&from->pipelined_eviction.lock);
> +end:
> ttm_resource_free(bo, &bo->resource);
> }
>
> diff --git a/drivers/gpu/drm/ttm/ttm_resource.c b/drivers/gpu/drm/ttm/ttm_resource.c
> index e2c82ad07eb4..ae0d4621cc55 100644
> --- a/drivers/gpu/drm/ttm/ttm_resource.c
> +++ b/drivers/gpu/drm/ttm/ttm_resource.c
> @@ -523,14 +523,19 @@ void ttm_resource_manager_init(struct ttm_resource_manager *man,
> {
> unsigned i;
>
> - spin_lock_init(&man->move_lock);
> man->bdev = bdev;
> man->size = size;
> man->usage = 0;
>
> for (i = 0; i < TTM_MAX_BO_PRIORITY; ++i)
> INIT_LIST_HEAD(&man->lru[i]);
> - man->move = NULL;
> + spin_lock_init(&man->pipelined_eviction.lock);
> + for (i = 0; i < TTM_FENCES_MAX_SLOT_COUNT; i++)
> + man->pipelined_eviction.fences[i] = NULL;
> + /* Can be overridden by drivers that wants to use more than 1 entity
> + * for moves and evictions (limited to TTM_FENCES_MAX_SLOT_COUNT).
> + */
> + man->pipelined_eviction.n_fences = 1;
> }
> EXPORT_SYMBOL(ttm_resource_manager_init);
>
> @@ -551,7 +556,7 @@ int ttm_resource_manager_evict_all(struct ttm_device *bdev,
> .no_wait_gpu = false,
> };
> struct dma_fence *fence;
> - int ret;
> + int ret, i;
>
> do {
> ret = ttm_bo_evict_first(bdev, man, &ctx);
> @@ -561,18 +566,32 @@ int ttm_resource_manager_evict_all(struct ttm_device *bdev,
> if (ret && ret != -ENOENT)
> return ret;
>
> - spin_lock(&man->move_lock);
> - fence = dma_fence_get(man->move);
> - spin_unlock(&man->move_lock);
> + ret = 0;
>
> - if (fence) {
> - ret = dma_fence_wait(fence, false);
> - dma_fence_put(fence);
> - if (ret)
> - return ret;
> - }
> + do {
> + fence = NULL;
>
> - return 0;
> + spin_lock(&man->pipelined_eviction.lock);
> + for (i = 0; i < man->pipelined_eviction.n_fences; i++) {
> + fence = man->pipelined_eviction.fences[i];
> + man->pipelined_eviction.fences[i] = NULL;
Drop that. We should never set man->pipelined_eviction.fences to NULL.
Potentially even initialize all move fences with a stub fence.
> + if (fence)
> + break;
> + }
> + spin_unlock(&man->pipelined_eviction.lock);
> +
> + if (fence) {
> + ret = dma_fence_wait(fence, false);
> + dma_fence_put(fence);
> +
> + if (ret)
> + break;
> + } else {
> + break;
> + }
> + } while (1);
> +
> + return ret;
> }
> EXPORT_SYMBOL(ttm_resource_manager_evict_all);
>
> diff --git a/include/drm/ttm/ttm_resource.h b/include/drm/ttm/ttm_resource.h
> index f49daa504c36..898c429b37ad 100644
> --- a/include/drm/ttm/ttm_resource.h
> +++ b/include/drm/ttm/ttm_resource.h
> @@ -50,6 +50,15 @@ struct io_mapping;
> struct sg_table;
> struct scatterlist;
>
> +/**
> + * define TTM_FENCES_MAX_SLOT_COUNT - How many entities can be used for evictions
> + *
> + * Pipelined evictions can be spread on multiple entities. This
> + * is the max number of entities that can be used by the driver
> + * for that purpose.
> + */
> +#define TTM_FENCES_MAX_SLOT_COUNT 8
Make that TTM_NUM_MOVE_FENCES.
> +
> /**
> * enum ttm_lru_item_type - enumerate ttm_lru_item subclasses
> */
> @@ -180,8 +189,10 @@ struct ttm_resource_manager_func {
> * @size: Size of the managed region.
> * @bdev: ttm device this manager belongs to
> * @func: structure pointer implementing the range manager. See above
> - * @move_lock: lock for move fence
> - * @move: The fence of the last pipelined move operation.
> + * @pipelined_eviction.lock: lock for eviction fences
> + * @pipelined_eviction.n_fences: The number of fences allowed in the array. If
> + * 0, pipelined evictions aren't used.
> + * @pipelined_eviction.fences: The fences of the last pipelined move operation.
> * @lru: The lru list for this memory type.
> *
> * This structure is used to identify and manage memory types for a device.
> @@ -195,12 +206,15 @@ struct ttm_resource_manager {
> struct ttm_device *bdev;
> uint64_t size;
> const struct ttm_resource_manager_func *func;
> - spinlock_t move_lock;
>
> - /*
> - * Protected by @move_lock.
> + /* This is very similar to a dma_resv object, but locking rules make
> + * it difficult to use a it in this context.
> */
> - struct dma_fence *move;
> + struct {
> + spinlock_t lock;
> + int n_fences;
> + struct dma_fence *fences[TTM_FENCES_MAX_SLOT_COUNT];
> + } pipelined_eviction;
Drop the separate structure, just make move an array instead.
And also drop n_fences. Just always take a look at all fences.
Regards,
Christian.
>
> /*
> * Protected by the bdev->lru_lock.
> @@ -421,8 +435,12 @@ static inline bool ttm_resource_manager_used(struct ttm_resource_manager *man)
> static inline void
> ttm_resource_manager_cleanup(struct ttm_resource_manager *man)
> {
> - dma_fence_put(man->move);
> - man->move = NULL;
> + int i;
> +
> + for (i = 0; i < TTM_FENCES_MAX_SLOT_COUNT; i++) {
> + dma_fence_put(man->pipelined_eviction.fences[i]);
> + man->pipelined_eviction.fences[i] = NULL;
> + }
> }
>
> void ttm_lru_bulk_move_init(struct ttm_lru_bulk_move *bulk);
^ permalink raw reply [flat|nested] 40+ messages in thread* Re: [PATCH v1 02/20] drm/ttm: rework pipelined eviction fence handling
2025-11-04 14:12 ` Christian König
@ 2025-11-05 10:34 ` Pierre-Eric Pelloux-Prayer
2025-11-05 13:00 ` Christian König
0 siblings, 1 reply; 40+ messages in thread
From: Pierre-Eric Pelloux-Prayer @ 2025-11-05 10:34 UTC (permalink / raw)
To: Christian König, Pierre-Eric Pelloux-Prayer, Alex Deucher,
David Airlie, Simona Vetter, Huang Rui, Matthew Auld,
Matthew Brost, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, Sumit Semwal
Cc: amd-gfx, dri-devel, linux-kernel, linux-media, linaro-mm-sig
Le 04/11/2025 à 15:12, Christian König a écrit :
> On 11/4/25 09:35, Pierre-Eric Pelloux-Prayer wrote:
>> Until now ttm stored a single pipelined eviction fence which means
>> drivers had to use a single entity for these evictions.
>>
>> To lift this requirement, this commit allows up to 8 entities to
>> be used.
>>
>> Ideally a dma_resv object would have been used as a container of
>> the eviction fences, but the locking rules makes it complex.
>> dma_resv all have the same ww_class, which means "Attempting to
>> lock more mutexes after ww_acquire_done." is an error.
>>
>> One alternative considered was to introduced a 2nd ww_class for
>> specific resv to hold a single "transient" lock (= the resv lock
>> would only be held for a short period, without taking any other
>> locks).
>>
>> The other option, is to statically reserve a fence array, and
>> extend the existing code to deal with N fences, instead of 1.
>>
>> The driver is still responsible to reserve the correct number
>> of fence slots.
>>
>> Lastly ttm_resource_manager.pipelined_eviction.n_fences is
>> initialized to 1, so the new behavior is opt-in.
>>
>> Signed-off-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
>> ---
>> drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 8 ++-
>> .../gpu/drm/ttm/tests/ttm_bo_validate_test.c | 13 +++--
>> drivers/gpu/drm/ttm/tests/ttm_resource_test.c | 5 +-
>> drivers/gpu/drm/ttm/ttm_bo.c | 56 ++++++++++++-------
>> drivers/gpu/drm/ttm/ttm_bo_util.c | 36 ++++++++++--
>> drivers/gpu/drm/ttm/ttm_resource.c | 45 ++++++++++-----
>> include/drm/ttm/ttm_resource.h | 34 ++++++++---
>> 7 files changed, 139 insertions(+), 58 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
>> index 326476089db3..c66f00434991 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
>> @@ -2156,7 +2156,7 @@ void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable)
>> {
>> struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM);
>> uint64_t size;
>> - int r;
>> + int r, i;
>>
>> if (!adev->mman.initialized || amdgpu_in_reset(adev) ||
>> adev->mman.buffer_funcs_enabled == enable || adev->gmc.is_app_apu)
>> @@ -2190,8 +2190,10 @@ void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable)
>> } else {
>> drm_sched_entity_destroy(&adev->mman.high_pr);
>> drm_sched_entity_destroy(&adev->mman.low_pr);
>> - dma_fence_put(man->move);
>> - man->move = NULL;
>> + for (i = 0; i < TTM_FENCES_MAX_SLOT_COUNT; i++) {
>> + dma_fence_put(man->pipelined_eviction.fences[i]);
>> + man->pipelined_eviction.fences[i] = NULL;
>> + }
>> }
>>
>> /* this just adjusts TTM size idea, which sets lpfn to the correct value */
>> diff --git a/drivers/gpu/drm/ttm/tests/ttm_bo_validate_test.c b/drivers/gpu/drm/ttm/tests/ttm_bo_validate_test.c
>> index 3148f5d3dbd6..1396674e1923 100644
>> --- a/drivers/gpu/drm/ttm/tests/ttm_bo_validate_test.c
>> +++ b/drivers/gpu/drm/ttm/tests/ttm_bo_validate_test.c
>> @@ -651,7 +651,8 @@ static void ttm_bo_validate_move_fence_signaled(struct kunit *test)
>> int err;
>>
>> man = ttm_manager_type(priv->ttm_dev, mem_type);
>> - man->move = dma_fence_get_stub();
>> + man->pipelined_eviction.n_fences = 1;
>> + man->pipelined_eviction.fences[0] = dma_fence_get_stub();
>>
>> bo = ttm_bo_kunit_init(test, test->priv, size, NULL);
>> bo->type = bo_type;
>> @@ -668,7 +669,7 @@ static void ttm_bo_validate_move_fence_signaled(struct kunit *test)
>> KUNIT_EXPECT_EQ(test, ctx.bytes_moved, size);
>>
>> ttm_bo_put(bo);
>> - dma_fence_put(man->move);
>> + dma_fence_put(man->pipelined_eviction.fences[0]);
>> }
>>
>> static const struct ttm_bo_validate_test_case ttm_bo_validate_wait_cases[] = {
>> @@ -732,9 +733,10 @@ static void ttm_bo_validate_move_fence_not_signaled(struct kunit *test)
>>
>> spin_lock_init(&fence_lock);
>> man = ttm_manager_type(priv->ttm_dev, fst_mem);
>> - man->move = alloc_mock_fence(test);
>> + man->pipelined_eviction.n_fences = 1;
>> + man->pipelined_eviction.fences[0] = alloc_mock_fence(test);
>>
>> - task = kthread_create(threaded_fence_signal, man->move, "move-fence-signal");
>> + task = kthread_create(threaded_fence_signal, man->pipelined_eviction.fences[0], "move-fence-signal");
>> if (IS_ERR(task))
>> KUNIT_FAIL(test, "Couldn't create move fence signal task\n");
>>
>> @@ -742,7 +744,8 @@ static void ttm_bo_validate_move_fence_not_signaled(struct kunit *test)
>> err = ttm_bo_validate(bo, placement_val, &ctx_val);
>> dma_resv_unlock(bo->base.resv);
>>
>> - dma_fence_wait_timeout(man->move, false, MAX_SCHEDULE_TIMEOUT);
>> + dma_fence_wait_timeout(man->pipelined_eviction.fences[0], false, MAX_SCHEDULE_TIMEOUT);
>> + man->pipelined_eviction.fences[0] = NULL;
>>
>> KUNIT_EXPECT_EQ(test, err, 0);
>> KUNIT_EXPECT_EQ(test, ctx_val.bytes_moved, size);
>> diff --git a/drivers/gpu/drm/ttm/tests/ttm_resource_test.c b/drivers/gpu/drm/ttm/tests/ttm_resource_test.c
>> index e6ea2bd01f07..6dfdf759a491 100644
>> --- a/drivers/gpu/drm/ttm/tests/ttm_resource_test.c
>> +++ b/drivers/gpu/drm/ttm/tests/ttm_resource_test.c
>> @@ -207,6 +207,7 @@ static void ttm_resource_manager_init_basic(struct kunit *test)
>> struct ttm_resource_test_priv *priv = test->priv;
>> struct ttm_resource_manager *man;
>> size_t size = SZ_16K;
>> + int i;
>>
>> man = kunit_kzalloc(test, sizeof(*man), GFP_KERNEL);
>> KUNIT_ASSERT_NOT_NULL(test, man);
>> @@ -216,8 +217,8 @@ static void ttm_resource_manager_init_basic(struct kunit *test)
>> KUNIT_ASSERT_PTR_EQ(test, man->bdev, priv->devs->ttm_dev);
>> KUNIT_ASSERT_EQ(test, man->size, size);
>> KUNIT_ASSERT_EQ(test, man->usage, 0);
>> - KUNIT_ASSERT_NULL(test, man->move);
>> - KUNIT_ASSERT_NOT_NULL(test, &man->move_lock);
>> + for (i = 0; i < TTM_FENCES_MAX_SLOT_COUNT; i++)
>> + KUNIT_ASSERT_NULL(test, man->pipelined_eviction.fences[i]);
>>
>> for (int i = 0; i < TTM_MAX_BO_PRIORITY; ++i)
>> KUNIT_ASSERT_TRUE(test, list_empty(&man->lru[i]));
>> diff --git a/drivers/gpu/drm/ttm/ttm_bo.c b/drivers/gpu/drm/ttm/ttm_bo.c
>> index f4d9e68b21e7..bc6d4a6c6d70 100644
>> --- a/drivers/gpu/drm/ttm/ttm_bo.c
>> +++ b/drivers/gpu/drm/ttm/ttm_bo.c
>> @@ -658,34 +658,48 @@ void ttm_bo_unpin(struct ttm_buffer_object *bo)
>> EXPORT_SYMBOL(ttm_bo_unpin);
>>
>> /*
>> - * Add the last move fence to the BO as kernel dependency and reserve a new
>> - * fence slot.
>> + * Add the pipelined eviction fencesto the BO as kernel dependency and reserve new
>> + * fence slots.
>> */
>> -static int ttm_bo_add_move_fence(struct ttm_buffer_object *bo,
>> - struct ttm_resource_manager *man,
>> - bool no_wait_gpu)
>> +static int ttm_bo_add_pipelined_eviction_fences(struct ttm_buffer_object *bo,
>> + struct ttm_resource_manager *man,
>> + bool no_wait_gpu)
>> {
>> + struct dma_fence *fences_to_add[TTM_FENCES_MAX_SLOT_COUNT] = {};
>> struct dma_fence *fence;
>> - int ret;
>> + bool all_signaled = true, signaled;
>> + int i, n = 0;
>>
>> - spin_lock(&man->move_lock);
>> - fence = dma_fence_get(man->move);
>> - spin_unlock(&man->move_lock);
>> + spin_lock(&man->pipelined_eviction.lock);
>> + for (i = 0; i < man->pipelined_eviction.n_fences; i++) {
>> + fence = man->pipelined_eviction.fences[i];
>
>> + if (!fence)
>> + continue;
>> + signaled = dma_fence_is_signaled(fence);
>>
>> - if (!fence)
>> + if (signaled) {
>> + dma_fence_put(man->pipelined_eviction.fences[i]);
>> + man->pipelined_eviction.fences[i] = NULL;
>
> Please completely drop that, only check if the fences are signaled when the no_wait_gpu flag is set.
ok.
>
>> + } else {
>> + all_signaled = false;
>> + if (no_wait_gpu) {
>> + spin_unlock(&man->pipelined_eviction.lock);
>> + return -EBUSY;
>> + }
>> + fences_to_add[n++] = dma_fence_get(fence);
>> + }
>> + }
>> + spin_unlock(&man->pipelined_eviction.lock);
>> +
>> + if (all_signaled)
>> return 0;
>>
>> - if (no_wait_gpu) {
>> - ret = dma_fence_is_signaled(fence) ? 0 : -EBUSY;
>> - dma_fence_put(fence);
>> - return ret;
>> + for (i = 0; i < n; i++) {
>> + dma_resv_add_fence(bo->base.resv, fences_to_add[i], DMA_RESV_USAGE_KERNEL);
>> + dma_fence_put(fences_to_add[i]);
>> }
>>
>> - dma_resv_add_fence(bo->base.resv, fence, DMA_RESV_USAGE_KERNEL);
>> -
>> - ret = dma_resv_reserve_fences(bo->base.resv, 1);
>> - dma_fence_put(fence);
>> - return ret;
>> + return dma_resv_reserve_fences(bo->base.resv, TTM_FENCES_MAX_SLOT_COUNT);
>
> Please separate out a patch where the call to dma_resv_reserve_fences() is removed here.
Can you remind me why it's not needed?
>
>> }
>>
>> /**
>> @@ -718,7 +732,7 @@ static int ttm_bo_alloc_resource(struct ttm_buffer_object *bo,
>> int i, ret;
>>
>> ticket = dma_resv_locking_ctx(bo->base.resv);
>> - ret = dma_resv_reserve_fences(bo->base.resv, 1);
>> + ret = dma_resv_reserve_fences(bo->base.resv, TTM_FENCES_MAX_SLOT_COUNT);
>> if (unlikely(ret))
>> return ret;
>>
>> @@ -757,7 +771,7 @@ static int ttm_bo_alloc_resource(struct ttm_buffer_object *bo,
>> return ret;
>> }
>>
>> - ret = ttm_bo_add_move_fence(bo, man, ctx->no_wait_gpu);
>> + ret = ttm_bo_add_pipelined_eviction_fences(bo, man, ctx->no_wait_gpu);
>> if (unlikely(ret)) {
>> ttm_resource_free(bo, res);
>> if (ret == -EBUSY)
>> diff --git a/drivers/gpu/drm/ttm/ttm_bo_util.c b/drivers/gpu/drm/ttm/ttm_bo_util.c
>> index acbbca9d5c92..ada8af965acf 100644
>> --- a/drivers/gpu/drm/ttm/ttm_bo_util.c
>> +++ b/drivers/gpu/drm/ttm/ttm_bo_util.c
>> @@ -258,7 +258,7 @@ static int ttm_buffer_object_transfer(struct ttm_buffer_object *bo,
>> ret = dma_resv_trylock(&fbo->base.base._resv);
>> WARN_ON(!ret);
>>
>> - ret = dma_resv_reserve_fences(&fbo->base.base._resv, 1);
>> + ret = dma_resv_reserve_fences(&fbo->base.base._resv, TTM_FENCES_MAX_SLOT_COUNT);
>> if (ret) {
>> dma_resv_unlock(&fbo->base.base._resv);
>> kfree(fbo);
>> @@ -646,6 +646,8 @@ static void ttm_bo_move_pipeline_evict(struct ttm_buffer_object *bo,
>> {
>> struct ttm_device *bdev = bo->bdev;
>> struct ttm_resource_manager *from;
>> + struct dma_fence *tmp;
>> + int i, free_slot = -1;
>>
>> from = ttm_manager_type(bdev, bo->resource->mem_type);
>>
>> @@ -653,13 +655,35 @@ static void ttm_bo_move_pipeline_evict(struct ttm_buffer_object *bo,
>> * BO doesn't have a TTM we need to bind/unbind. Just remember
>> * this eviction and free up the allocation
>> */
>> - spin_lock(&from->move_lock);
>> - if (!from->move || dma_fence_is_later(fence, from->move)) {
>> - dma_fence_put(from->move);
>> - from->move = dma_fence_get(fence);
>> + spin_lock(&from->pipelined_eviction.lock);
>> + for (i = 0; i < from->pipelined_eviction.n_fences; i++) {
>> + tmp = from->pipelined_eviction.fences[i];
>> + if (!tmp) {
>> + if (free_slot < 0)
>> + free_slot = i;
>> + continue;
>
> Just break here.
The logic here is to reuse context slots. Even if slot 0 is empty, I need to use
slot 1 if slot 1's context is the same as fence->context.
This way, we're guaranteed to find a slot for all contexts used by the driver.
>
>> + }
>> + if (fence->context != tmp->context)
>> + continue;
>> + if (dma_fence_is_later(fence, tmp)) {
>> + dma_fence_put(tmp);
>> + free_slot = i;
>> + break;
>> + }
>> + goto unlock;
>> + }
>> + if (free_slot >= 0) {
>
> Drop free_slot and check i here.
>
>> + from->pipelined_eviction.fences[free_slot] = dma_fence_get(fence);
>> + } else {
>> + WARN(1, "not enough fence slots for all fence contexts");
>> + spin_unlock(&from->pipelined_eviction.lock);
>> + dma_fence_wait(fence, false);
>> + goto end;
>> }
>> - spin_unlock(&from->move_lock);
>>
>> +unlock:
>> + spin_unlock(&from->pipelined_eviction.lock);
>> +end:
>> ttm_resource_free(bo, &bo->resource);
>> }
>>
>> diff --git a/drivers/gpu/drm/ttm/ttm_resource.c b/drivers/gpu/drm/ttm/ttm_resource.c
>> index e2c82ad07eb4..ae0d4621cc55 100644
>> --- a/drivers/gpu/drm/ttm/ttm_resource.c
>> +++ b/drivers/gpu/drm/ttm/ttm_resource.c
>> @@ -523,14 +523,19 @@ void ttm_resource_manager_init(struct ttm_resource_manager *man,
>> {
>> unsigned i;
>>
>> - spin_lock_init(&man->move_lock);
>> man->bdev = bdev;
>> man->size = size;
>> man->usage = 0;
>>
>> for (i = 0; i < TTM_MAX_BO_PRIORITY; ++i)
>> INIT_LIST_HEAD(&man->lru[i]);
>> - man->move = NULL;
>> + spin_lock_init(&man->pipelined_eviction.lock);
>> + for (i = 0; i < TTM_FENCES_MAX_SLOT_COUNT; i++)
>> + man->pipelined_eviction.fences[i] = NULL;
>> + /* Can be overridden by drivers that wants to use more than 1 entity
>> + * for moves and evictions (limited to TTM_FENCES_MAX_SLOT_COUNT).
>> + */
>> + man->pipelined_eviction.n_fences = 1;
>> }
>> EXPORT_SYMBOL(ttm_resource_manager_init);
>>
>> @@ -551,7 +556,7 @@ int ttm_resource_manager_evict_all(struct ttm_device *bdev,
>> .no_wait_gpu = false,
>> };
>> struct dma_fence *fence;
>> - int ret;
>> + int ret, i;
>>
>> do {
>> ret = ttm_bo_evict_first(bdev, man, &ctx);
>> @@ -561,18 +566,32 @@ int ttm_resource_manager_evict_all(struct ttm_device *bdev,
>> if (ret && ret != -ENOENT)
>> return ret;
>>
>> - spin_lock(&man->move_lock);
>> - fence = dma_fence_get(man->move);
>> - spin_unlock(&man->move_lock);
>> + ret = 0;
>>
>> - if (fence) {
>> - ret = dma_fence_wait(fence, false);
>> - dma_fence_put(fence);
>> - if (ret)
>> - return ret;
>> - }
>> + do {
>> + fence = NULL;
>>
>> - return 0;
>> + spin_lock(&man->pipelined_eviction.lock);
>> + for (i = 0; i < man->pipelined_eviction.n_fences; i++) {
>> + fence = man->pipelined_eviction.fences[i];
>
>> + man->pipelined_eviction.fences[i] = NULL;
>
> Drop that. We should never set man->pipelined_eviction.fences to NULL.
Why?
>
> Potentially even initialize all move fences with a stub fence.
>
>> + if (fence)
>> + break;
>> + }
>> + spin_unlock(&man->pipelined_eviction.lock);
>> +
>> + if (fence) {
>> + ret = dma_fence_wait(fence, false);
>> + dma_fence_put(fence);
>> +
>> + if (ret)
>> + break;
>> + } else {
>> + break;
>> + }
>> + } while (1);
>> +
>> + return ret;
>> }
>> EXPORT_SYMBOL(ttm_resource_manager_evict_all);
>>
>> diff --git a/include/drm/ttm/ttm_resource.h b/include/drm/ttm/ttm_resource.h
>> index f49daa504c36..898c429b37ad 100644
>> --- a/include/drm/ttm/ttm_resource.h
>> +++ b/include/drm/ttm/ttm_resource.h
>> @@ -50,6 +50,15 @@ struct io_mapping;
>> struct sg_table;
>> struct scatterlist;
>>
>> +/**
>> + * define TTM_FENCES_MAX_SLOT_COUNT - How many entities can be used for evictions
>> + *
>> + * Pipelined evictions can be spread on multiple entities. This
>> + * is the max number of entities that can be used by the driver
>> + * for that purpose.
>> + */
>> +#define TTM_FENCES_MAX_SLOT_COUNT 8
>
> Make that TTM_NUM_MOVE_FENCES.
Ok.
>
>> +
>> /**
>> * enum ttm_lru_item_type - enumerate ttm_lru_item subclasses
>> */
>> @@ -180,8 +189,10 @@ struct ttm_resource_manager_func {
>> * @size: Size of the managed region.
>> * @bdev: ttm device this manager belongs to
>> * @func: structure pointer implementing the range manager. See above
>> - * @move_lock: lock for move fence
>> - * @move: The fence of the last pipelined move operation.
>> + * @pipelined_eviction.lock: lock for eviction fences
>> + * @pipelined_eviction.n_fences: The number of fences allowed in the array. If
>> + * 0, pipelined evictions aren't used.
>> + * @pipelined_eviction.fences: The fences of the last pipelined move operation.
>> * @lru: The lru list for this memory type.
>> *
>> * This structure is used to identify and manage memory types for a device.
>> @@ -195,12 +206,15 @@ struct ttm_resource_manager {
>> struct ttm_device *bdev;
>> uint64_t size;
>> const struct ttm_resource_manager_func *func;
>> - spinlock_t move_lock;
>>
>> - /*
>> - * Protected by @move_lock.
>> + /* This is very similar to a dma_resv object, but locking rules make
>> + * it difficult to use a it in this context.
>> */
>> - struct dma_fence *move;
>> + struct {
>> + spinlock_t lock;
>> + int n_fences;
>> + struct dma_fence *fences[TTM_FENCES_MAX_SLOT_COUNT];
>> + } pipelined_eviction;
>
> Drop the separate structure, just make move an array instead.
IMO pipelined_eviction.fences and pipelined_eviction.lock is clearer when
reading the code than moves and move_lock but if you prefer I'll switch back to
the old names.
>
> And also drop n_fences. Just always take a look at all fences.
OK.
Thanks,
Pierre-Eric
>
> Regards,
> Christian.
>
>>
>> /*
>> * Protected by the bdev->lru_lock.
>> @@ -421,8 +435,12 @@ static inline bool ttm_resource_manager_used(struct ttm_resource_manager *man)
>> static inline void
>> ttm_resource_manager_cleanup(struct ttm_resource_manager *man)
>> {
>> - dma_fence_put(man->move);
>> - man->move = NULL;
>> + int i;
>> +
>> + for (i = 0; i < TTM_FENCES_MAX_SLOT_COUNT; i++) {
>> + dma_fence_put(man->pipelined_eviction.fences[i]);
>> + man->pipelined_eviction.fences[i] = NULL;
>> + }
>> }
>>
>> void ttm_lru_bulk_move_init(struct ttm_lru_bulk_move *bulk);
^ permalink raw reply [flat|nested] 40+ messages in thread* Re: [PATCH v1 02/20] drm/ttm: rework pipelined eviction fence handling
2025-11-05 10:34 ` Pierre-Eric Pelloux-Prayer
@ 2025-11-05 13:00 ` Christian König
0 siblings, 0 replies; 40+ messages in thread
From: Christian König @ 2025-11-05 13:00 UTC (permalink / raw)
To: Pierre-Eric Pelloux-Prayer, Pierre-Eric Pelloux-Prayer,
Alex Deucher, David Airlie, Simona Vetter, Huang Rui,
Matthew Auld, Matthew Brost, Maarten Lankhorst, Maxime Ripard,
Thomas Zimmermann, Sumit Semwal
Cc: amd-gfx, dri-devel, linux-kernel, linux-media, linaro-mm-sig
On 11/5/25 11:34, Pierre-Eric Pelloux-Prayer wrote:
>>
>>> + } else {
>>> + all_signaled = false;
>>> + if (no_wait_gpu) {
>>> + spin_unlock(&man->pipelined_eviction.lock);
>>> + return -EBUSY;
>>> + }
>>> + fences_to_add[n++] = dma_fence_get(fence);
>>> + }
>>> + }
>>> + spin_unlock(&man->pipelined_eviction.lock);
>>> +
>>> + if (all_signaled)
>>> return 0;
>>> - if (no_wait_gpu) {
>>> - ret = dma_fence_is_signaled(fence) ? 0 : -EBUSY;
>>> - dma_fence_put(fence);
>>> - return ret;
>>> + for (i = 0; i < n; i++) {
>>> + dma_resv_add_fence(bo->base.resv, fences_to_add[i], DMA_RESV_USAGE_KERNEL);
>>> + dma_fence_put(fences_to_add[i]);
>>> }
>>> - dma_resv_add_fence(bo->base.resv, fence, DMA_RESV_USAGE_KERNEL);
>>> -
>>> - ret = dma_resv_reserve_fences(bo->base.resv, 1);
>>> - dma_fence_put(fence);
>>> - return ret;
>>> + return dma_resv_reserve_fences(bo->base.resv, TTM_FENCES_MAX_SLOT_COUNT);
>>
>> Please separate out a patch where the call to dma_resv_reserve_fences() is removed here.
>
> Can you remind me why it's not needed?
Some years ago the dma_resv object had a fixed field for an exclusive fence.
When we removed that we sprinkled calls like "dma_resv_reserve_fences(bo->base.resv, 1)" all over the place where we previously used this exclusive fence slot to prevent things from going boom!
It could be that some old drivers like radeon or qxl still rely on that somewhere, but that would then clearly be a driver bug.
What we could do is to either leave it alone or remove it, but changing it to reserving TTM_FENCES_MAX_SLOT_COUNT is clearly not correct.
>>
>>> }
>>> /**
>>> @@ -718,7 +732,7 @@ static int ttm_bo_alloc_resource(struct ttm_buffer_object *bo,
>>> int i, ret;
>>> ticket = dma_resv_locking_ctx(bo->base.resv);
>>> - ret = dma_resv_reserve_fences(bo->base.resv, 1);
>>> + ret = dma_resv_reserve_fences(bo->base.resv, TTM_FENCES_MAX_SLOT_COUNT);
>>> if (unlikely(ret))
>>> return ret;
>>> @@ -757,7 +771,7 @@ static int ttm_bo_alloc_resource(struct ttm_buffer_object *bo,
>>> return ret;
>>> }
>>> - ret = ttm_bo_add_move_fence(bo, man, ctx->no_wait_gpu);
>>> + ret = ttm_bo_add_pipelined_eviction_fences(bo, man, ctx->no_wait_gpu);
>>> if (unlikely(ret)) {
>>> ttm_resource_free(bo, res);
>>> if (ret == -EBUSY)
>>> diff --git a/drivers/gpu/drm/ttm/ttm_bo_util.c b/drivers/gpu/drm/ttm/ttm_bo_util.c
>>> index acbbca9d5c92..ada8af965acf 100644
>>> --- a/drivers/gpu/drm/ttm/ttm_bo_util.c
>>> +++ b/drivers/gpu/drm/ttm/ttm_bo_util.c
>>> @@ -258,7 +258,7 @@ static int ttm_buffer_object_transfer(struct ttm_buffer_object *bo,
>>> ret = dma_resv_trylock(&fbo->base.base._resv);
>>> WARN_ON(!ret);
>>> - ret = dma_resv_reserve_fences(&fbo->base.base._resv, 1);
>>> + ret = dma_resv_reserve_fences(&fbo->base.base._resv, TTM_FENCES_MAX_SLOT_COUNT);
>>> if (ret) {
>>> dma_resv_unlock(&fbo->base.base._resv);
>>> kfree(fbo);
>>> @@ -646,6 +646,8 @@ static void ttm_bo_move_pipeline_evict(struct ttm_buffer_object *bo,
>>> {
>>> struct ttm_device *bdev = bo->bdev;
>>> struct ttm_resource_manager *from;
>>> + struct dma_fence *tmp;
>>> + int i, free_slot = -1;
>>> from = ttm_manager_type(bdev, bo->resource->mem_type);
>>> @@ -653,13 +655,35 @@ static void ttm_bo_move_pipeline_evict(struct ttm_buffer_object *bo,
>>> * BO doesn't have a TTM we need to bind/unbind. Just remember
>>> * this eviction and free up the allocation
>>> */
>>> - spin_lock(&from->move_lock);
>>> - if (!from->move || dma_fence_is_later(fence, from->move)) {
>>> - dma_fence_put(from->move);
>>> - from->move = dma_fence_get(fence);
>>> + spin_lock(&from->pipelined_eviction.lock);
>>> + for (i = 0; i < from->pipelined_eviction.n_fences; i++) {
>>> + tmp = from->pipelined_eviction.fences[i];
>>> + if (!tmp) {
>>> + if (free_slot < 0)
>>> + free_slot = i;
>>> + continue;
>>
>> Just break here.
>
> The logic here is to reuse context slots. Even if slot 0 is empty, I need to use slot 1 if slot 1's context is the same as fence->context.
Good point, but slot 0 should never be empty. See we fill the slots starting from 0 and then incrementing you either have NULL or a slot which doesn't match.
> This way, we're guaranteed to find a slot for all contexts used by the driver.
>
>>
>>> + }
>>> + if (fence->context != tmp->context)
>>> + continue;
>>> + if (dma_fence_is_later(fence, tmp)) {
>>> + dma_fence_put(tmp);
>>> + free_slot = i;
>>> + break;
>>> + }
>>> + goto unlock;
>>> + }
>>> + if (free_slot >= 0) {
>>
>> Drop free_slot and check i here.
>>
>>> + from->pipelined_eviction.fences[free_slot] = dma_fence_get(fence);
>>> + } else {
>>> + WARN(1, "not enough fence slots for all fence contexts");
>>> + spin_unlock(&from->pipelined_eviction.lock);
>>> + dma_fence_wait(fence, false);
>>> + goto end;
>>> }
>>> - spin_unlock(&from->move_lock);
>>> +unlock:
>>> + spin_unlock(&from->pipelined_eviction.lock);
>>> +end:
>>> ttm_resource_free(bo, &bo->resource);
>>> }
>>> diff --git a/drivers/gpu/drm/ttm/ttm_resource.c b/drivers/gpu/drm/ttm/ttm_resource.c
>>> index e2c82ad07eb4..ae0d4621cc55 100644
>>> --- a/drivers/gpu/drm/ttm/ttm_resource.c
>>> +++ b/drivers/gpu/drm/ttm/ttm_resource.c
>>> @@ -523,14 +523,19 @@ void ttm_resource_manager_init(struct ttm_resource_manager *man,
>>> {
>>> unsigned i;
>>> - spin_lock_init(&man->move_lock);
>>> man->bdev = bdev;
>>> man->size = size;
>>> man->usage = 0;
>>> for (i = 0; i < TTM_MAX_BO_PRIORITY; ++i)
>>> INIT_LIST_HEAD(&man->lru[i]);
>>> - man->move = NULL;
>>> + spin_lock_init(&man->pipelined_eviction.lock);
>>> + for (i = 0; i < TTM_FENCES_MAX_SLOT_COUNT; i++)
>>> + man->pipelined_eviction.fences[i] = NULL;
>>> + /* Can be overridden by drivers that wants to use more than 1 entity
>>> + * for moves and evictions (limited to TTM_FENCES_MAX_SLOT_COUNT).
>>> + */
>>> + man->pipelined_eviction.n_fences = 1;
>>> }
>>> EXPORT_SYMBOL(ttm_resource_manager_init);
>>> @@ -551,7 +556,7 @@ int ttm_resource_manager_evict_all(struct ttm_device *bdev,
>>> .no_wait_gpu = false,
>>> };
>>> struct dma_fence *fence;
>>> - int ret;
>>> + int ret, i;
>>> do {
>>> ret = ttm_bo_evict_first(bdev, man, &ctx);
>>> @@ -561,18 +566,32 @@ int ttm_resource_manager_evict_all(struct ttm_device *bdev,
>>> if (ret && ret != -ENOENT)
>>> return ret;
>>> - spin_lock(&man->move_lock);
>>> - fence = dma_fence_get(man->move);
>>> - spin_unlock(&man->move_lock);
>>> + ret = 0;
>>> - if (fence) {
>>> - ret = dma_fence_wait(fence, false);
>>> - dma_fence_put(fence);
>>> - if (ret)
>>> - return ret;
>>> - }
>>> + do {
>>> + fence = NULL;
>>> - return 0;
>>> + spin_lock(&man->pipelined_eviction.lock);
>>> + for (i = 0; i < man->pipelined_eviction.n_fences; i++) {
>>> + fence = man->pipelined_eviction.fences[i];
>>
>>> + man->pipelined_eviction.fences[i] = NULL;
>>
>> Drop that. We should never set man->pipelined_eviction.fences to NULL.
>
> Why?
To simplify the logic while filling the slots.
dma_fences are made to be keept around for long.
>>
>>> +
>>> /**
>>> * enum ttm_lru_item_type - enumerate ttm_lru_item subclasses
>>> */
>>> @@ -180,8 +189,10 @@ struct ttm_resource_manager_func {
>>> * @size: Size of the managed region.
>>> * @bdev: ttm device this manager belongs to
>>> * @func: structure pointer implementing the range manager. See above
>>> - * @move_lock: lock for move fence
>>> - * @move: The fence of the last pipelined move operation.
>>> + * @pipelined_eviction.lock: lock for eviction fences
>>> + * @pipelined_eviction.n_fences: The number of fences allowed in the array. If
>>> + * 0, pipelined evictions aren't used.
>>> + * @pipelined_eviction.fences: The fences of the last pipelined move operation.
>>> * @lru: The lru list for this memory type.
>>> *
>>> * This structure is used to identify and manage memory types for a device.
>>> @@ -195,12 +206,15 @@ struct ttm_resource_manager {
>>> struct ttm_device *bdev;
>>> uint64_t size;
>>> const struct ttm_resource_manager_func *func;
>>> - spinlock_t move_lock;
>>> - /*
>>> - * Protected by @move_lock.
>>> + /* This is very similar to a dma_resv object, but locking rules make
>>> + * it difficult to use a it in this context.
>>> */
>>> - struct dma_fence *move;
>>> + struct {
>>> + spinlock_t lock;
>>> + int n_fences;
>>> + struct dma_fence *fences[TTM_FENCES_MAX_SLOT_COUNT];
>>> + } pipelined_eviction;
>>
>> Drop the separate structure, just make move an array instead.
>
> IMO pipelined_eviction.fences and pipelined_eviction.lock is clearer when reading the code than moves and move_lock but if you prefer I'll switch back to the old names.
The name "pipelined_eviction" is just a bit to long. Maybe just eviction_fences and eviction_fences_lock?
Regards,
Christian.
>>
>> And also drop n_fences. Just always take a look at all fences.
>
> OK.
>
> Thanks,
> Pierre-Eric
>
>>
>> Regards,
>> Christian.
>>
>>> /*
>>> * Protected by the bdev->lru_lock.
>>> @@ -421,8 +435,12 @@ static inline bool ttm_resource_manager_used(struct ttm_resource_manager *man)
>>> static inline void
>>> ttm_resource_manager_cleanup(struct ttm_resource_manager *man)
>>> {
>>> - dma_fence_put(man->move);
>>> - man->move = NULL;
>>> + int i;
>>> +
>>> + for (i = 0; i < TTM_FENCES_MAX_SLOT_COUNT; i++) {
>>> + dma_fence_put(man->pipelined_eviction.fences[i]);
>>> + man->pipelined_eviction.fences[i] = NULL;
>>> + }
>>> }
>>> void ttm_lru_bulk_move_init(struct ttm_lru_bulk_move *bulk);
^ permalink raw reply [flat|nested] 40+ messages in thread
* [PATCH v1 03/20] drm/amdgpu: remove direct_submit arg from amdgpu_copy_buffer
2025-11-04 8:35 [PATCH v1 00/20] drm/amdgpu: use all SDMA instances for TTM clears and moves Pierre-Eric Pelloux-Prayer
2025-11-04 8:35 ` [PATCH v1 01/20] drm/amdgpu: give each kernel job a unique id Pierre-Eric Pelloux-Prayer
2025-11-04 8:35 ` [PATCH v1 02/20] drm/ttm: rework pipelined eviction fence handling Pierre-Eric Pelloux-Prayer
@ 2025-11-04 8:35 ` Pierre-Eric Pelloux-Prayer
2025-11-04 14:13 ` Christian König
2025-11-04 8:35 ` [PATCH v1 04/20] drm/amdgpu: introduce amdgpu_ttm_entity Pierre-Eric Pelloux-Prayer
` (16 subsequent siblings)
19 siblings, 1 reply; 40+ messages in thread
From: Pierre-Eric Pelloux-Prayer @ 2025-11-04 8:35 UTC (permalink / raw)
To: Alex Deucher, Christian König, David Airlie, Simona Vetter,
Felix Kuehling, Sumit Semwal
Cc: Pierre-Eric Pelloux-Prayer, amd-gfx, dri-devel, linux-kernel,
linux-media, linaro-mm-sig
It was always false.
Signed-off-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 20 +++++++------------
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 2 +-
drivers/gpu/drm/amd/amdkfd/kfd_migrate.c | 2 +-
4 files changed, 10 insertions(+), 16 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c
index 199693369c7c..02c2479a8840 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c
@@ -39,7 +39,7 @@ static int amdgpu_benchmark_do_move(struct amdgpu_device *adev, unsigned size,
for (i = 0; i < n; i++) {
struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
r = amdgpu_copy_buffer(ring, saddr, daddr, size, NULL, &fence,
- false, false, 0);
+ false, 0);
if (r)
goto exit_do_move;
r = dma_fence_wait(fence, false);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index c66f00434991..fce22712396b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -354,7 +354,7 @@ static int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
}
r = amdgpu_copy_buffer(ring, from, to, cur_size, resv,
- &next, false, true, copy_flags);
+ &next, true, copy_flags);
if (r)
goto error;
@@ -2211,16 +2211,13 @@ void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable)
}
static int amdgpu_ttm_prepare_job(struct amdgpu_device *adev,
- bool direct_submit,
unsigned int num_dw,
struct dma_resv *resv,
bool vm_needs_flush,
struct amdgpu_job **job,
bool delayed, u64 k_job_id)
{
- enum amdgpu_ib_pool_type pool = direct_submit ?
- AMDGPU_IB_POOL_DIRECT :
- AMDGPU_IB_POOL_DELAYED;
+ enum amdgpu_ib_pool_type pool = AMDGPU_IB_POOL_DELAYED;
int r;
struct drm_sched_entity *entity = delayed ? &adev->mman.low_pr :
&adev->mman.high_pr;
@@ -2246,7 +2243,7 @@ static int amdgpu_ttm_prepare_job(struct amdgpu_device *adev,
int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
uint64_t dst_offset, uint32_t byte_count,
struct dma_resv *resv,
- struct dma_fence **fence, bool direct_submit,
+ struct dma_fence **fence,
bool vm_needs_flush, uint32_t copy_flags)
{
struct amdgpu_device *adev = ring->adev;
@@ -2256,7 +2253,7 @@ int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
unsigned int i;
int r;
- if (!direct_submit && !ring->sched.ready) {
+ if (!ring->sched.ready) {
dev_err(adev->dev,
"Trying to move memory with ring turned off.\n");
return -EINVAL;
@@ -2265,7 +2262,7 @@ int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
max_bytes = adev->mman.buffer_funcs->copy_max_bytes;
num_loops = DIV_ROUND_UP(byte_count, max_bytes);
num_dw = ALIGN(num_loops * adev->mman.buffer_funcs->copy_num_dw, 8);
- r = amdgpu_ttm_prepare_job(adev, direct_submit, num_dw,
+ r = amdgpu_ttm_prepare_job(adev, num_dw,
resv, vm_needs_flush, &job, false,
AMDGPU_KERNEL_JOB_ID_TTM_COPY_BUFFER);
if (r)
@@ -2283,10 +2280,7 @@ int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
amdgpu_ring_pad_ib(ring, &job->ibs[0]);
WARN_ON(job->ibs[0].length_dw > num_dw);
- if (direct_submit)
- r = amdgpu_job_submit_direct(job, ring, fence);
- else
- *fence = amdgpu_job_submit(job);
+ *fence = amdgpu_job_submit(job);
if (r)
goto error_free;
@@ -2315,7 +2309,7 @@ static int amdgpu_ttm_fill_mem(struct amdgpu_ring *ring, uint32_t src_data,
max_bytes = adev->mman.buffer_funcs->fill_max_bytes;
num_loops = DIV_ROUND_UP_ULL(byte_count, max_bytes);
num_dw = ALIGN(num_loops * adev->mman.buffer_funcs->fill_num_dw, 8);
- r = amdgpu_ttm_prepare_job(adev, false, num_dw, resv, vm_needs_flush,
+ r = amdgpu_ttm_prepare_job(adev, num_dw, resv, vm_needs_flush,
&job, delayed, k_job_id);
if (r)
return r;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
index 577ee04ce0bf..50e40380fe95 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
@@ -166,7 +166,7 @@ void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev,
int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
uint64_t dst_offset, uint32_t byte_count,
struct dma_resv *resv,
- struct dma_fence **fence, bool direct_submit,
+ struct dma_fence **fence,
bool vm_needs_flush, uint32_t copy_flags);
int amdgpu_ttm_clear_buffer(struct amdgpu_bo *bo,
struct dma_resv *resv,
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
index 46c84fc60af1..378af0b2aaa9 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
@@ -153,7 +153,7 @@ svm_migrate_copy_memory_gart(struct amdgpu_device *adev, dma_addr_t *sys,
}
r = amdgpu_copy_buffer(ring, gart_s, gart_d, size * PAGE_SIZE,
- NULL, &next, false, true, 0);
+ NULL, &next, true, 0);
if (r) {
dev_err(adev->dev, "fail %d to copy memory\n", r);
goto out_unlock;
--
2.43.0
^ permalink raw reply [flat|nested] 40+ messages in thread* Re: [PATCH v1 03/20] drm/amdgpu: remove direct_submit arg from amdgpu_copy_buffer
2025-11-04 8:35 ` [PATCH v1 03/20] drm/amdgpu: remove direct_submit arg from amdgpu_copy_buffer Pierre-Eric Pelloux-Prayer
@ 2025-11-04 14:13 ` Christian König
0 siblings, 0 replies; 40+ messages in thread
From: Christian König @ 2025-11-04 14:13 UTC (permalink / raw)
To: Pierre-Eric Pelloux-Prayer, Alex Deucher, David Airlie,
Simona Vetter, Felix Kuehling, Sumit Semwal
Cc: amd-gfx, dri-devel, linux-kernel, linux-media, linaro-mm-sig
On 11/4/25 09:35, Pierre-Eric Pelloux-Prayer wrote:
> It was always false.
>
> Signed-off-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 20 +++++++------------
> drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 2 +-
> drivers/gpu/drm/amd/amdkfd/kfd_migrate.c | 2 +-
> 4 files changed, 10 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c
> index 199693369c7c..02c2479a8840 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c
> @@ -39,7 +39,7 @@ static int amdgpu_benchmark_do_move(struct amdgpu_device *adev, unsigned size,
> for (i = 0; i < n; i++) {
> struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
> r = amdgpu_copy_buffer(ring, saddr, daddr, size, NULL, &fence,
> - false, false, 0);
> + false, 0);
> if (r)
> goto exit_do_move;
> r = dma_fence_wait(fence, false);
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> index c66f00434991..fce22712396b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> @@ -354,7 +354,7 @@ static int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
> }
>
> r = amdgpu_copy_buffer(ring, from, to, cur_size, resv,
> - &next, false, true, copy_flags);
> + &next, true, copy_flags);
> if (r)
> goto error;
>
> @@ -2211,16 +2211,13 @@ void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable)
> }
>
> static int amdgpu_ttm_prepare_job(struct amdgpu_device *adev,
> - bool direct_submit,
> unsigned int num_dw,
> struct dma_resv *resv,
> bool vm_needs_flush,
> struct amdgpu_job **job,
> bool delayed, u64 k_job_id)
> {
> - enum amdgpu_ib_pool_type pool = direct_submit ?
> - AMDGPU_IB_POOL_DIRECT :
> - AMDGPU_IB_POOL_DELAYED;
> + enum amdgpu_ib_pool_type pool = AMDGPU_IB_POOL_DELAYED;
> int r;
> struct drm_sched_entity *entity = delayed ? &adev->mman.low_pr :
> &adev->mman.high_pr;
> @@ -2246,7 +2243,7 @@ static int amdgpu_ttm_prepare_job(struct amdgpu_device *adev,
> int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
> uint64_t dst_offset, uint32_t byte_count,
> struct dma_resv *resv,
> - struct dma_fence **fence, bool direct_submit,
> + struct dma_fence **fence,
> bool vm_needs_flush, uint32_t copy_flags)
> {
> struct amdgpu_device *adev = ring->adev;
> @@ -2256,7 +2253,7 @@ int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
> unsigned int i;
> int r;
>
> - if (!direct_submit && !ring->sched.ready) {
> + if (!ring->sched.ready) {
> dev_err(adev->dev,
> "Trying to move memory with ring turned off.\n");
> return -EINVAL;
> @@ -2265,7 +2262,7 @@ int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
> max_bytes = adev->mman.buffer_funcs->copy_max_bytes;
> num_loops = DIV_ROUND_UP(byte_count, max_bytes);
> num_dw = ALIGN(num_loops * adev->mman.buffer_funcs->copy_num_dw, 8);
> - r = amdgpu_ttm_prepare_job(adev, direct_submit, num_dw,
> + r = amdgpu_ttm_prepare_job(adev, num_dw,
> resv, vm_needs_flush, &job, false,
> AMDGPU_KERNEL_JOB_ID_TTM_COPY_BUFFER);
> if (r)
> @@ -2283,10 +2280,7 @@ int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
>
> amdgpu_ring_pad_ib(ring, &job->ibs[0]);
> WARN_ON(job->ibs[0].length_dw > num_dw);
> - if (direct_submit)
> - r = amdgpu_job_submit_direct(job, ring, fence);
> - else
> - *fence = amdgpu_job_submit(job);
> + *fence = amdgpu_job_submit(job);
> if (r)
> goto error_free;
>
> @@ -2315,7 +2309,7 @@ static int amdgpu_ttm_fill_mem(struct amdgpu_ring *ring, uint32_t src_data,
> max_bytes = adev->mman.buffer_funcs->fill_max_bytes;
> num_loops = DIV_ROUND_UP_ULL(byte_count, max_bytes);
> num_dw = ALIGN(num_loops * adev->mman.buffer_funcs->fill_num_dw, 8);
> - r = amdgpu_ttm_prepare_job(adev, false, num_dw, resv, vm_needs_flush,
> + r = amdgpu_ttm_prepare_job(adev, num_dw, resv, vm_needs_flush,
> &job, delayed, k_job_id);
> if (r)
> return r;
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
> index 577ee04ce0bf..50e40380fe95 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
> @@ -166,7 +166,7 @@ void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev,
> int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
> uint64_t dst_offset, uint32_t byte_count,
> struct dma_resv *resv,
> - struct dma_fence **fence, bool direct_submit,
> + struct dma_fence **fence,
> bool vm_needs_flush, uint32_t copy_flags);
> int amdgpu_ttm_clear_buffer(struct amdgpu_bo *bo,
> struct dma_resv *resv,
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
> index 46c84fc60af1..378af0b2aaa9 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
> @@ -153,7 +153,7 @@ svm_migrate_copy_memory_gart(struct amdgpu_device *adev, dma_addr_t *sys,
> }
>
> r = amdgpu_copy_buffer(ring, gart_s, gart_d, size * PAGE_SIZE,
> - NULL, &next, false, true, 0);
> + NULL, &next, true, 0);
> if (r) {
> dev_err(adev->dev, "fail %d to copy memory\n", r);
> goto out_unlock;
^ permalink raw reply [flat|nested] 40+ messages in thread
* [PATCH v1 04/20] drm/amdgpu: introduce amdgpu_ttm_entity
2025-11-04 8:35 [PATCH v1 00/20] drm/amdgpu: use all SDMA instances for TTM clears and moves Pierre-Eric Pelloux-Prayer
` (2 preceding siblings ...)
2025-11-04 8:35 ` [PATCH v1 03/20] drm/amdgpu: remove direct_submit arg from amdgpu_copy_buffer Pierre-Eric Pelloux-Prayer
@ 2025-11-04 8:35 ` Pierre-Eric Pelloux-Prayer
2025-11-04 15:13 ` Christian König
2025-11-04 8:35 ` [PATCH v1 05/20] drm/amdgpu: pass the entity to use to ttm functions Pierre-Eric Pelloux-Prayer
` (15 subsequent siblings)
19 siblings, 1 reply; 40+ messages in thread
From: Pierre-Eric Pelloux-Prayer @ 2025-11-04 8:35 UTC (permalink / raw)
To: Alex Deucher, Christian König, David Airlie, Simona Vetter,
Felix Kuehling
Cc: Pierre-Eric Pelloux-Prayer, amd-gfx, dri-devel, linux-kernel
No functional change for now, but this struct will have more
fields added in the next commit.
Technically the change introduces synchronisation issue, because
dependencies between successive jobs are not taken care of
properly. For instance, amdgpu_ttm_clear_buffer uses
amdgpu_ttm_map_buffer then amdgpu_ttm_fill_mem which use
different entities (default_entity then move/clear entity).
But it's all working as expected, because all entities use the
same sdma instance for now and default_entity has a higher prio
so its job always gets scheduler first.
The next commits will deal with these dependencies correctly.
Signed-off-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 30 +++++++++++++++++-------
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 12 ++++++----
drivers/gpu/drm/amd/amdkfd/kfd_migrate.c | 13 ++++++----
4 files changed, 39 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
index 9dcf51991b5b..8e2d41c9c271 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
@@ -687,7 +687,7 @@ void amdgpu_gmc_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
* itself at least for GART.
*/
mutex_lock(&adev->mman.gtt_window_lock);
- r = amdgpu_job_alloc_with_ib(ring->adev, &adev->mman.high_pr,
+ r = amdgpu_job_alloc_with_ib(ring->adev, &adev->mman.default_entity.base,
AMDGPU_FENCE_OWNER_UNDEFINED,
16 * 4, AMDGPU_IB_POOL_IMMEDIATE,
&job, AMDGPU_KERNEL_JOB_ID_FLUSH_GPU_TLB);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index fce22712396b..94e909905c64 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -224,7 +224,7 @@ static int amdgpu_ttm_map_buffer(struct ttm_buffer_object *bo,
num_dw = ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8);
num_bytes = num_pages * 8 * AMDGPU_GPU_PAGES_IN_CPU_PAGE;
- r = amdgpu_job_alloc_with_ib(adev, &adev->mman.high_pr,
+ r = amdgpu_job_alloc_with_ib(adev, &adev->mman.default_entity.base,
AMDGPU_FENCE_OWNER_UNDEFINED,
num_dw * 4 + num_bytes,
AMDGPU_IB_POOL_DELAYED, &job,
@@ -1486,7 +1486,7 @@ static int amdgpu_ttm_access_memory_sdma(struct ttm_buffer_object *bo,
memcpy(adev->mman.sdma_access_ptr, buf, len);
num_dw = ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8);
- r = amdgpu_job_alloc_with_ib(adev, &adev->mman.high_pr,
+ r = amdgpu_job_alloc_with_ib(adev, &adev->mman.default_entity.base,
AMDGPU_FENCE_OWNER_UNDEFINED,
num_dw * 4, AMDGPU_IB_POOL_DELAYED,
&job,
@@ -2168,7 +2168,7 @@ void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable)
ring = adev->mman.buffer_funcs_ring;
sched = &ring->sched;
- r = drm_sched_entity_init(&adev->mman.high_pr,
+ r = drm_sched_entity_init(&adev->mman.default_entity.base,
DRM_SCHED_PRIORITY_KERNEL, &sched,
1, NULL);
if (r) {
@@ -2178,18 +2178,30 @@ void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable)
return;
}
- r = drm_sched_entity_init(&adev->mman.low_pr,
+ r = drm_sched_entity_init(&adev->mman.clear_entity.base,
+ DRM_SCHED_PRIORITY_NORMAL, &sched,
+ 1, NULL);
+ if (r) {
+ dev_err(adev->dev,
+ "Failed setting up TTM BO clear entity (%d)\n",
+ r);
+ goto error_free_entity;
+ }
+
+ r = drm_sched_entity_init(&adev->mman.move_entity.base,
DRM_SCHED_PRIORITY_NORMAL, &sched,
1, NULL);
if (r) {
dev_err(adev->dev,
"Failed setting up TTM BO move entity (%d)\n",
r);
+ drm_sched_entity_destroy(&adev->mman.clear_entity.base);
goto error_free_entity;
}
} else {
- drm_sched_entity_destroy(&adev->mman.high_pr);
- drm_sched_entity_destroy(&adev->mman.low_pr);
+ drm_sched_entity_destroy(&adev->mman.default_entity.base);
+ drm_sched_entity_destroy(&adev->mman.clear_entity.base);
+ drm_sched_entity_destroy(&adev->mman.move_entity.base);
for (i = 0; i < TTM_FENCES_MAX_SLOT_COUNT; i++) {
dma_fence_put(man->pipelined_eviction.fences[i]);
man->pipelined_eviction.fences[i] = NULL;
@@ -2207,7 +2219,7 @@ void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable)
return;
error_free_entity:
- drm_sched_entity_destroy(&adev->mman.high_pr);
+ drm_sched_entity_destroy(&adev->mman.default_entity.base);
}
static int amdgpu_ttm_prepare_job(struct amdgpu_device *adev,
@@ -2219,8 +2231,8 @@ static int amdgpu_ttm_prepare_job(struct amdgpu_device *adev,
{
enum amdgpu_ib_pool_type pool = AMDGPU_IB_POOL_DELAYED;
int r;
- struct drm_sched_entity *entity = delayed ? &adev->mman.low_pr :
- &adev->mman.high_pr;
+ struct drm_sched_entity *entity = delayed ? &adev->mman.clear_entity.base :
+ &adev->mman.move_entity.base;
r = amdgpu_job_alloc_with_ib(adev, entity,
AMDGPU_FENCE_OWNER_UNDEFINED,
num_dw * 4, pool, job, k_job_id);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
index 50e40380fe95..f83313bc0afb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
@@ -52,6 +52,10 @@ struct amdgpu_gtt_mgr {
spinlock_t lock;
};
+struct amdgpu_ttm_entity {
+ struct drm_sched_entity base;
+};
+
struct amdgpu_mman {
struct ttm_device bdev;
struct ttm_pool *ttm_pools;
@@ -64,10 +68,10 @@ struct amdgpu_mman {
bool buffer_funcs_enabled;
struct mutex gtt_window_lock;
- /* High priority scheduler entity for buffer moves */
- struct drm_sched_entity high_pr;
- /* Low priority scheduler entity for VRAM clearing */
- struct drm_sched_entity low_pr;
+
+ struct amdgpu_ttm_entity default_entity;
+ struct amdgpu_ttm_entity clear_entity;
+ struct amdgpu_ttm_entity move_entity;
struct amdgpu_vram_mgr vram_mgr;
struct amdgpu_gtt_mgr gtt_mgr;
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
index 378af0b2aaa9..1d35a89999f7 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
@@ -45,7 +45,9 @@ svm_migrate_direct_mapping_addr(struct amdgpu_device *adev, u64 addr)
}
static int
-svm_migrate_gart_map(struct amdgpu_ring *ring, u64 npages,
+svm_migrate_gart_map(struct amdgpu_ring *ring,
+ struct amdgpu_ttm_entity *entity,
+ u64 npages,
dma_addr_t *addr, u64 *gart_addr, u64 flags)
{
struct amdgpu_device *adev = ring->adev;
@@ -63,7 +65,7 @@ svm_migrate_gart_map(struct amdgpu_ring *ring, u64 npages,
num_dw = ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8);
num_bytes = npages * 8;
- r = amdgpu_job_alloc_with_ib(adev, &adev->mman.high_pr,
+ r = amdgpu_job_alloc_with_ib(adev, &entity->base,
AMDGPU_FENCE_OWNER_UNDEFINED,
num_dw * 4 + num_bytes,
AMDGPU_IB_POOL_DELAYED,
@@ -128,11 +130,14 @@ svm_migrate_copy_memory_gart(struct amdgpu_device *adev, dma_addr_t *sys,
{
const u64 GTT_MAX_PAGES = AMDGPU_GTT_MAX_TRANSFER_SIZE;
struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
+ struct amdgpu_ttm_entity *entity;
u64 gart_s, gart_d;
struct dma_fence *next;
u64 size;
int r;
+ entity = &adev->mman.move_entity;
+
mutex_lock(&adev->mman.gtt_window_lock);
while (npages) {
@@ -140,10 +145,10 @@ svm_migrate_copy_memory_gart(struct amdgpu_device *adev, dma_addr_t *sys,
if (direction == FROM_VRAM_TO_RAM) {
gart_s = svm_migrate_direct_mapping_addr(adev, *vram);
- r = svm_migrate_gart_map(ring, size, sys, &gart_d, 0);
+ r = svm_migrate_gart_map(ring, entity, size, sys, &gart_d, 0);
} else if (direction == FROM_RAM_TO_VRAM) {
- r = svm_migrate_gart_map(ring, size, sys, &gart_s,
+ r = svm_migrate_gart_map(ring, entity, size, sys, &gart_s,
KFD_IOCTL_SVM_FLAG_GPU_RO);
gart_d = svm_migrate_direct_mapping_addr(adev, *vram);
}
--
2.43.0
^ permalink raw reply [flat|nested] 40+ messages in thread* Re: [PATCH v1 04/20] drm/amdgpu: introduce amdgpu_ttm_entity
2025-11-04 8:35 ` [PATCH v1 04/20] drm/amdgpu: introduce amdgpu_ttm_entity Pierre-Eric Pelloux-Prayer
@ 2025-11-04 15:13 ` Christian König
0 siblings, 0 replies; 40+ messages in thread
From: Christian König @ 2025-11-04 15:13 UTC (permalink / raw)
To: Pierre-Eric Pelloux-Prayer, Alex Deucher, David Airlie,
Simona Vetter, Felix Kuehling
Cc: amd-gfx, dri-devel, linux-kernel
On 11/4/25 09:35, Pierre-Eric Pelloux-Prayer wrote:
> No functional change for now, but this struct will have more
> fields added in the next commit.
>
> Technically the change introduces synchronisation issue, because
> dependencies between successive jobs are not taken care of
> properly. For instance, amdgpu_ttm_clear_buffer uses
> amdgpu_ttm_map_buffer then amdgpu_ttm_fill_mem which use
> different entities (default_entity then move/clear entity).
> But it's all working as expected, because all entities use the
> same sdma instance for now and default_entity has a higher prio
> so its job always gets scheduler first.
>
> The next commits will deal with these dependencies correctly.
>
> Signed-off-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 30 +++++++++++++++++-------
> drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 12 ++++++----
> drivers/gpu/drm/amd/amdkfd/kfd_migrate.c | 13 ++++++----
> 4 files changed, 39 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
> index 9dcf51991b5b..8e2d41c9c271 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
> @@ -687,7 +687,7 @@ void amdgpu_gmc_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
> * itself at least for GART.
> */
> mutex_lock(&adev->mman.gtt_window_lock);
> - r = amdgpu_job_alloc_with_ib(ring->adev, &adev->mman.high_pr,
> + r = amdgpu_job_alloc_with_ib(ring->adev, &adev->mman.default_entity.base,
> AMDGPU_FENCE_OWNER_UNDEFINED,
> 16 * 4, AMDGPU_IB_POOL_IMMEDIATE,
> &job, AMDGPU_KERNEL_JOB_ID_FLUSH_GPU_TLB);
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> index fce22712396b..94e909905c64 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> @@ -224,7 +224,7 @@ static int amdgpu_ttm_map_buffer(struct ttm_buffer_object *bo,
> num_dw = ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8);
> num_bytes = num_pages * 8 * AMDGPU_GPU_PAGES_IN_CPU_PAGE;
>
> - r = amdgpu_job_alloc_with_ib(adev, &adev->mman.high_pr,
> + r = amdgpu_job_alloc_with_ib(adev, &adev->mman.default_entity.base,
> AMDGPU_FENCE_OWNER_UNDEFINED,
> num_dw * 4 + num_bytes,
> AMDGPU_IB_POOL_DELAYED, &job,
> @@ -1486,7 +1486,7 @@ static int amdgpu_ttm_access_memory_sdma(struct ttm_buffer_object *bo,
> memcpy(adev->mman.sdma_access_ptr, buf, len);
>
> num_dw = ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8);
> - r = amdgpu_job_alloc_with_ib(adev, &adev->mman.high_pr,
> + r = amdgpu_job_alloc_with_ib(adev, &adev->mman.default_entity.base,
> AMDGPU_FENCE_OWNER_UNDEFINED,
> num_dw * 4, AMDGPU_IB_POOL_DELAYED,
> &job,
> @@ -2168,7 +2168,7 @@ void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable)
>
> ring = adev->mman.buffer_funcs_ring;
> sched = &ring->sched;
> - r = drm_sched_entity_init(&adev->mman.high_pr,
> + r = drm_sched_entity_init(&adev->mman.default_entity.base,
> DRM_SCHED_PRIORITY_KERNEL, &sched,
> 1, NULL);
> if (r) {
> @@ -2178,18 +2178,30 @@ void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable)
> return;
> }
>
> - r = drm_sched_entity_init(&adev->mman.low_pr,
> + r = drm_sched_entity_init(&adev->mman.clear_entity.base,
> + DRM_SCHED_PRIORITY_NORMAL, &sched,
> + 1, NULL);
> + if (r) {
> + dev_err(adev->dev,
> + "Failed setting up TTM BO clear entity (%d)\n",
> + r);
> + goto error_free_entity;
> + }
> +
> + r = drm_sched_entity_init(&adev->mman.move_entity.base,
> DRM_SCHED_PRIORITY_NORMAL, &sched,
> 1, NULL);
> if (r) {
> dev_err(adev->dev,
> "Failed setting up TTM BO move entity (%d)\n",
> r);
> + drm_sched_entity_destroy(&adev->mman.clear_entity.base);
> goto error_free_entity;
> }
> } else {
> - drm_sched_entity_destroy(&adev->mman.high_pr);
> - drm_sched_entity_destroy(&adev->mman.low_pr);
> + drm_sched_entity_destroy(&adev->mman.default_entity.base);
> + drm_sched_entity_destroy(&adev->mman.clear_entity.base);
> + drm_sched_entity_destroy(&adev->mman.move_entity.base);
> for (i = 0; i < TTM_FENCES_MAX_SLOT_COUNT; i++) {
> dma_fence_put(man->pipelined_eviction.fences[i]);
> man->pipelined_eviction.fences[i] = NULL;
> @@ -2207,7 +2219,7 @@ void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable)
> return;
>
> error_free_entity:
> - drm_sched_entity_destroy(&adev->mman.high_pr);
> + drm_sched_entity_destroy(&adev->mman.default_entity.base);
> }
>
> static int amdgpu_ttm_prepare_job(struct amdgpu_device *adev,
> @@ -2219,8 +2231,8 @@ static int amdgpu_ttm_prepare_job(struct amdgpu_device *adev,
> {
> enum amdgpu_ib_pool_type pool = AMDGPU_IB_POOL_DELAYED;
> int r;
> - struct drm_sched_entity *entity = delayed ? &adev->mman.low_pr :
> - &adev->mman.high_pr;
> + struct drm_sched_entity *entity = delayed ? &adev->mman.clear_entity.base :
> + &adev->mman.move_entity.base;
> r = amdgpu_job_alloc_with_ib(adev, entity,
> AMDGPU_FENCE_OWNER_UNDEFINED,
> num_dw * 4, pool, job, k_job_id);
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
> index 50e40380fe95..f83313bc0afb 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
> @@ -52,6 +52,10 @@ struct amdgpu_gtt_mgr {
> spinlock_t lock;
> };
>
> +struct amdgpu_ttm_entity {
Mhm, I think this needs a better name.
Maybe amdgpu_ttm_buffer_entity or something like that.
Apart from that looks good to me.
Christian.
> + struct drm_sched_entity base;
> +};
> +
> struct amdgpu_mman {
> struct ttm_device bdev;
> struct ttm_pool *ttm_pools;
> @@ -64,10 +68,10 @@ struct amdgpu_mman {
> bool buffer_funcs_enabled;
>
> struct mutex gtt_window_lock;
> - /* High priority scheduler entity for buffer moves */
> - struct drm_sched_entity high_pr;
> - /* Low priority scheduler entity for VRAM clearing */
> - struct drm_sched_entity low_pr;
> +
> + struct amdgpu_ttm_entity default_entity;
> + struct amdgpu_ttm_entity clear_entity;
> + struct amdgpu_ttm_entity move_entity;
>
> struct amdgpu_vram_mgr vram_mgr;
> struct amdgpu_gtt_mgr gtt_mgr;
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
> index 378af0b2aaa9..1d35a89999f7 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
> @@ -45,7 +45,9 @@ svm_migrate_direct_mapping_addr(struct amdgpu_device *adev, u64 addr)
> }
>
> static int
> -svm_migrate_gart_map(struct amdgpu_ring *ring, u64 npages,
> +svm_migrate_gart_map(struct amdgpu_ring *ring,
> + struct amdgpu_ttm_entity *entity,
> + u64 npages,
> dma_addr_t *addr, u64 *gart_addr, u64 flags)
> {
> struct amdgpu_device *adev = ring->adev;
> @@ -63,7 +65,7 @@ svm_migrate_gart_map(struct amdgpu_ring *ring, u64 npages,
> num_dw = ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8);
> num_bytes = npages * 8;
>
> - r = amdgpu_job_alloc_with_ib(adev, &adev->mman.high_pr,
> + r = amdgpu_job_alloc_with_ib(adev, &entity->base,
> AMDGPU_FENCE_OWNER_UNDEFINED,
> num_dw * 4 + num_bytes,
> AMDGPU_IB_POOL_DELAYED,
> @@ -128,11 +130,14 @@ svm_migrate_copy_memory_gart(struct amdgpu_device *adev, dma_addr_t *sys,
> {
> const u64 GTT_MAX_PAGES = AMDGPU_GTT_MAX_TRANSFER_SIZE;
> struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
> + struct amdgpu_ttm_entity *entity;
> u64 gart_s, gart_d;
> struct dma_fence *next;
> u64 size;
> int r;
>
> + entity = &adev->mman.move_entity;
> +
> mutex_lock(&adev->mman.gtt_window_lock);
>
> while (npages) {
> @@ -140,10 +145,10 @@ svm_migrate_copy_memory_gart(struct amdgpu_device *adev, dma_addr_t *sys,
>
> if (direction == FROM_VRAM_TO_RAM) {
> gart_s = svm_migrate_direct_mapping_addr(adev, *vram);
> - r = svm_migrate_gart_map(ring, size, sys, &gart_d, 0);
> + r = svm_migrate_gart_map(ring, entity, size, sys, &gart_d, 0);
>
> } else if (direction == FROM_RAM_TO_VRAM) {
> - r = svm_migrate_gart_map(ring, size, sys, &gart_s,
> + r = svm_migrate_gart_map(ring, entity, size, sys, &gart_s,
> KFD_IOCTL_SVM_FLAG_GPU_RO);
> gart_d = svm_migrate_direct_mapping_addr(adev, *vram);
> }
^ permalink raw reply [flat|nested] 40+ messages in thread
* [PATCH v1 05/20] drm/amdgpu: pass the entity to use to ttm functions
2025-11-04 8:35 [PATCH v1 00/20] drm/amdgpu: use all SDMA instances for TTM clears and moves Pierre-Eric Pelloux-Prayer
` (3 preceding siblings ...)
2025-11-04 8:35 ` [PATCH v1 04/20] drm/amdgpu: introduce amdgpu_ttm_entity Pierre-Eric Pelloux-Prayer
@ 2025-11-04 8:35 ` Pierre-Eric Pelloux-Prayer
2025-11-04 8:35 ` [PATCH v1 06/20] drm/amdgpu: statically assign gart windows to ttm entities Pierre-Eric Pelloux-Prayer
` (14 subsequent siblings)
19 siblings, 0 replies; 40+ messages in thread
From: Pierre-Eric Pelloux-Prayer @ 2025-11-04 8:35 UTC (permalink / raw)
To: Alex Deucher, Christian König, David Airlie, Simona Vetter,
Felix Kuehling, Sumit Semwal
Cc: Pierre-Eric Pelloux-Prayer, amd-gfx, dri-devel, linux-kernel,
linux-media, linaro-mm-sig
This way the caller can select the one it wants to use.
Signed-off-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c | 3 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 4 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 75 +++++++++++--------
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 16 ++--
drivers/gpu/drm/amd/amdkfd/kfd_migrate.c | 3 +-
5 files changed, 60 insertions(+), 41 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c
index 02c2479a8840..b59040a8771f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c
@@ -38,7 +38,8 @@ static int amdgpu_benchmark_do_move(struct amdgpu_device *adev, unsigned size,
stime = ktime_get();
for (i = 0; i < n; i++) {
struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
- r = amdgpu_copy_buffer(ring, saddr, daddr, size, NULL, &fence,
+ r = amdgpu_copy_buffer(ring, &adev->mman.default_entity.base,
+ saddr, daddr, size, NULL, &fence,
false, 0);
if (r)
goto exit_do_move;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index e08f58de4b17..c06c132a753c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -1321,8 +1321,8 @@ void amdgpu_bo_release_notify(struct ttm_buffer_object *bo)
if (r)
goto out;
- r = amdgpu_fill_buffer(abo, 0, &bo->base._resv, &fence, true,
- AMDGPU_KERNEL_JOB_ID_CLEAR_ON_RELEASE);
+ r = amdgpu_fill_buffer(&adev->mman.clear_entity, abo, 0, &bo->base._resv,
+ &fence, AMDGPU_KERNEL_JOB_ID_CLEAR_ON_RELEASE);
if (WARN_ON(r))
goto out;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 94e909905c64..bd35bea4b573 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -164,6 +164,7 @@ static void amdgpu_evict_flags(struct ttm_buffer_object *bo,
/**
* amdgpu_ttm_map_buffer - Map memory into the GART windows
+ * @entity: entity to run the window setup job
* @bo: buffer object to map
* @mem: memory object to map
* @mm_cur: range to map
@@ -176,7 +177,8 @@ static void amdgpu_evict_flags(struct ttm_buffer_object *bo,
* Setup one of the GART windows to access a specific piece of memory or return
* the physical address for local memory.
*/
-static int amdgpu_ttm_map_buffer(struct ttm_buffer_object *bo,
+static int amdgpu_ttm_map_buffer(struct drm_sched_entity *entity,
+ struct ttm_buffer_object *bo,
struct ttm_resource *mem,
struct amdgpu_res_cursor *mm_cur,
unsigned int window, struct amdgpu_ring *ring,
@@ -224,7 +226,7 @@ static int amdgpu_ttm_map_buffer(struct ttm_buffer_object *bo,
num_dw = ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8);
num_bytes = num_pages * 8 * AMDGPU_GPU_PAGES_IN_CPU_PAGE;
- r = amdgpu_job_alloc_with_ib(adev, &adev->mman.default_entity.base,
+ r = amdgpu_job_alloc_with_ib(adev, entity,
AMDGPU_FENCE_OWNER_UNDEFINED,
num_dw * 4 + num_bytes,
AMDGPU_IB_POOL_DELAYED, &job,
@@ -274,6 +276,7 @@ static int amdgpu_ttm_map_buffer(struct ttm_buffer_object *bo,
/**
* amdgpu_ttm_copy_mem_to_mem - Helper function for copy
* @adev: amdgpu device
+ * @entity: entity to run the jobs
* @src: buffer/address where to read from
* @dst: buffer/address where to write to
* @size: number of bytes to copy
@@ -288,6 +291,7 @@ static int amdgpu_ttm_map_buffer(struct ttm_buffer_object *bo,
*/
__attribute__((nonnull))
static int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
+ struct drm_sched_entity *entity,
const struct amdgpu_copy_mem *src,
const struct amdgpu_copy_mem *dst,
uint64_t size, bool tmz,
@@ -320,12 +324,14 @@ static int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
cur_size = min3(src_mm.size, dst_mm.size, 256ULL << 20);
/* Map src to window 0 and dst to window 1. */
- r = amdgpu_ttm_map_buffer(src->bo, src->mem, &src_mm,
+ r = amdgpu_ttm_map_buffer(entity,
+ src->bo, src->mem, &src_mm,
0, ring, tmz, &cur_size, &from);
if (r)
goto error;
- r = amdgpu_ttm_map_buffer(dst->bo, dst->mem, &dst_mm,
+ r = amdgpu_ttm_map_buffer(entity,
+ dst->bo, dst->mem, &dst_mm,
1, ring, tmz, &cur_size, &to);
if (r)
goto error;
@@ -353,7 +359,7 @@ static int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
write_compress_disable));
}
- r = amdgpu_copy_buffer(ring, from, to, cur_size, resv,
+ r = amdgpu_copy_buffer(ring, entity, from, to, cur_size, resv,
&next, true, copy_flags);
if (r)
goto error;
@@ -394,7 +400,9 @@ static int amdgpu_move_blit(struct ttm_buffer_object *bo,
src.offset = 0;
dst.offset = 0;
- r = amdgpu_ttm_copy_mem_to_mem(adev, &src, &dst,
+ r = amdgpu_ttm_copy_mem_to_mem(adev,
+ &adev->mman.move_entity.base,
+ &src, &dst,
new_mem->size,
amdgpu_bo_encrypted(abo),
bo->base.resv, &fence);
@@ -406,8 +414,9 @@ static int amdgpu_move_blit(struct ttm_buffer_object *bo,
(abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE)) {
struct dma_fence *wipe_fence = NULL;
- r = amdgpu_fill_buffer(abo, 0, NULL, &wipe_fence,
- false, AMDGPU_KERNEL_JOB_ID_MOVE_BLIT);
+ r = amdgpu_fill_buffer(&adev->mman.move_entity,
+ abo, 0, NULL, &wipe_fence,
+ AMDGPU_KERNEL_JOB_ID_MOVE_BLIT);
if (r) {
goto error;
} else if (wipe_fence) {
@@ -2223,16 +2232,15 @@ void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable)
}
static int amdgpu_ttm_prepare_job(struct amdgpu_device *adev,
+ struct drm_sched_entity *entity,
unsigned int num_dw,
struct dma_resv *resv,
bool vm_needs_flush,
struct amdgpu_job **job,
- bool delayed, u64 k_job_id)
+ u64 k_job_id)
{
enum amdgpu_ib_pool_type pool = AMDGPU_IB_POOL_DELAYED;
int r;
- struct drm_sched_entity *entity = delayed ? &adev->mman.clear_entity.base :
- &adev->mman.move_entity.base;
r = amdgpu_job_alloc_with_ib(adev, entity,
AMDGPU_FENCE_OWNER_UNDEFINED,
num_dw * 4, pool, job, k_job_id);
@@ -2252,7 +2260,9 @@ static int amdgpu_ttm_prepare_job(struct amdgpu_device *adev,
DMA_RESV_USAGE_BOOKKEEP);
}
-int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
+int amdgpu_copy_buffer(struct amdgpu_ring *ring,
+ struct drm_sched_entity *entity,
+ uint64_t src_offset,
uint64_t dst_offset, uint32_t byte_count,
struct dma_resv *resv,
struct dma_fence **fence,
@@ -2274,8 +2284,8 @@ int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
max_bytes = adev->mman.buffer_funcs->copy_max_bytes;
num_loops = DIV_ROUND_UP(byte_count, max_bytes);
num_dw = ALIGN(num_loops * adev->mman.buffer_funcs->copy_num_dw, 8);
- r = amdgpu_ttm_prepare_job(adev, num_dw,
- resv, vm_needs_flush, &job, false,
+ r = amdgpu_ttm_prepare_job(adev, entity, num_dw,
+ resv, vm_needs_flush, &job,
AMDGPU_KERNEL_JOB_ID_TTM_COPY_BUFFER);
if (r)
return r;
@@ -2304,11 +2314,13 @@ int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
return r;
}
-static int amdgpu_ttm_fill_mem(struct amdgpu_ring *ring, uint32_t src_data,
+static int amdgpu_ttm_fill_mem(struct amdgpu_ring *ring,
+ struct drm_sched_entity *entity,
+ uint32_t src_data,
uint64_t dst_addr, uint32_t byte_count,
struct dma_resv *resv,
struct dma_fence **fence,
- bool vm_needs_flush, bool delayed,
+ bool vm_needs_flush,
u64 k_job_id)
{
struct amdgpu_device *adev = ring->adev;
@@ -2321,8 +2333,8 @@ static int amdgpu_ttm_fill_mem(struct amdgpu_ring *ring, uint32_t src_data,
max_bytes = adev->mman.buffer_funcs->fill_max_bytes;
num_loops = DIV_ROUND_UP_ULL(byte_count, max_bytes);
num_dw = ALIGN(num_loops * adev->mman.buffer_funcs->fill_num_dw, 8);
- r = amdgpu_ttm_prepare_job(adev, num_dw, resv, vm_needs_flush,
- &job, delayed, k_job_id);
+ r = amdgpu_ttm_prepare_job(adev, entity, num_dw, resv,
+ vm_needs_flush, &job, k_job_id);
if (r)
return r;
@@ -2386,13 +2398,14 @@ int amdgpu_ttm_clear_buffer(struct amdgpu_bo *bo,
/* Never clear more than 256MiB at once to avoid timeouts */
size = min(cursor.size, 256ULL << 20);
- r = amdgpu_ttm_map_buffer(&bo->tbo, bo->tbo.resource, &cursor,
+ r = amdgpu_ttm_map_buffer(&adev->mman.clear_entity.base,
+ &bo->tbo, bo->tbo.resource, &cursor,
1, ring, false, &size, &addr);
if (r)
goto err;
- r = amdgpu_ttm_fill_mem(ring, 0, addr, size, resv,
- &next, true, true,
+ r = amdgpu_ttm_fill_mem(ring, &adev->mman.clear_entity.base, 0, addr, size, resv,
+ &next, true,
AMDGPU_KERNEL_JOB_ID_TTM_CLEAR_BUFFER);
if (r)
goto err;
@@ -2408,12 +2421,12 @@ int amdgpu_ttm_clear_buffer(struct amdgpu_bo *bo,
return r;
}
-int amdgpu_fill_buffer(struct amdgpu_bo *bo,
- uint32_t src_data,
- struct dma_resv *resv,
- struct dma_fence **f,
- bool delayed,
- u64 k_job_id)
+int amdgpu_fill_buffer(struct amdgpu_ttm_entity *entity,
+ struct amdgpu_bo *bo,
+ uint32_t src_data,
+ struct dma_resv *resv,
+ struct dma_fence **f,
+ u64 k_job_id)
{
struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
@@ -2437,13 +2450,15 @@ int amdgpu_fill_buffer(struct amdgpu_bo *bo,
/* Never fill more than 256MiB at once to avoid timeouts */
cur_size = min(dst.size, 256ULL << 20);
- r = amdgpu_ttm_map_buffer(&bo->tbo, bo->tbo.resource, &dst,
+ r = amdgpu_ttm_map_buffer(&entity->base,
+ &bo->tbo, bo->tbo.resource, &dst,
1, ring, false, &cur_size, &to);
if (r)
goto error;
- r = amdgpu_ttm_fill_mem(ring, src_data, to, cur_size, resv,
- &next, true, delayed, k_job_id);
+ r = amdgpu_ttm_fill_mem(ring, &entity->base,
+ src_data, to, cur_size, resv,
+ &next, true, k_job_id);
if (r)
goto error;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
index f83313bc0afb..a3be0e06e1e7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
@@ -167,7 +167,9 @@ int amdgpu_ttm_init(struct amdgpu_device *adev);
void amdgpu_ttm_fini(struct amdgpu_device *adev);
void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev,
bool enable);
-int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
+int amdgpu_copy_buffer(struct amdgpu_ring *ring,
+ struct drm_sched_entity *entity,
+ uint64_t src_offset,
uint64_t dst_offset, uint32_t byte_count,
struct dma_resv *resv,
struct dma_fence **fence,
@@ -175,12 +177,12 @@ int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
int amdgpu_ttm_clear_buffer(struct amdgpu_bo *bo,
struct dma_resv *resv,
struct dma_fence **fence);
-int amdgpu_fill_buffer(struct amdgpu_bo *bo,
- uint32_t src_data,
- struct dma_resv *resv,
- struct dma_fence **fence,
- bool delayed,
- u64 k_job_id);
+int amdgpu_fill_buffer(struct amdgpu_ttm_entity *entity,
+ struct amdgpu_bo *bo,
+ uint32_t src_data,
+ struct dma_resv *resv,
+ struct dma_fence **f,
+ u64 k_job_id);
int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo);
void amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo);
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
index 1d35a89999f7..dfcba2c4580d 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
@@ -157,7 +157,8 @@ svm_migrate_copy_memory_gart(struct amdgpu_device *adev, dma_addr_t *sys,
goto out_unlock;
}
- r = amdgpu_copy_buffer(ring, gart_s, gart_d, size * PAGE_SIZE,
+ r = amdgpu_copy_buffer(ring, &entity->base,
+ gart_s, gart_d, size * PAGE_SIZE,
NULL, &next, true, 0);
if (r) {
dev_err(adev->dev, "fail %d to copy memory\n", r);
--
2.43.0
^ permalink raw reply [flat|nested] 40+ messages in thread* [PATCH v1 06/20] drm/amdgpu: statically assign gart windows to ttm entities
2025-11-04 8:35 [PATCH v1 00/20] drm/amdgpu: use all SDMA instances for TTM clears and moves Pierre-Eric Pelloux-Prayer
` (4 preceding siblings ...)
2025-11-04 8:35 ` [PATCH v1 05/20] drm/amdgpu: pass the entity to use to ttm functions Pierre-Eric Pelloux-Prayer
@ 2025-11-04 8:35 ` Pierre-Eric Pelloux-Prayer
2025-11-04 8:35 ` [PATCH v1 07/20] drm/amdgpu: allocate multiple clear entities Pierre-Eric Pelloux-Prayer
` (13 subsequent siblings)
19 siblings, 0 replies; 40+ messages in thread
From: Pierre-Eric Pelloux-Prayer @ 2025-11-04 8:35 UTC (permalink / raw)
To: Alex Deucher, Christian König, David Airlie, Simona Vetter,
Felix Kuehling
Cc: Pierre-Eric Pelloux-Prayer, amd-gfx, dri-devel, linux-kernel
If multiple entities share the same window we must make sure
that jobs using them are executed sequentially.
This commit gives separate window id to each entity, so jobs
from multiple entities could execute in parallel if needed.
(for now they all use the first sdma engine, so it makes no
difference yet).
default_entity doesn't get any windows reserved since there is
no use for them.
Signed-off-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 9 +++--
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 48 ++++++++++++++----------
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 7 +++-
drivers/gpu/drm/amd/amdkfd/kfd_migrate.c | 8 ++--
4 files changed, 44 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
index 8e2d41c9c271..2a444d02cf4b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
@@ -686,7 +686,8 @@ void amdgpu_gmc_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
* translation. Avoid this by doing the invalidation from the SDMA
* itself at least for GART.
*/
- mutex_lock(&adev->mman.gtt_window_lock);
+ mutex_lock(&adev->mman.clear_entity.gart_window_lock);
+ mutex_lock(&adev->mman.move_entity.gart_window_lock);
r = amdgpu_job_alloc_with_ib(ring->adev, &adev->mman.default_entity.base,
AMDGPU_FENCE_OWNER_UNDEFINED,
16 * 4, AMDGPU_IB_POOL_IMMEDIATE,
@@ -699,7 +700,8 @@ void amdgpu_gmc_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
job->ibs->ptr[job->ibs->length_dw++] = ring->funcs->nop;
amdgpu_ring_pad_ib(ring, &job->ibs[0]);
fence = amdgpu_job_submit(job);
- mutex_unlock(&adev->mman.gtt_window_lock);
+ mutex_unlock(&adev->mman.move_entity.gart_window_lock);
+ mutex_unlock(&adev->mman.clear_entity.gart_window_lock);
dma_fence_wait(fence, false);
dma_fence_put(fence);
@@ -707,7 +709,8 @@ void amdgpu_gmc_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
return;
error_alloc:
- mutex_unlock(&adev->mman.gtt_window_lock);
+ mutex_unlock(&adev->mman.move_entity.gart_window_lock);
+ mutex_unlock(&adev->mman.clear_entity.gart_window_lock);
dev_err(adev->dev, "Error flushing GPU TLB using the SDMA (%d)!\n", r);
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index bd35bea4b573..3a77eea8869d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -291,7 +291,7 @@ static int amdgpu_ttm_map_buffer(struct drm_sched_entity *entity,
*/
__attribute__((nonnull))
static int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
- struct drm_sched_entity *entity,
+ struct amdgpu_ttm_entity *entity,
const struct amdgpu_copy_mem *src,
const struct amdgpu_copy_mem *dst,
uint64_t size, bool tmz,
@@ -314,7 +314,7 @@ static int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
amdgpu_res_first(src->mem, src->offset, size, &src_mm);
amdgpu_res_first(dst->mem, dst->offset, size, &dst_mm);
- mutex_lock(&adev->mman.gtt_window_lock);
+ mutex_lock(&entity->gart_window_lock);
while (src_mm.remaining) {
uint64_t from, to, cur_size, tiling_flags;
uint32_t num_type, data_format, max_com, write_compress_disable;
@@ -324,15 +324,15 @@ static int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
cur_size = min3(src_mm.size, dst_mm.size, 256ULL << 20);
/* Map src to window 0 and dst to window 1. */
- r = amdgpu_ttm_map_buffer(entity,
+ r = amdgpu_ttm_map_buffer(&entity->base,
src->bo, src->mem, &src_mm,
- 0, ring, tmz, &cur_size, &from);
+ entity->gart_window_id0, ring, tmz, &cur_size, &from);
if (r)
goto error;
- r = amdgpu_ttm_map_buffer(entity,
+ r = amdgpu_ttm_map_buffer(&entity->base,
dst->bo, dst->mem, &dst_mm,
- 1, ring, tmz, &cur_size, &to);
+ entity->gart_window_id1, ring, tmz, &cur_size, &to);
if (r)
goto error;
@@ -359,7 +359,7 @@ static int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
write_compress_disable));
}
- r = amdgpu_copy_buffer(ring, entity, from, to, cur_size, resv,
+ r = amdgpu_copy_buffer(ring, &entity->base, from, to, cur_size, resv,
&next, true, copy_flags);
if (r)
goto error;
@@ -371,7 +371,7 @@ static int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
amdgpu_res_next(&dst_mm, cur_size);
}
error:
- mutex_unlock(&adev->mman.gtt_window_lock);
+ mutex_unlock(&entity->gart_window_lock);
*f = fence;
return r;
}
@@ -401,7 +401,7 @@ static int amdgpu_move_blit(struct ttm_buffer_object *bo,
dst.offset = 0;
r = amdgpu_ttm_copy_mem_to_mem(adev,
- &adev->mman.move_entity.base,
+ &adev->mman.move_entity,
&src, &dst,
new_mem->size,
amdgpu_bo_encrypted(abo),
@@ -1893,8 +1893,6 @@ int amdgpu_ttm_init(struct amdgpu_device *adev)
uint64_t gtt_size;
int r;
- mutex_init(&adev->mman.gtt_window_lock);
-
dma_set_max_seg_size(adev->dev, UINT_MAX);
/* No others user of address space so set it to 0 */
r = ttm_device_init(&adev->mman.bdev, &amdgpu_bo_driver, adev->dev,
@@ -2207,6 +2205,15 @@ void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable)
drm_sched_entity_destroy(&adev->mman.clear_entity.base);
goto error_free_entity;
}
+
+ /* Statically assign GART windows to each entity. */
+ mutex_init(&adev->mman.default_entity.gart_window_lock);
+ adev->mman.move_entity.gart_window_id0 = 0;
+ adev->mman.move_entity.gart_window_id1 = 1;
+ mutex_init(&adev->mman.move_entity.gart_window_lock);
+ /* Clearing entity doesn't use id0 */
+ adev->mman.clear_entity.gart_window_id1 = 2;
+ mutex_init(&adev->mman.clear_entity.gart_window_lock);
} else {
drm_sched_entity_destroy(&adev->mman.default_entity.base);
drm_sched_entity_destroy(&adev->mman.clear_entity.base);
@@ -2371,6 +2378,7 @@ int amdgpu_ttm_clear_buffer(struct amdgpu_bo *bo,
{
struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
+ struct amdgpu_ttm_entity *entity;
struct amdgpu_res_cursor cursor;
u64 addr;
int r = 0;
@@ -2381,11 +2389,12 @@ int amdgpu_ttm_clear_buffer(struct amdgpu_bo *bo,
if (!fence)
return -EINVAL;
+ entity = &adev->mman.clear_entity;
*fence = dma_fence_get_stub();
amdgpu_res_first(bo->tbo.resource, 0, amdgpu_bo_size(bo), &cursor);
- mutex_lock(&adev->mman.gtt_window_lock);
+ mutex_lock(&entity->gart_window_lock);
while (cursor.remaining) {
struct dma_fence *next = NULL;
u64 size;
@@ -2398,13 +2407,13 @@ int amdgpu_ttm_clear_buffer(struct amdgpu_bo *bo,
/* Never clear more than 256MiB at once to avoid timeouts */
size = min(cursor.size, 256ULL << 20);
- r = amdgpu_ttm_map_buffer(&adev->mman.clear_entity.base,
+ r = amdgpu_ttm_map_buffer(&entity->base,
&bo->tbo, bo->tbo.resource, &cursor,
- 1, ring, false, &size, &addr);
+ entity->gart_window_id1, ring, false, &size, &addr);
if (r)
goto err;
- r = amdgpu_ttm_fill_mem(ring, &adev->mman.clear_entity.base, 0, addr, size, resv,
+ r = amdgpu_ttm_fill_mem(ring, &entity->base, 0, addr, size, resv,
&next, true,
AMDGPU_KERNEL_JOB_ID_TTM_CLEAR_BUFFER);
if (r)
@@ -2416,7 +2425,7 @@ int amdgpu_ttm_clear_buffer(struct amdgpu_bo *bo,
amdgpu_res_next(&cursor, size);
}
err:
- mutex_unlock(&adev->mman.gtt_window_lock);
+ mutex_unlock(&entity->gart_window_lock);
return r;
}
@@ -2442,7 +2451,7 @@ int amdgpu_fill_buffer(struct amdgpu_ttm_entity *entity,
amdgpu_res_first(bo->tbo.resource, 0, amdgpu_bo_size(bo), &dst);
- mutex_lock(&adev->mman.gtt_window_lock);
+ mutex_lock(&entity->gart_window_lock);
while (dst.remaining) {
struct dma_fence *next;
uint64_t cur_size, to;
@@ -2452,7 +2461,8 @@ int amdgpu_fill_buffer(struct amdgpu_ttm_entity *entity,
r = amdgpu_ttm_map_buffer(&entity->base,
&bo->tbo, bo->tbo.resource, &dst,
- 1, ring, false, &cur_size, &to);
+ entity->gart_window_id1, ring, false,
+ &cur_size, &to);
if (r)
goto error;
@@ -2468,7 +2478,7 @@ int amdgpu_fill_buffer(struct amdgpu_ttm_entity *entity,
amdgpu_res_next(&dst, cur_size);
}
error:
- mutex_unlock(&adev->mman.gtt_window_lock);
+ mutex_unlock(&entity->gart_window_lock);
if (f)
*f = dma_fence_get(fence);
dma_fence_put(fence);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
index a3be0e06e1e7..8b7a56737479 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
@@ -39,7 +39,7 @@
#define __AMDGPU_PL_NUM (TTM_PL_PRIV + 6)
#define AMDGPU_GTT_MAX_TRANSFER_SIZE 512
-#define AMDGPU_GTT_NUM_TRANSFER_WINDOWS 2
+#define AMDGPU_GTT_NUM_TRANSFER_WINDOWS 3
extern const struct attribute_group amdgpu_vram_mgr_attr_group;
extern const struct attribute_group amdgpu_gtt_mgr_attr_group;
@@ -54,6 +54,9 @@ struct amdgpu_gtt_mgr {
struct amdgpu_ttm_entity {
struct drm_sched_entity base;
+ struct mutex gart_window_lock;
+ u32 gart_window_id0;
+ u32 gart_window_id1;
};
struct amdgpu_mman {
@@ -69,7 +72,7 @@ struct amdgpu_mman {
struct mutex gtt_window_lock;
- struct amdgpu_ttm_entity default_entity;
+ struct amdgpu_ttm_entity default_entity; /* has no gart windows */
struct amdgpu_ttm_entity clear_entity;
struct amdgpu_ttm_entity move_entity;
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
index dfcba2c4580d..7aade289f32a 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
@@ -60,7 +60,7 @@ svm_migrate_gart_map(struct amdgpu_ring *ring,
int r;
/* use gart window 0 */
- *gart_addr = adev->gmc.gart_start;
+ *gart_addr = entity->gart_window_id0;
num_dw = ALIGN(adev->mman.buffer_funcs->copy_num_dw, 8);
num_bytes = npages * 8;
@@ -116,7 +116,7 @@ svm_migrate_gart_map(struct amdgpu_ring *ring,
* multiple GTT_MAX_PAGES transfer, all sdma operations are serialized, wait for
* the last sdma finish fence which is returned to check copy memory is done.
*
- * Context: Process context, takes and releases gtt_window_lock
+ * Context: Process context, takes and releases gart_window_lock
*
* Return:
* 0 - OK, otherwise error code
@@ -138,7 +138,7 @@ svm_migrate_copy_memory_gart(struct amdgpu_device *adev, dma_addr_t *sys,
entity = &adev->mman.move_entity;
- mutex_lock(&adev->mman.gtt_window_lock);
+ mutex_lock(&entity->gart_window_lock);
while (npages) {
size = min(GTT_MAX_PAGES, npages);
@@ -175,7 +175,7 @@ svm_migrate_copy_memory_gart(struct amdgpu_device *adev, dma_addr_t *sys,
}
out_unlock:
- mutex_unlock(&adev->mman.gtt_window_lock);
+ mutex_unlock(&entity->gart_window_lock);
return r;
}
--
2.43.0
^ permalink raw reply [flat|nested] 40+ messages in thread* [PATCH v1 07/20] drm/amdgpu: allocate multiple clear entities
2025-11-04 8:35 [PATCH v1 00/20] drm/amdgpu: use all SDMA instances for TTM clears and moves Pierre-Eric Pelloux-Prayer
` (5 preceding siblings ...)
2025-11-04 8:35 ` [PATCH v1 06/20] drm/amdgpu: statically assign gart windows to ttm entities Pierre-Eric Pelloux-Prayer
@ 2025-11-04 8:35 ` Pierre-Eric Pelloux-Prayer
2025-11-04 8:35 ` [PATCH v1 08/20] drm/amdgpu: allocate multiple move entities Pierre-Eric Pelloux-Prayer
` (12 subsequent siblings)
19 siblings, 0 replies; 40+ messages in thread
From: Pierre-Eric Pelloux-Prayer @ 2025-11-04 8:35 UTC (permalink / raw)
To: Alex Deucher, Christian König, David Airlie, Simona Vetter
Cc: Pierre-Eric Pelloux-Prayer, amd-gfx, dri-devel, linux-kernel
No functional change for now, as we always use entity 0.
Signed-off-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 11 +--
drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c | 6 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 76 +++++++++++++--------
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 10 +--
5 files changed, 66 insertions(+), 39 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
index 2a444d02cf4b..e73dcfed5338 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
@@ -655,7 +655,7 @@ void amdgpu_gmc_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
struct amdgpu_vmhub *hub = &adev->vmhub[vmhub];
struct dma_fence *fence;
struct amdgpu_job *job;
- int r;
+ int r, i;
if (!hub->sdma_invalidation_workaround || vmid ||
!adev->mman.buffer_funcs_enabled || !adev->ib_pool_ready ||
@@ -686,8 +686,9 @@ void amdgpu_gmc_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
* translation. Avoid this by doing the invalidation from the SDMA
* itself at least for GART.
*/
- mutex_lock(&adev->mman.clear_entity.gart_window_lock);
mutex_lock(&adev->mman.move_entity.gart_window_lock);
+ for (i = 0; i < adev->mman.num_clear_entities; i++)
+ mutex_lock(&adev->mman.clear_entities[i].gart_window_lock);
r = amdgpu_job_alloc_with_ib(ring->adev, &adev->mman.default_entity.base,
AMDGPU_FENCE_OWNER_UNDEFINED,
16 * 4, AMDGPU_IB_POOL_IMMEDIATE,
@@ -701,7 +702,8 @@ void amdgpu_gmc_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
amdgpu_ring_pad_ib(ring, &job->ibs[0]);
fence = amdgpu_job_submit(job);
mutex_unlock(&adev->mman.move_entity.gart_window_lock);
- mutex_unlock(&adev->mman.clear_entity.gart_window_lock);
+ for (i = 0; i < adev->mman.num_clear_entities; i++)
+ mutex_unlock(&adev->mman.clear_entities[i].gart_window_lock);
dma_fence_wait(fence, false);
dma_fence_put(fence);
@@ -710,7 +712,8 @@ void amdgpu_gmc_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
error_alloc:
mutex_unlock(&adev->mman.move_entity.gart_window_lock);
- mutex_unlock(&adev->mman.clear_entity.gart_window_lock);
+ for (i = 0; i < adev->mman.num_clear_entities; i++)
+ mutex_unlock(&adev->mman.clear_entities[i].gart_window_lock);
dev_err(adev->dev, "Error flushing GPU TLB using the SDMA (%d)!\n", r);
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
index 0760e70402ec..3771e89035f5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
@@ -269,10 +269,12 @@ static const struct ttm_resource_manager_func amdgpu_gtt_mgr_func = {
*
* @adev: amdgpu_device pointer
* @gtt_size: maximum size of GTT
+ * @reserved_windows: num of already used windows
*
* Allocate and initialize the GTT manager.
*/
-int amdgpu_gtt_mgr_init(struct amdgpu_device *adev, uint64_t gtt_size)
+int amdgpu_gtt_mgr_init(struct amdgpu_device *adev, uint64_t gtt_size,
+ u32 reserved_windows)
{
struct amdgpu_gtt_mgr *mgr = &adev->mman.gtt_mgr;
struct ttm_resource_manager *man = &mgr->manager;
@@ -283,7 +285,7 @@ int amdgpu_gtt_mgr_init(struct amdgpu_device *adev, uint64_t gtt_size)
ttm_resource_manager_init(man, &adev->mman.bdev, gtt_size);
- start = AMDGPU_GTT_MAX_TRANSFER_SIZE * AMDGPU_GTT_NUM_TRANSFER_WINDOWS;
+ start = AMDGPU_GTT_MAX_TRANSFER_SIZE * reserved_windows;
size = (adev->gmc.gart_size >> PAGE_SHIFT) - start;
drm_mm_init(&mgr->mm, start, size);
spin_lock_init(&mgr->lock);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index c06c132a753c..e7b2cae031b3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -1321,7 +1321,7 @@ void amdgpu_bo_release_notify(struct ttm_buffer_object *bo)
if (r)
goto out;
- r = amdgpu_fill_buffer(&adev->mman.clear_entity, abo, 0, &bo->base._resv,
+ r = amdgpu_fill_buffer(&adev->mman.clear_entities[0], abo, 0, &bo->base._resv,
&fence, AMDGPU_KERNEL_JOB_ID_CLEAR_ON_RELEASE);
if (WARN_ON(r))
goto out;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 3a77eea8869d..e0e469b73013 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -1891,6 +1891,7 @@ static void amdgpu_ttm_mmio_remap_bo_fini(struct amdgpu_device *adev)
int amdgpu_ttm_init(struct amdgpu_device *adev)
{
uint64_t gtt_size;
+ u32 gart_window;
int r;
dma_set_max_seg_size(adev->dev, UINT_MAX);
@@ -1923,7 +1924,7 @@ int amdgpu_ttm_init(struct amdgpu_device *adev)
}
/* Change the size here instead of the init above so only lpfn is affected */
- amdgpu_ttm_set_buffer_funcs_status(adev, false);
+ gart_window = amdgpu_ttm_set_buffer_funcs_status(adev, false);
#ifdef CONFIG_64BIT
#ifdef CONFIG_X86
if (adev->gmc.xgmi.connected_to_cpu)
@@ -2019,7 +2020,7 @@ int amdgpu_ttm_init(struct amdgpu_device *adev)
}
/* Initialize GTT memory pool */
- r = amdgpu_gtt_mgr_init(adev, gtt_size);
+ r = amdgpu_gtt_mgr_init(adev, gtt_size, gart_window);
if (r) {
dev_err(adev->dev, "Failed initializing GTT heap.\n");
return r;
@@ -2158,16 +2159,22 @@ void amdgpu_ttm_fini(struct amdgpu_device *adev)
*
* Enable/disable use of buffer functions during suspend/resume. This should
* only be called at bootup or when userspace isn't running.
+ *
+ * Returns: the number of GART reserved window
*/
-void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable)
+u32 amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable)
{
struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM);
uint64_t size;
- int r, i;
+ int r, i, j;
+ u32 num_clear_entities, windows, w;
+
+ num_clear_entities = adev->sdma.num_instances;
+ windows = adev->gmc.is_app_apu ? 0 : (2 + num_clear_entities);
if (!adev->mman.initialized || amdgpu_in_reset(adev) ||
adev->mman.buffer_funcs_enabled == enable || adev->gmc.is_app_apu)
- return;
+ return windows;
if (enable) {
struct amdgpu_ring *ring;
@@ -2180,19 +2187,9 @@ void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable)
1, NULL);
if (r) {
dev_err(adev->dev,
- "Failed setting up TTM BO move entity (%d)\n",
+ "Failed setting up TTM BO eviction entity (%d)\n",
r);
- return;
- }
-
- r = drm_sched_entity_init(&adev->mman.clear_entity.base,
- DRM_SCHED_PRIORITY_NORMAL, &sched,
- 1, NULL);
- if (r) {
- dev_err(adev->dev,
- "Failed setting up TTM BO clear entity (%d)\n",
- r);
- goto error_free_entity;
+ return 0;
}
r = drm_sched_entity_init(&adev->mman.move_entity.base,
@@ -2202,26 +2199,51 @@ void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable)
dev_err(adev->dev,
"Failed setting up TTM BO move entity (%d)\n",
r);
- drm_sched_entity_destroy(&adev->mman.clear_entity.base);
goto error_free_entity;
}
+ adev->mman.num_clear_entities = num_clear_entities;
+ adev->mman.clear_entities = kcalloc(num_clear_entities,
+ sizeof(struct amdgpu_ttm_entity),
+ GFP_KERNEL);
+ if (!adev->mman.clear_entities)
+ goto error_free_entity;
+
+ for (i = 0; i < num_clear_entities; i++) {
+ r = drm_sched_entity_init(&adev->mman.clear_entities[i].base,
+ DRM_SCHED_PRIORITY_NORMAL, &sched,
+ 1, NULL);
+ if (r) {
+ for (j = 0; j < i; j++)
+ drm_sched_entity_destroy(
+ &adev->mman.clear_entities[j].base);
+ kfree(adev->mman.clear_entities);
+ goto error_free_entity;
+ }
+ }
+
/* Statically assign GART windows to each entity. */
+ w = 0;
mutex_init(&adev->mman.default_entity.gart_window_lock);
- adev->mman.move_entity.gart_window_id0 = 0;
- adev->mman.move_entity.gart_window_id1 = 1;
+ adev->mman.move_entity.gart_window_id0 = w++;
+ adev->mman.move_entity.gart_window_id1 = w++;
mutex_init(&adev->mman.move_entity.gart_window_lock);
- /* Clearing entity doesn't use id0 */
- adev->mman.clear_entity.gart_window_id1 = 2;
- mutex_init(&adev->mman.clear_entity.gart_window_lock);
+ for (i = 0; i < num_clear_entities; i++) {
+ /* Clearing entities don't use id0 */
+ adev->mman.clear_entities[i].gart_window_id1 = w++;
+ mutex_init(&adev->mman.clear_entities[i].gart_window_lock);
+ }
+ WARN_ON(w != windows);
} else {
drm_sched_entity_destroy(&adev->mman.default_entity.base);
- drm_sched_entity_destroy(&adev->mman.clear_entity.base);
drm_sched_entity_destroy(&adev->mman.move_entity.base);
+ for (i = 0; i < num_clear_entities; i++)
+ drm_sched_entity_destroy(&adev->mman.clear_entities[i].base);
for (i = 0; i < TTM_FENCES_MAX_SLOT_COUNT; i++) {
dma_fence_put(man->pipelined_eviction.fences[i]);
man->pipelined_eviction.fences[i] = NULL;
}
+ kfree(adev->mman.clear_entities);
}
/* this just adjusts TTM size idea, which sets lpfn to the correct value */
@@ -2232,10 +2254,11 @@ void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable)
man->size = size;
adev->mman.buffer_funcs_enabled = enable;
- return;
+ return windows;
error_free_entity:
drm_sched_entity_destroy(&adev->mman.default_entity.base);
+ return 0;
}
static int amdgpu_ttm_prepare_job(struct amdgpu_device *adev,
@@ -2388,8 +2411,7 @@ int amdgpu_ttm_clear_buffer(struct amdgpu_bo *bo,
if (!fence)
return -EINVAL;
-
- entity = &adev->mman.clear_entity;
+ entity = &adev->mman.clear_entities[0];
*fence = dma_fence_get_stub();
amdgpu_res_first(bo->tbo.resource, 0, amdgpu_bo_size(bo), &cursor);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
index 8b7a56737479..e7ada4605472 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
@@ -39,7 +39,6 @@
#define __AMDGPU_PL_NUM (TTM_PL_PRIV + 6)
#define AMDGPU_GTT_MAX_TRANSFER_SIZE 512
-#define AMDGPU_GTT_NUM_TRANSFER_WINDOWS 3
extern const struct attribute_group amdgpu_vram_mgr_attr_group;
extern const struct attribute_group amdgpu_gtt_mgr_attr_group;
@@ -73,8 +72,9 @@ struct amdgpu_mman {
struct mutex gtt_window_lock;
struct amdgpu_ttm_entity default_entity; /* has no gart windows */
- struct amdgpu_ttm_entity clear_entity;
struct amdgpu_ttm_entity move_entity;
+ struct amdgpu_ttm_entity *clear_entities;
+ u32 num_clear_entities;
struct amdgpu_vram_mgr vram_mgr;
struct amdgpu_gtt_mgr gtt_mgr;
@@ -134,7 +134,7 @@ struct amdgpu_copy_mem {
#define AMDGPU_COPY_FLAGS_GET(value, field) \
(((__u32)(value) >> AMDGPU_COPY_FLAGS_##field##_SHIFT) & AMDGPU_COPY_FLAGS_##field##_MASK)
-int amdgpu_gtt_mgr_init(struct amdgpu_device *adev, uint64_t gtt_size);
+int amdgpu_gtt_mgr_init(struct amdgpu_device *adev, uint64_t gtt_size, u32 reserved_windows);
void amdgpu_gtt_mgr_fini(struct amdgpu_device *adev);
int amdgpu_preempt_mgr_init(struct amdgpu_device *adev);
void amdgpu_preempt_mgr_fini(struct amdgpu_device *adev);
@@ -168,8 +168,8 @@ bool amdgpu_res_cpu_visible(struct amdgpu_device *adev,
int amdgpu_ttm_init(struct amdgpu_device *adev);
void amdgpu_ttm_fini(struct amdgpu_device *adev);
-void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev,
- bool enable);
+u32 amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev,
+ bool enable);
int amdgpu_copy_buffer(struct amdgpu_ring *ring,
struct drm_sched_entity *entity,
uint64_t src_offset,
--
2.43.0
^ permalink raw reply [flat|nested] 40+ messages in thread* [PATCH v1 08/20] drm/amdgpu: allocate multiple move entities
2025-11-04 8:35 [PATCH v1 00/20] drm/amdgpu: use all SDMA instances for TTM clears and moves Pierre-Eric Pelloux-Prayer
` (6 preceding siblings ...)
2025-11-04 8:35 ` [PATCH v1 07/20] drm/amdgpu: allocate multiple clear entities Pierre-Eric Pelloux-Prayer
@ 2025-11-04 8:35 ` Pierre-Eric Pelloux-Prayer
2025-11-04 8:35 ` [PATCH v1 09/20] drm/amdgpu: pass optional dependency to amdgpu_fill_buffer Pierre-Eric Pelloux-Prayer
` (11 subsequent siblings)
19 siblings, 0 replies; 40+ messages in thread
From: Pierre-Eric Pelloux-Prayer @ 2025-11-04 8:35 UTC (permalink / raw)
To: Alex Deucher, Christian König, David Airlie, Simona Vetter,
Felix Kuehling
Cc: Pierre-Eric Pelloux-Prayer, amd-gfx, dri-devel, linux-kernel
No functional change for now, as we always use entity 0.
Signed-off-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 9 +++--
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 48 +++++++++++++++---------
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 3 +-
drivers/gpu/drm/amd/amdkfd/kfd_migrate.c | 2 +-
4 files changed, 39 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
index e73dcfed5338..2713dd51ab9a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
@@ -686,9 +686,10 @@ void amdgpu_gmc_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
* translation. Avoid this by doing the invalidation from the SDMA
* itself at least for GART.
*/
- mutex_lock(&adev->mman.move_entity.gart_window_lock);
for (i = 0; i < adev->mman.num_clear_entities; i++)
mutex_lock(&adev->mman.clear_entities[i].gart_window_lock);
+ for (i = 0; i < adev->mman.num_move_entities; i++)
+ mutex_lock(&adev->mman.move_entities[i].gart_window_lock);
r = amdgpu_job_alloc_with_ib(ring->adev, &adev->mman.default_entity.base,
AMDGPU_FENCE_OWNER_UNDEFINED,
16 * 4, AMDGPU_IB_POOL_IMMEDIATE,
@@ -701,7 +702,8 @@ void amdgpu_gmc_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
job->ibs->ptr[job->ibs->length_dw++] = ring->funcs->nop;
amdgpu_ring_pad_ib(ring, &job->ibs[0]);
fence = amdgpu_job_submit(job);
- mutex_unlock(&adev->mman.move_entity.gart_window_lock);
+ for (i = 0; i < adev->mman.num_move_entities; i++)
+ mutex_unlock(&adev->mman.move_entities[i].gart_window_lock);
for (i = 0; i < adev->mman.num_clear_entities; i++)
mutex_unlock(&adev->mman.clear_entities[i].gart_window_lock);
@@ -711,7 +713,8 @@ void amdgpu_gmc_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
return;
error_alloc:
- mutex_unlock(&adev->mman.move_entity.gart_window_lock);
+ for (i = 0; i < adev->mman.num_move_entities; i++)
+ mutex_unlock(&adev->mman.move_entities[i].gart_window_lock);
for (i = 0; i < adev->mman.num_clear_entities; i++)
mutex_unlock(&adev->mman.clear_entities[i].gart_window_lock);
dev_err(adev->dev, "Error flushing GPU TLB using the SDMA (%d)!\n", r);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index e0e469b73013..1b3945513157 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -401,7 +401,7 @@ static int amdgpu_move_blit(struct ttm_buffer_object *bo,
dst.offset = 0;
r = amdgpu_ttm_copy_mem_to_mem(adev,
- &adev->mman.move_entity,
+ &adev->mman.move_entities[0],
&src, &dst,
new_mem->size,
amdgpu_bo_encrypted(abo),
@@ -414,7 +414,7 @@ static int amdgpu_move_blit(struct ttm_buffer_object *bo,
(abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE)) {
struct dma_fence *wipe_fence = NULL;
- r = amdgpu_fill_buffer(&adev->mman.move_entity,
+ r = amdgpu_fill_buffer(&adev->mman.move_entities[0],
abo, 0, NULL, &wipe_fence,
AMDGPU_KERNEL_JOB_ID_MOVE_BLIT);
if (r) {
@@ -2167,10 +2167,11 @@ u32 amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable)
struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM);
uint64_t size;
int r, i, j;
- u32 num_clear_entities, windows, w;
+ u32 num_clear_entities, num_move_entities, windows, w;
num_clear_entities = adev->sdma.num_instances;
- windows = adev->gmc.is_app_apu ? 0 : (2 + num_clear_entities);
+ num_move_entities = MIN(adev->sdma.num_instances, TTM_FENCES_MAX_SLOT_COUNT);
+ windows = adev->gmc.is_app_apu ? 0 : (2 * num_move_entities + num_clear_entities);
if (!adev->mman.initialized || amdgpu_in_reset(adev) ||
adev->mman.buffer_funcs_enabled == enable || adev->gmc.is_app_apu)
@@ -2186,20 +2187,25 @@ u32 amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable)
DRM_SCHED_PRIORITY_KERNEL, &sched,
1, NULL);
if (r) {
- dev_err(adev->dev,
- "Failed setting up TTM BO eviction entity (%d)\n",
+ dev_err(adev->dev, "Failed setting up entity (%d)\n",
r);
return 0;
}
- r = drm_sched_entity_init(&adev->mman.move_entity.base,
- DRM_SCHED_PRIORITY_NORMAL, &sched,
- 1, NULL);
- if (r) {
- dev_err(adev->dev,
- "Failed setting up TTM BO move entity (%d)\n",
- r);
- goto error_free_entity;
+ adev->mman.num_move_entities = num_move_entities;
+ for (i = 0; i < num_move_entities; i++) {
+ r = drm_sched_entity_init(&adev->mman.move_entities[i].base,
+ DRM_SCHED_PRIORITY_NORMAL, &sched,
+ 1, NULL);
+ if (r) {
+ dev_err(adev->dev,
+ "Failed setting up TTM BO move entities (%d)\n",
+ r);
+ for (j = 0; j < i; j++)
+ drm_sched_entity_destroy(
+ &adev->mman.move_entities[j].base);
+ goto error_free_entity;
+ }
}
adev->mman.num_clear_entities = num_clear_entities;
@@ -2214,6 +2220,9 @@ u32 amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable)
DRM_SCHED_PRIORITY_NORMAL, &sched,
1, NULL);
if (r) {
+ for (j = 0; j < num_move_entities; j++)
+ drm_sched_entity_destroy(
+ &adev->mman.move_entities[j].base);
for (j = 0; j < i; j++)
drm_sched_entity_destroy(
&adev->mman.clear_entities[j].base);
@@ -2225,9 +2234,11 @@ u32 amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable)
/* Statically assign GART windows to each entity. */
w = 0;
mutex_init(&adev->mman.default_entity.gart_window_lock);
- adev->mman.move_entity.gart_window_id0 = w++;
- adev->mman.move_entity.gart_window_id1 = w++;
- mutex_init(&adev->mman.move_entity.gart_window_lock);
+ for (i = 0; i < num_move_entities; i++) {
+ adev->mman.move_entities[i].gart_window_id0 = w++;
+ adev->mman.move_entities[i].gart_window_id1 = w++;
+ mutex_init(&adev->mman.move_entities[i].gart_window_lock);
+ }
for (i = 0; i < num_clear_entities; i++) {
/* Clearing entities don't use id0 */
adev->mman.clear_entities[i].gart_window_id1 = w++;
@@ -2236,7 +2247,8 @@ u32 amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable)
WARN_ON(w != windows);
} else {
drm_sched_entity_destroy(&adev->mman.default_entity.base);
- drm_sched_entity_destroy(&adev->mman.move_entity.base);
+ for (i = 0; i < num_move_entities; i++)
+ drm_sched_entity_destroy(&adev->mman.move_entities[i].base);
for (i = 0; i < num_clear_entities; i++)
drm_sched_entity_destroy(&adev->mman.clear_entities[i].base);
for (i = 0; i < TTM_FENCES_MAX_SLOT_COUNT; i++) {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
index e7ada4605472..2874f054e869 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
@@ -72,9 +72,10 @@ struct amdgpu_mman {
struct mutex gtt_window_lock;
struct amdgpu_ttm_entity default_entity; /* has no gart windows */
- struct amdgpu_ttm_entity move_entity;
struct amdgpu_ttm_entity *clear_entities;
u32 num_clear_entities;
+ struct amdgpu_ttm_entity move_entities[TTM_FENCES_MAX_SLOT_COUNT];
+ u32 num_move_entities;
struct amdgpu_vram_mgr vram_mgr;
struct amdgpu_gtt_mgr gtt_mgr;
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
index 7aade289f32a..5daacb816cf7 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
@@ -136,7 +136,7 @@ svm_migrate_copy_memory_gart(struct amdgpu_device *adev, dma_addr_t *sys,
u64 size;
int r;
- entity = &adev->mman.move_entity;
+ entity = &adev->mman.move_entities[0];
mutex_lock(&entity->gart_window_lock);
--
2.43.0
^ permalink raw reply [flat|nested] 40+ messages in thread* [PATCH v1 09/20] drm/amdgpu: pass optional dependency to amdgpu_fill_buffer
2025-11-04 8:35 [PATCH v1 00/20] drm/amdgpu: use all SDMA instances for TTM clears and moves Pierre-Eric Pelloux-Prayer
` (7 preceding siblings ...)
2025-11-04 8:35 ` [PATCH v1 08/20] drm/amdgpu: allocate multiple move entities Pierre-Eric Pelloux-Prayer
@ 2025-11-04 8:35 ` Pierre-Eric Pelloux-Prayer
2025-11-04 8:35 ` [PATCH v1 10/20] drm/amdgpu: prepare amdgpu_fill_buffer to use N entities Pierre-Eric Pelloux-Prayer
` (10 subsequent siblings)
19 siblings, 0 replies; 40+ messages in thread
From: Pierre-Eric Pelloux-Prayer @ 2025-11-04 8:35 UTC (permalink / raw)
To: Alex Deucher, Christian König, David Airlie, Simona Vetter,
Sumit Semwal
Cc: Pierre-Eric Pelloux-Prayer, amd-gfx, dri-devel, linux-kernel,
linux-media, linaro-mm-sig
In case the fill job depends on a previous fence, the caller can
now pass it to make sure the ordering of the jobs is correct.
Signed-off-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 22 ++++++++++++++++------
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 1 +
3 files changed, 18 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index e7b2cae031b3..be3532134e46 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -1322,7 +1322,7 @@ void amdgpu_bo_release_notify(struct ttm_buffer_object *bo)
goto out;
r = amdgpu_fill_buffer(&adev->mman.clear_entities[0], abo, 0, &bo->base._resv,
- &fence, AMDGPU_KERNEL_JOB_ID_CLEAR_ON_RELEASE);
+ &fence, NULL, AMDGPU_KERNEL_JOB_ID_CLEAR_ON_RELEASE);
if (WARN_ON(r))
goto out;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 1b3945513157..b94ac16c785b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -173,6 +173,7 @@ static void amdgpu_evict_flags(struct ttm_buffer_object *bo,
* @tmz: if we should setup a TMZ enabled mapping
* @size: in number of bytes to map, out number of bytes mapped
* @addr: resulting address inside the MC address space
+ * @dep: optional dependency
*
* Setup one of the GART windows to access a specific piece of memory or return
* the physical address for local memory.
@@ -182,7 +183,8 @@ static int amdgpu_ttm_map_buffer(struct drm_sched_entity *entity,
struct ttm_resource *mem,
struct amdgpu_res_cursor *mm_cur,
unsigned int window, struct amdgpu_ring *ring,
- bool tmz, uint64_t *size, uint64_t *addr)
+ bool tmz, uint64_t *size, uint64_t *addr,
+ struct dma_fence *dep)
{
struct amdgpu_device *adev = ring->adev;
unsigned int offset, num_pages, num_dw, num_bytes;
@@ -234,6 +236,9 @@ static int amdgpu_ttm_map_buffer(struct drm_sched_entity *entity,
if (r)
return r;
+ if (dep)
+ drm_sched_job_add_dependency(&job->base, dma_fence_get(dep));
+
src_addr = num_dw * 4;
src_addr += job->ibs[0].gpu_addr;
@@ -326,13 +331,15 @@ static int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
/* Map src to window 0 and dst to window 1. */
r = amdgpu_ttm_map_buffer(&entity->base,
src->bo, src->mem, &src_mm,
- entity->gart_window_id0, ring, tmz, &cur_size, &from);
+ entity->gart_window_id0, ring, tmz, &cur_size, &from,
+ NULL);
if (r)
goto error;
r = amdgpu_ttm_map_buffer(&entity->base,
dst->bo, dst->mem, &dst_mm,
- entity->gart_window_id1, ring, tmz, &cur_size, &to);
+ entity->gart_window_id1, ring, tmz, &cur_size, &to,
+ NULL);
if (r)
goto error;
@@ -415,7 +422,7 @@ static int amdgpu_move_blit(struct ttm_buffer_object *bo,
struct dma_fence *wipe_fence = NULL;
r = amdgpu_fill_buffer(&adev->mman.move_entities[0],
- abo, 0, NULL, &wipe_fence,
+ abo, 0, NULL, &wipe_fence, fence,
AMDGPU_KERNEL_JOB_ID_MOVE_BLIT);
if (r) {
goto error;
@@ -2443,7 +2450,8 @@ int amdgpu_ttm_clear_buffer(struct amdgpu_bo *bo,
r = amdgpu_ttm_map_buffer(&entity->base,
&bo->tbo, bo->tbo.resource, &cursor,
- entity->gart_window_id1, ring, false, &size, &addr);
+ entity->gart_window_id1, ring, false, &size, &addr,
+ NULL);
if (r)
goto err;
@@ -2469,6 +2477,7 @@ int amdgpu_fill_buffer(struct amdgpu_ttm_entity *entity,
uint32_t src_data,
struct dma_resv *resv,
struct dma_fence **f,
+ struct dma_fence *dependency,
u64 k_job_id)
{
struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
@@ -2496,7 +2505,8 @@ int amdgpu_fill_buffer(struct amdgpu_ttm_entity *entity,
r = amdgpu_ttm_map_buffer(&entity->base,
&bo->tbo, bo->tbo.resource, &dst,
entity->gart_window_id1, ring, false,
- &cur_size, &to);
+ &cur_size, &to,
+ dependency);
if (r)
goto error;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
index 2874f054e869..9dd2a76a5641 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
@@ -186,6 +186,7 @@ int amdgpu_fill_buffer(struct amdgpu_ttm_entity *entity,
uint32_t src_data,
struct dma_resv *resv,
struct dma_fence **f,
+ struct dma_fence *dependency,
u64 k_job_id);
int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo);
--
2.43.0
^ permalink raw reply [flat|nested] 40+ messages in thread* [PATCH v1 10/20] drm/amdgpu: prepare amdgpu_fill_buffer to use N entities
2025-11-04 8:35 [PATCH v1 00/20] drm/amdgpu: use all SDMA instances for TTM clears and moves Pierre-Eric Pelloux-Prayer
` (8 preceding siblings ...)
2025-11-04 8:35 ` [PATCH v1 09/20] drm/amdgpu: pass optional dependency to amdgpu_fill_buffer Pierre-Eric Pelloux-Prayer
@ 2025-11-04 8:35 ` Pierre-Eric Pelloux-Prayer
2025-11-04 8:35 ` [PATCH v1 11/20] drm/amdgpu: use multiple entities in amdgpu_fill_buffer Pierre-Eric Pelloux-Prayer
` (9 subsequent siblings)
19 siblings, 0 replies; 40+ messages in thread
From: Pierre-Eric Pelloux-Prayer @ 2025-11-04 8:35 UTC (permalink / raw)
To: Alex Deucher, Christian König, David Airlie, Simona Vetter,
Sumit Semwal
Cc: Pierre-Eric Pelloux-Prayer, amd-gfx, dri-devel, linux-kernel,
linux-media, linaro-mm-sig
We want to use multiple entities for clears to enable parallelism.
To achieve this, let amdgpu_fill_buffer select the entity to use
when it's possible by passing a NULL entity.
We can also simplify the signature and remove the resv param:
amdgpu_move_blit is the only caller that doesn't use it, and it's
also the only caller that needs to specify an entity.
Signed-off-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 11 +----
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 54 ++++++++++++++++++----
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 1 -
3 files changed, 47 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index be3532134e46..4a69324bb730 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -1287,7 +1287,6 @@ void amdgpu_bo_move_notify(struct ttm_buffer_object *bo,
void amdgpu_bo_release_notify(struct ttm_buffer_object *bo)
{
struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
- struct dma_fence *fence = NULL;
struct amdgpu_bo *abo;
int r;
@@ -1317,18 +1316,12 @@ void amdgpu_bo_release_notify(struct ttm_buffer_object *bo)
adev->in_suspend || drm_dev_is_unplugged(adev_to_drm(adev)))
goto out;
- r = dma_resv_reserve_fences(&bo->base._resv, 1);
- if (r)
- goto out;
-
- r = amdgpu_fill_buffer(&adev->mman.clear_entities[0], abo, 0, &bo->base._resv,
- &fence, NULL, AMDGPU_KERNEL_JOB_ID_CLEAR_ON_RELEASE);
+ r = amdgpu_fill_buffer(NULL, abo, 0, NULL,
+ NULL, AMDGPU_KERNEL_JOB_ID_CLEAR_ON_RELEASE);
if (WARN_ON(r))
goto out;
amdgpu_vram_mgr_set_cleared(bo->resource);
- dma_resv_add_fence(&bo->base._resv, fence, DMA_RESV_USAGE_KERNEL);
- dma_fence_put(fence);
out:
dma_resv_unlock(&bo->base._resv);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index b94ac16c785b..c357a6d9763a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -184,7 +184,8 @@ static int amdgpu_ttm_map_buffer(struct drm_sched_entity *entity,
struct amdgpu_res_cursor *mm_cur,
unsigned int window, struct amdgpu_ring *ring,
bool tmz, uint64_t *size, uint64_t *addr,
- struct dma_fence *dep)
+ struct dma_fence *dep,
+ struct dma_resv *resv)
{
struct amdgpu_device *adev = ring->adev;
unsigned int offset, num_pages, num_dw, num_bytes;
@@ -239,6 +240,10 @@ static int amdgpu_ttm_map_buffer(struct drm_sched_entity *entity,
if (dep)
drm_sched_job_add_dependency(&job->base, dma_fence_get(dep));
+ if (resv)
+ drm_sched_job_add_resv_dependencies(&job->base, resv,
+ DMA_RESV_USAGE_BOOKKEEP);
+
src_addr = num_dw * 4;
src_addr += job->ibs[0].gpu_addr;
@@ -332,14 +337,14 @@ static int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
r = amdgpu_ttm_map_buffer(&entity->base,
src->bo, src->mem, &src_mm,
entity->gart_window_id0, ring, tmz, &cur_size, &from,
- NULL);
+ NULL, NULL);
if (r)
goto error;
r = amdgpu_ttm_map_buffer(&entity->base,
dst->bo, dst->mem, &dst_mm,
entity->gart_window_id1, ring, tmz, &cur_size, &to,
- NULL);
+ NULL, NULL);
if (r)
goto error;
@@ -422,7 +427,7 @@ static int amdgpu_move_blit(struct ttm_buffer_object *bo,
struct dma_fence *wipe_fence = NULL;
r = amdgpu_fill_buffer(&adev->mman.move_entities[0],
- abo, 0, NULL, &wipe_fence, fence,
+ abo, 0, &wipe_fence, fence,
AMDGPU_KERNEL_JOB_ID_MOVE_BLIT);
if (r) {
goto error;
@@ -2451,7 +2456,7 @@ int amdgpu_ttm_clear_buffer(struct amdgpu_bo *bo,
r = amdgpu_ttm_map_buffer(&entity->base,
&bo->tbo, bo->tbo.resource, &cursor,
entity->gart_window_id1, ring, false, &size, &addr,
- NULL);
+ NULL, NULL);
if (r)
goto err;
@@ -2472,10 +2477,21 @@ int amdgpu_ttm_clear_buffer(struct amdgpu_bo *bo,
return r;
}
+/**
+ * amdgpu_fill_buffer - fill a buffer with a given value
+ * @entity: optional entity to use. If NULL, the clearing entities will be
+ * used to load-balance the partial clears
+ * @bo: the bo to fill
+ * @src_data: the value to set
+ * @f: optional out fence. If @entity is NULL, this must be NULL and the
+ * fences from each partial clear will be added to the &dma_resv.
+ * @dependency: optional input dependency fence.
+ * @k_job_id: trace id
+ *
+ */
int amdgpu_fill_buffer(struct amdgpu_ttm_entity *entity,
struct amdgpu_bo *bo,
uint32_t src_data,
- struct dma_resv *resv,
struct dma_fence **f,
struct dma_fence *dependency,
u64 k_job_id)
@@ -2483,15 +2499,29 @@ int amdgpu_fill_buffer(struct amdgpu_ttm_entity *entity,
struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
struct dma_fence *fence = NULL;
+ struct dma_resv *resv = NULL;
struct amdgpu_res_cursor dst;
int r;
+ /* The fences will be either added to the resv object or the last fence
+ * will be returned to the caller. In the latter case, all fill jobs will
+ * be executed on the same ring.
+ */
+ WARN_ON_ONCE((entity && !f) || (!entity && f));
if (!adev->mman.buffer_funcs_enabled) {
dev_err(adev->dev,
"Trying to clear memory with ring turned off.\n");
return -EINVAL;
}
+ if (!entity) {
+ entity = &adev->mman.clear_entities[0];
+ resv = &bo->tbo.base._resv;
+ r = dma_resv_reserve_fences(resv, 1);
+ if (r)
+ return r;
+ }
+
amdgpu_res_first(bo->tbo.resource, 0, amdgpu_bo_size(bo), &dst);
mutex_lock(&entity->gart_window_lock);
@@ -2506,7 +2536,8 @@ int amdgpu_fill_buffer(struct amdgpu_ttm_entity *entity,
&bo->tbo, bo->tbo.resource, &dst,
entity->gart_window_id1, ring, false,
&cur_size, &to,
- dependency);
+ dependency,
+ resv);
if (r)
goto error;
@@ -2516,8 +2547,13 @@ int amdgpu_fill_buffer(struct amdgpu_ttm_entity *entity,
if (r)
goto error;
- dma_fence_put(fence);
- fence = next;
+ if (resv) {
+ dma_resv_add_fence(resv, next, DMA_RESV_USAGE_KERNEL);
+ dma_fence_put(next);
+ } else {
+ dma_fence_put(fence);
+ fence = next;
+ }
amdgpu_res_next(&dst, cur_size);
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
index 9dd2a76a5641..38df2b5b4bc7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
@@ -184,7 +184,6 @@ int amdgpu_ttm_clear_buffer(struct amdgpu_bo *bo,
int amdgpu_fill_buffer(struct amdgpu_ttm_entity *entity,
struct amdgpu_bo *bo,
uint32_t src_data,
- struct dma_resv *resv,
struct dma_fence **f,
struct dma_fence *dependency,
u64 k_job_id);
--
2.43.0
^ permalink raw reply [flat|nested] 40+ messages in thread* [PATCH v1 11/20] drm/amdgpu: use multiple entities in amdgpu_fill_buffer
2025-11-04 8:35 [PATCH v1 00/20] drm/amdgpu: use all SDMA instances for TTM clears and moves Pierre-Eric Pelloux-Prayer
` (9 preceding siblings ...)
2025-11-04 8:35 ` [PATCH v1 10/20] drm/amdgpu: prepare amdgpu_fill_buffer to use N entities Pierre-Eric Pelloux-Prayer
@ 2025-11-04 8:35 ` Pierre-Eric Pelloux-Prayer
2025-11-04 16:40 ` Christian König
2025-11-04 8:35 ` [PATCH v1 12/20] drm/amdgpu: use TTM_FENCES_MAX_SLOT_COUNT Pierre-Eric Pelloux-Prayer
` (8 subsequent siblings)
19 siblings, 1 reply; 40+ messages in thread
From: Pierre-Eric Pelloux-Prayer @ 2025-11-04 8:35 UTC (permalink / raw)
To: Alex Deucher, Christian König, David Airlie, Simona Vetter,
Sumit Semwal
Cc: Pierre-Eric Pelloux-Prayer, amd-gfx, dri-devel, linux-kernel,
linux-media, linaro-mm-sig
The benefits of using multiple entities is that multiple fill jobs
can run in parallel. Otherwise, even if the entity has access
to multiple engines, a burst of N independent jobs will all
run on the same engine because an entity guarantees the ordering
of execution matches the ordering of the submission.
Callers can opt-out of this behavior by passing the entity they
want to use (see amdgpu_move_blit).
Signed-off-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 84 ++++++++++++++++++-------
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 1 +
2 files changed, 64 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index c357a6d9763a..839ea8c7f6be 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -2224,6 +2224,7 @@ u32 amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable)
adev->mman.clear_entities = kcalloc(num_clear_entities,
sizeof(struct amdgpu_ttm_entity),
GFP_KERNEL);
+ atomic_set(&adev->mman.next_clear_entity, 0);
if (!adev->mman.clear_entities)
goto error_free_entity;
@@ -2498,10 +2499,12 @@ int amdgpu_fill_buffer(struct amdgpu_ttm_entity *entity,
{
struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
+ struct dma_fence *fences[TTM_FENCES_MAX_SLOT_COUNT] = {};
struct dma_fence *fence = NULL;
struct dma_resv *resv = NULL;
struct amdgpu_res_cursor dst;
- int r;
+ uint64_t cur_size, to;
+ int r, e, n_fences;
/* The fences will be either added to the resv object or the last fence
* will be returned to the caller. In the latter case, all fill jobs will
@@ -2515,53 +2518,92 @@ int amdgpu_fill_buffer(struct amdgpu_ttm_entity *entity,
}
if (!entity) {
- entity = &adev->mman.clear_entities[0];
resv = &bo->tbo.base._resv;
- r = dma_resv_reserve_fences(resv, 1);
+
+ /* Determine how much fences we're going to add to the
+ * resv object.
+ */
+ n_fences = 0;
+ amdgpu_res_first(bo->tbo.resource, 0, amdgpu_bo_size(bo), &dst);
+ while (dst.remaining) {
+ cur_size = min(dst.size, 256ULL << 20);
+
+ n_fences += 1;
+ amdgpu_res_next(&dst, cur_size);
+ }
+ if (n_fences == 0)
+ return 0;
+
+ /* One slot per entity at most. */
+ n_fences = MIN(n_fences, adev->mman.num_clear_entities);
+
+ r = dma_resv_reserve_fences(resv, n_fences);
if (r)
return r;
+ } else {
+ mutex_lock(&entity->gart_window_lock);
}
amdgpu_res_first(bo->tbo.resource, 0, amdgpu_bo_size(bo), &dst);
- mutex_lock(&entity->gart_window_lock);
while (dst.remaining) {
- struct dma_fence *next;
- uint64_t cur_size, to;
-
/* Never fill more than 256MiB at once to avoid timeouts */
cur_size = min(dst.size, 256ULL << 20);
+ if (resv) {
+ /* Pick a new entity for each partial clear so they can
+ * execute in parallel.
+ */
+ e = atomic_inc_return(&adev->mman.next_clear_entity) %
+ adev->mman.num_clear_entities;
+ entity = &adev->mman.clear_entities[e];
+ mutex_lock(&entity->gart_window_lock);
+ }
+
r = amdgpu_ttm_map_buffer(&entity->base,
&bo->tbo, bo->tbo.resource, &dst,
entity->gart_window_id1, ring, false,
&cur_size, &to,
dependency,
resv);
- if (r)
+ if (r) {
+ mutex_unlock(&entity->gart_window_lock);
goto error;
+ }
r = amdgpu_ttm_fill_mem(ring, &entity->base,
src_data, to, cur_size, resv,
- &next, true, k_job_id);
- if (r)
+ &fence, true, k_job_id);
+ if (r) {
+ mutex_unlock(&entity->gart_window_lock);
goto error;
-
- if (resv) {
- dma_resv_add_fence(resv, next, DMA_RESV_USAGE_KERNEL);
- dma_fence_put(next);
- } else {
- dma_fence_put(fence);
- fence = next;
}
amdgpu_res_next(&dst, cur_size);
+
+ if (resv) {
+ /* Delay the addition of the fences to resv, otherwise the next partial
+ * clears will depend on this one.
+ */
+ fences[e] = fence;
+ mutex_unlock(&entity->gart_window_lock);
+ } else {
+ dma_fence_put(*f);
+ *f = fence;
+ }
}
error:
- mutex_unlock(&entity->gart_window_lock);
- if (f)
- *f = dma_fence_get(fence);
- dma_fence_put(fence);
+ if (resv) {
+ for (e = 0; e < adev->mman.num_clear_entities; e++) {
+ if (fences[e]) {
+ dma_resv_add_fence(resv, fences[e], DMA_RESV_USAGE_KERNEL);
+ dma_fence_put(fences[e]);
+ }
+ }
+ } else {
+ mutex_unlock(&entity->gart_window_lock);
+ }
+
return r;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
index 38df2b5b4bc7..3fc31c7c6bfe 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
@@ -73,6 +73,7 @@ struct amdgpu_mman {
struct amdgpu_ttm_entity default_entity; /* has no gart windows */
struct amdgpu_ttm_entity *clear_entities;
+ atomic_t next_clear_entity;
u32 num_clear_entities;
struct amdgpu_ttm_entity move_entities[TTM_FENCES_MAX_SLOT_COUNT];
u32 num_move_entities;
--
2.43.0
^ permalink raw reply [flat|nested] 40+ messages in thread* Re: [PATCH v1 11/20] drm/amdgpu: use multiple entities in amdgpu_fill_buffer
2025-11-04 8:35 ` [PATCH v1 11/20] drm/amdgpu: use multiple entities in amdgpu_fill_buffer Pierre-Eric Pelloux-Prayer
@ 2025-11-04 16:40 ` Christian König
2025-11-05 10:39 ` Pierre-Eric Pelloux-Prayer
0 siblings, 1 reply; 40+ messages in thread
From: Christian König @ 2025-11-04 16:40 UTC (permalink / raw)
To: Pierre-Eric Pelloux-Prayer, Alex Deucher, David Airlie,
Simona Vetter, Sumit Semwal
Cc: amd-gfx, dri-devel, linux-kernel, linux-media, linaro-mm-sig
On 11/4/25 09:35, Pierre-Eric Pelloux-Prayer wrote:
> The benefits of using multiple entities is that multiple fill jobs
> can run in parallel. Otherwise, even if the entity has access
> to multiple engines, a burst of N independent jobs will all
> run on the same engine because an entity guarantees the ordering
> of execution matches the ordering of the submission.
>
> Callers can opt-out of this behavior by passing the entity they
> want to use (see amdgpu_move_blit).
That still sounds like a really bad idea to me.
First of all we can't reserve so many fence slots in the release handler, previously we basically just relied on the fact that the BO will most likely be mostly idle.
I think we should just use a single SDMA engine for each clear and distribute clearing different BOs over multiple engines.
Regards,
Christian.
>
> Signed-off-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 84 ++++++++++++++++++-------
> drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 1 +
> 2 files changed, 64 insertions(+), 21 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> index c357a6d9763a..839ea8c7f6be 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> @@ -2224,6 +2224,7 @@ u32 amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable)
> adev->mman.clear_entities = kcalloc(num_clear_entities,
> sizeof(struct amdgpu_ttm_entity),
> GFP_KERNEL);
> + atomic_set(&adev->mman.next_clear_entity, 0);
> if (!adev->mman.clear_entities)
> goto error_free_entity;
>
> @@ -2498,10 +2499,12 @@ int amdgpu_fill_buffer(struct amdgpu_ttm_entity *entity,
> {
> struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
> struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
> + struct dma_fence *fences[TTM_FENCES_MAX_SLOT_COUNT] = {};
> struct dma_fence *fence = NULL;
> struct dma_resv *resv = NULL;
> struct amdgpu_res_cursor dst;
> - int r;
> + uint64_t cur_size, to;
> + int r, e, n_fences;
>
> /* The fences will be either added to the resv object or the last fence
> * will be returned to the caller. In the latter case, all fill jobs will
> @@ -2515,53 +2518,92 @@ int amdgpu_fill_buffer(struct amdgpu_ttm_entity *entity,
> }
>
> if (!entity) {
> - entity = &adev->mman.clear_entities[0];
> resv = &bo->tbo.base._resv;
> - r = dma_resv_reserve_fences(resv, 1);
> +
> + /* Determine how much fences we're going to add to the
> + * resv object.
> + */
> + n_fences = 0;
> + amdgpu_res_first(bo->tbo.resource, 0, amdgpu_bo_size(bo), &dst);
> + while (dst.remaining) {
> + cur_size = min(dst.size, 256ULL << 20);
> +
> + n_fences += 1;
> + amdgpu_res_next(&dst, cur_size);
> + }
> + if (n_fences == 0)
> + return 0;
> +
> + /* One slot per entity at most. */
> + n_fences = MIN(n_fences, adev->mman.num_clear_entities);
> +
> + r = dma_resv_reserve_fences(resv, n_fences);
> if (r)
> return r;
> + } else {
> + mutex_lock(&entity->gart_window_lock);
> }
>
> amdgpu_res_first(bo->tbo.resource, 0, amdgpu_bo_size(bo), &dst);
>
> - mutex_lock(&entity->gart_window_lock);
> while (dst.remaining) {
> - struct dma_fence *next;
> - uint64_t cur_size, to;
> -
> /* Never fill more than 256MiB at once to avoid timeouts */
> cur_size = min(dst.size, 256ULL << 20);
>
> + if (resv) {
> + /* Pick a new entity for each partial clear so they can
> + * execute in parallel.
> + */
> + e = atomic_inc_return(&adev->mman.next_clear_entity) %
> + adev->mman.num_clear_entities;
> + entity = &adev->mman.clear_entities[e];
> + mutex_lock(&entity->gart_window_lock);
> + }
> +
> r = amdgpu_ttm_map_buffer(&entity->base,
> &bo->tbo, bo->tbo.resource, &dst,
> entity->gart_window_id1, ring, false,
> &cur_size, &to,
> dependency,
> resv);
> - if (r)
> + if (r) {
> + mutex_unlock(&entity->gart_window_lock);
> goto error;
> + }
>
> r = amdgpu_ttm_fill_mem(ring, &entity->base,
> src_data, to, cur_size, resv,
> - &next, true, k_job_id);
> - if (r)
> + &fence, true, k_job_id);
> + if (r) {
> + mutex_unlock(&entity->gart_window_lock);
> goto error;
> -
> - if (resv) {
> - dma_resv_add_fence(resv, next, DMA_RESV_USAGE_KERNEL);
> - dma_fence_put(next);
> - } else {
> - dma_fence_put(fence);
> - fence = next;
> }
>
> amdgpu_res_next(&dst, cur_size);
> +
> + if (resv) {
> + /* Delay the addition of the fences to resv, otherwise the next partial
> + * clears will depend on this one.
> + */
> + fences[e] = fence;
> + mutex_unlock(&entity->gart_window_lock);
> + } else {
> + dma_fence_put(*f);
> + *f = fence;
> + }
> }
> error:
> - mutex_unlock(&entity->gart_window_lock);
> - if (f)
> - *f = dma_fence_get(fence);
> - dma_fence_put(fence);
> + if (resv) {
> + for (e = 0; e < adev->mman.num_clear_entities; e++) {
> + if (fences[e]) {
> + dma_resv_add_fence(resv, fences[e], DMA_RESV_USAGE_KERNEL);
> + dma_fence_put(fences[e]);
> + }
> + }
> + } else {
> + mutex_unlock(&entity->gart_window_lock);
> + }
> +
> return r;
> }
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
> index 38df2b5b4bc7..3fc31c7c6bfe 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
> @@ -73,6 +73,7 @@ struct amdgpu_mman {
>
> struct amdgpu_ttm_entity default_entity; /* has no gart windows */
> struct amdgpu_ttm_entity *clear_entities;
> + atomic_t next_clear_entity;
> u32 num_clear_entities;
> struct amdgpu_ttm_entity move_entities[TTM_FENCES_MAX_SLOT_COUNT];
> u32 num_move_entities;
^ permalink raw reply [flat|nested] 40+ messages in thread* Re: [PATCH v1 11/20] drm/amdgpu: use multiple entities in amdgpu_fill_buffer
2025-11-04 16:40 ` Christian König
@ 2025-11-05 10:39 ` Pierre-Eric Pelloux-Prayer
2025-11-05 13:03 ` Christian König
0 siblings, 1 reply; 40+ messages in thread
From: Pierre-Eric Pelloux-Prayer @ 2025-11-05 10:39 UTC (permalink / raw)
To: Christian König, Pierre-Eric Pelloux-Prayer, Alex Deucher,
David Airlie, Simona Vetter, Sumit Semwal
Cc: amd-gfx, dri-devel, linux-kernel, linux-media, linaro-mm-sig
Le 04/11/2025 à 17:40, Christian König a écrit :
> On 11/4/25 09:35, Pierre-Eric Pelloux-Prayer wrote:
>> The benefits of using multiple entities is that multiple fill jobs
>> can run in parallel. Otherwise, even if the entity has access
>> to multiple engines, a burst of N independent jobs will all
>> run on the same engine because an entity guarantees the ordering
>> of execution matches the ordering of the submission.
>>
>> Callers can opt-out of this behavior by passing the entity they
>> want to use (see amdgpu_move_blit).
>
> That still sounds like a really bad idea to me.
>
> First of all we can't reserve so many fence slots in the release handler, previously we basically just relied on the fact that the BO will most likely be mostly idle.
>
> I think we should just use a single SDMA engine for each clear and distribute clearing different BOs over multiple engines.
So N clear entities, each one having access to a single engine. And all jobs to
clear a single BO go to the same entity?
Is that what you mean?
Pierre-Eric
>
> Regards,
> Christian.
>
>>
>> Signed-off-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
>> ---
>> drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 84 ++++++++++++++++++-------
>> drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 1 +
>> 2 files changed, 64 insertions(+), 21 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
>> index c357a6d9763a..839ea8c7f6be 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
>> @@ -2224,6 +2224,7 @@ u32 amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable)
>> adev->mman.clear_entities = kcalloc(num_clear_entities,
>> sizeof(struct amdgpu_ttm_entity),
>> GFP_KERNEL);
>> + atomic_set(&adev->mman.next_clear_entity, 0);
>> if (!adev->mman.clear_entities)
>> goto error_free_entity;
>>
>> @@ -2498,10 +2499,12 @@ int amdgpu_fill_buffer(struct amdgpu_ttm_entity *entity,
>> {
>> struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
>> struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
>> + struct dma_fence *fences[TTM_FENCES_MAX_SLOT_COUNT] = {};
>> struct dma_fence *fence = NULL;
>> struct dma_resv *resv = NULL;
>> struct amdgpu_res_cursor dst;
>> - int r;
>> + uint64_t cur_size, to;
>> + int r, e, n_fences;
>>
>> /* The fences will be either added to the resv object or the last fence
>> * will be returned to the caller. In the latter case, all fill jobs will
>> @@ -2515,53 +2518,92 @@ int amdgpu_fill_buffer(struct amdgpu_ttm_entity *entity,
>> }
>>
>> if (!entity) {
>> - entity = &adev->mman.clear_entities[0];
>> resv = &bo->tbo.base._resv;
>> - r = dma_resv_reserve_fences(resv, 1);
>> +
>> + /* Determine how much fences we're going to add to the
>> + * resv object.
>> + */
>> + n_fences = 0;
>> + amdgpu_res_first(bo->tbo.resource, 0, amdgpu_bo_size(bo), &dst);
>> + while (dst.remaining) {
>> + cur_size = min(dst.size, 256ULL << 20);
>> +
>> + n_fences += 1;
>> + amdgpu_res_next(&dst, cur_size);
>> + }
>> + if (n_fences == 0)
>> + return 0;
>> +
>> + /* One slot per entity at most. */
>> + n_fences = MIN(n_fences, adev->mman.num_clear_entities);
>> +
>> + r = dma_resv_reserve_fences(resv, n_fences);
>> if (r)
>> return r;
>> + } else {
>> + mutex_lock(&entity->gart_window_lock);
>> }
>>
>> amdgpu_res_first(bo->tbo.resource, 0, amdgpu_bo_size(bo), &dst);
>>
>> - mutex_lock(&entity->gart_window_lock);
>> while (dst.remaining) {
>> - struct dma_fence *next;
>> - uint64_t cur_size, to;
>> -
>> /* Never fill more than 256MiB at once to avoid timeouts */
>> cur_size = min(dst.size, 256ULL << 20);
>>
>> + if (resv) {
>> + /* Pick a new entity for each partial clear so they can
>> + * execute in parallel.
>> + */
>> + e = atomic_inc_return(&adev->mman.next_clear_entity) %
>> + adev->mman.num_clear_entities;
>> + entity = &adev->mman.clear_entities[e];
>> + mutex_lock(&entity->gart_window_lock);
>> + }
>> +
>> r = amdgpu_ttm_map_buffer(&entity->base,
>> &bo->tbo, bo->tbo.resource, &dst,
>> entity->gart_window_id1, ring, false,
>> &cur_size, &to,
>> dependency,
>> resv);
>> - if (r)
>> + if (r) {
>> + mutex_unlock(&entity->gart_window_lock);
>> goto error;
>> + }
>>
>> r = amdgpu_ttm_fill_mem(ring, &entity->base,
>> src_data, to, cur_size, resv,
>> - &next, true, k_job_id);
>> - if (r)
>> + &fence, true, k_job_id);
>> + if (r) {
>> + mutex_unlock(&entity->gart_window_lock);
>> goto error;
>> -
>> - if (resv) {
>> - dma_resv_add_fence(resv, next, DMA_RESV_USAGE_KERNEL);
>> - dma_fence_put(next);
>> - } else {
>> - dma_fence_put(fence);
>> - fence = next;
>> }
>>
>> amdgpu_res_next(&dst, cur_size);
>> +
>> + if (resv) {
>> + /* Delay the addition of the fences to resv, otherwise the next partial
>> + * clears will depend on this one.
>> + */
>> + fences[e] = fence;
>> + mutex_unlock(&entity->gart_window_lock);
>> + } else {
>> + dma_fence_put(*f);
>> + *f = fence;
>> + }
>> }
>> error:
>> - mutex_unlock(&entity->gart_window_lock);
>> - if (f)
>> - *f = dma_fence_get(fence);
>> - dma_fence_put(fence);
>> + if (resv) {
>> + for (e = 0; e < adev->mman.num_clear_entities; e++) {
>> + if (fences[e]) {
>> + dma_resv_add_fence(resv, fences[e], DMA_RESV_USAGE_KERNEL);
>> + dma_fence_put(fences[e]);
>> + }
>> + }
>> + } else {
>> + mutex_unlock(&entity->gart_window_lock);
>> + }
>> +
>> return r;
>> }
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
>> index 38df2b5b4bc7..3fc31c7c6bfe 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
>> @@ -73,6 +73,7 @@ struct amdgpu_mman {
>>
>> struct amdgpu_ttm_entity default_entity; /* has no gart windows */
>> struct amdgpu_ttm_entity *clear_entities;
>> + atomic_t next_clear_entity;
>> u32 num_clear_entities;
>> struct amdgpu_ttm_entity move_entities[TTM_FENCES_MAX_SLOT_COUNT];
>> u32 num_move_entities;
^ permalink raw reply [flat|nested] 40+ messages in thread* Re: [PATCH v1 11/20] drm/amdgpu: use multiple entities in amdgpu_fill_buffer
2025-11-05 10:39 ` Pierre-Eric Pelloux-Prayer
@ 2025-11-05 13:03 ` Christian König
2025-11-12 10:39 ` Pierre-Eric Pelloux-Prayer
0 siblings, 1 reply; 40+ messages in thread
From: Christian König @ 2025-11-05 13:03 UTC (permalink / raw)
To: Pierre-Eric Pelloux-Prayer, Pierre-Eric Pelloux-Prayer,
Alex Deucher, David Airlie, Simona Vetter, Sumit Semwal
Cc: amd-gfx, dri-devel, linux-kernel, linux-media, linaro-mm-sig
On 11/5/25 11:39, Pierre-Eric Pelloux-Prayer wrote:
> Le 04/11/2025 à 17:40, Christian König a écrit :
>> On 11/4/25 09:35, Pierre-Eric Pelloux-Prayer wrote:
>>> The benefits of using multiple entities is that multiple fill jobs
>>> can run in parallel. Otherwise, even if the entity has access
>>> to multiple engines, a burst of N independent jobs will all
>>> run on the same engine because an entity guarantees the ordering
>>> of execution matches the ordering of the submission.
>>>
>>> Callers can opt-out of this behavior by passing the entity they
>>> want to use (see amdgpu_move_blit).
>>
>> That still sounds like a really bad idea to me.
>>
>> First of all we can't reserve so many fence slots in the release handler, previously we basically just relied on the fact that the BO will most likely be mostly idle.
>>
>> I think we should just use a single SDMA engine for each clear and distribute clearing different BOs over multiple engines.
>
> So N clear entities, each one having access to a single engine. And all jobs to clear a single BO go to the same entity?
>
> Is that what you mean?
More or less.
N clear entities, each one has access to all engines. When a BO needs to be cleared it picks the next best entity and submits the jobs.
This way clear entities still load balance with moves and page table updates but we can keep the clearing logic simple.
Christian.
>
> Pierre-Eric
>
>>
>> Regards,
>> Christian.
>>
>>>
>>> Signed-off-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
>>> ---
>>> drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 84 ++++++++++++++++++-------
>>> drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 1 +
>>> 2 files changed, 64 insertions(+), 21 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
>>> index c357a6d9763a..839ea8c7f6be 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
>>> @@ -2224,6 +2224,7 @@ u32 amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable)
>>> adev->mman.clear_entities = kcalloc(num_clear_entities,
>>> sizeof(struct amdgpu_ttm_entity),
>>> GFP_KERNEL);
>>> + atomic_set(&adev->mman.next_clear_entity, 0);
>>> if (!adev->mman.clear_entities)
>>> goto error_free_entity;
>>> @@ -2498,10 +2499,12 @@ int amdgpu_fill_buffer(struct amdgpu_ttm_entity *entity,
>>> {
>>> struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
>>> struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
>>> + struct dma_fence *fences[TTM_FENCES_MAX_SLOT_COUNT] = {};
>>> struct dma_fence *fence = NULL;
>>> struct dma_resv *resv = NULL;
>>> struct amdgpu_res_cursor dst;
>>> - int r;
>>> + uint64_t cur_size, to;
>>> + int r, e, n_fences;
>>> /* The fences will be either added to the resv object or the last fence
>>> * will be returned to the caller. In the latter case, all fill jobs will
>>> @@ -2515,53 +2518,92 @@ int amdgpu_fill_buffer(struct amdgpu_ttm_entity *entity,
>>> }
>>> if (!entity) {
>>> - entity = &adev->mman.clear_entities[0];
>>> resv = &bo->tbo.base._resv;
>>> - r = dma_resv_reserve_fences(resv, 1);
>>> +
>>> + /* Determine how much fences we're going to add to the
>>> + * resv object.
>>> + */
>>> + n_fences = 0;
>>> + amdgpu_res_first(bo->tbo.resource, 0, amdgpu_bo_size(bo), &dst);
>>> + while (dst.remaining) {
>>> + cur_size = min(dst.size, 256ULL << 20);
>>> +
>>> + n_fences += 1;
>>> + amdgpu_res_next(&dst, cur_size);
>>> + }
>>> + if (n_fences == 0)
>>> + return 0;
>>> +
>>> + /* One slot per entity at most. */
>>> + n_fences = MIN(n_fences, adev->mman.num_clear_entities);
>>> +
>>> + r = dma_resv_reserve_fences(resv, n_fences);
>>> if (r)
>>> return r;
>>> + } else {
>>> + mutex_lock(&entity->gart_window_lock);
>>> }
>>> amdgpu_res_first(bo->tbo.resource, 0, amdgpu_bo_size(bo), &dst);
>>> - mutex_lock(&entity->gart_window_lock);
>>> while (dst.remaining) {
>>> - struct dma_fence *next;
>>> - uint64_t cur_size, to;
>>> -
>>> /* Never fill more than 256MiB at once to avoid timeouts */
>>> cur_size = min(dst.size, 256ULL << 20);
>>> + if (resv) {
>>> + /* Pick a new entity for each partial clear so they can
>>> + * execute in parallel.
>>> + */
>>> + e = atomic_inc_return(&adev->mman.next_clear_entity) %
>>> + adev->mman.num_clear_entities;
>>> + entity = &adev->mman.clear_entities[e];
>>> + mutex_lock(&entity->gart_window_lock);
>>> + }
>>> +
>>> r = amdgpu_ttm_map_buffer(&entity->base,
>>> &bo->tbo, bo->tbo.resource, &dst,
>>> entity->gart_window_id1, ring, false,
>>> &cur_size, &to,
>>> dependency,
>>> resv);
>>> - if (r)
>>> + if (r) {
>>> + mutex_unlock(&entity->gart_window_lock);
>>> goto error;
>>> + }
>>> r = amdgpu_ttm_fill_mem(ring, &entity->base,
>>> src_data, to, cur_size, resv,
>>> - &next, true, k_job_id);
>>> - if (r)
>>> + &fence, true, k_job_id);
>>> + if (r) {
>>> + mutex_unlock(&entity->gart_window_lock);
>>> goto error;
>>> -
>>> - if (resv) {
>>> - dma_resv_add_fence(resv, next, DMA_RESV_USAGE_KERNEL);
>>> - dma_fence_put(next);
>>> - } else {
>>> - dma_fence_put(fence);
>>> - fence = next;
>>> }
>>> amdgpu_res_next(&dst, cur_size);
>>> +
>>> + if (resv) {
>>> + /* Delay the addition of the fences to resv, otherwise the next partial
>>> + * clears will depend on this one.
>>> + */
>>> + fences[e] = fence;
>>> + mutex_unlock(&entity->gart_window_lock);
>>> + } else {
>>> + dma_fence_put(*f);
>>> + *f = fence;
>>> + }
>>> }
>>> error:
>>> - mutex_unlock(&entity->gart_window_lock);
>>> - if (f)
>>> - *f = dma_fence_get(fence);
>>> - dma_fence_put(fence);
>>> + if (resv) {
>>> + for (e = 0; e < adev->mman.num_clear_entities; e++) {
>>> + if (fences[e]) {
>>> + dma_resv_add_fence(resv, fences[e], DMA_RESV_USAGE_KERNEL);
>>> + dma_fence_put(fences[e]);
>>> + }
>>> + }
>>> + } else {
>>> + mutex_unlock(&entity->gart_window_lock);
>>> + }
>>> +
>>> return r;
>>> }
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
>>> index 38df2b5b4bc7..3fc31c7c6bfe 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
>>> @@ -73,6 +73,7 @@ struct amdgpu_mman {
>>> struct amdgpu_ttm_entity default_entity; /* has no gart windows */
>>> struct amdgpu_ttm_entity *clear_entities;
>>> + atomic_t next_clear_entity;
>>> u32 num_clear_entities;
>>> struct amdgpu_ttm_entity move_entities[TTM_FENCES_MAX_SLOT_COUNT];
>>> u32 num_move_entities;
^ permalink raw reply [flat|nested] 40+ messages in thread* Re: [PATCH v1 11/20] drm/amdgpu: use multiple entities in amdgpu_fill_buffer
2025-11-05 13:03 ` Christian König
@ 2025-11-12 10:39 ` Pierre-Eric Pelloux-Prayer
0 siblings, 0 replies; 40+ messages in thread
From: Pierre-Eric Pelloux-Prayer @ 2025-11-12 10:39 UTC (permalink / raw)
To: Christian König, Pierre-Eric Pelloux-Prayer, Alex Deucher,
David Airlie, Simona Vetter, Sumit Semwal
Cc: amd-gfx, dri-devel, linux-kernel, linux-media, linaro-mm-sig
Le 05/11/2025 à 14:03, Christian König a écrit :
> On 11/5/25 11:39, Pierre-Eric Pelloux-Prayer wrote:
>> Le 04/11/2025 à 17:40, Christian König a écrit :
>>> On 11/4/25 09:35, Pierre-Eric Pelloux-Prayer wrote:
>>>> The benefits of using multiple entities is that multiple fill jobs
>>>> can run in parallel. Otherwise, even if the entity has access
>>>> to multiple engines, a burst of N independent jobs will all
>>>> run on the same engine because an entity guarantees the ordering
>>>> of execution matches the ordering of the submission.
>>>>
>>>> Callers can opt-out of this behavior by passing the entity they
>>>> want to use (see amdgpu_move_blit).
>>>
>>> That still sounds like a really bad idea to me.
>>>
>>> First of all we can't reserve so many fence slots in the release handler, previously we basically just relied on the fact that the BO will most likely be mostly idle.
>>>
>>> I think we should just use a single SDMA engine for each clear and distribute clearing different BOs over multiple engines.
>>
>> So N clear entities, each one having access to a single engine. And all jobs to clear a single BO go to the same entity?
>>
>> Is that what you mean?
>
> More or less.
>
> N clear entities, each one has access to all engines. When a BO needs to be cleared it picks the next best entity and submits the jobs.
>
> This way clear entities still load balance with moves and page table updates but we can keep the clearing logic simple.
OK, I'll drop this change from patchset as a tradeoff: we lose a bit of
performance (because if a BO is built of N regions, then the N clears will
execute sequentially) but it keep the code simple.
Pierre-Eric
>
> Christian.
>
>>
>> Pierre-Eric
>>
>>>
>>> Regards,
>>> Christian.
>>>
>>>>
>>>> Signed-off-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
>>>> ---
>>>> drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 84 ++++++++++++++++++-------
>>>> drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 1 +
>>>> 2 files changed, 64 insertions(+), 21 deletions(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
>>>> index c357a6d9763a..839ea8c7f6be 100644
>>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
>>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
>>>> @@ -2224,6 +2224,7 @@ u32 amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable)
>>>> adev->mman.clear_entities = kcalloc(num_clear_entities,
>>>> sizeof(struct amdgpu_ttm_entity),
>>>> GFP_KERNEL);
>>>> + atomic_set(&adev->mman.next_clear_entity, 0);
>>>> if (!adev->mman.clear_entities)
>>>> goto error_free_entity;
>>>> @@ -2498,10 +2499,12 @@ int amdgpu_fill_buffer(struct amdgpu_ttm_entity *entity,
>>>> {
>>>> struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
>>>> struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
>>>> + struct dma_fence *fences[TTM_FENCES_MAX_SLOT_COUNT] = {};
>>>> struct dma_fence *fence = NULL;
>>>> struct dma_resv *resv = NULL;
>>>> struct amdgpu_res_cursor dst;
>>>> - int r;
>>>> + uint64_t cur_size, to;
>>>> + int r, e, n_fences;
>>>> /* The fences will be either added to the resv object or the last fence
>>>> * will be returned to the caller. In the latter case, all fill jobs will
>>>> @@ -2515,53 +2518,92 @@ int amdgpu_fill_buffer(struct amdgpu_ttm_entity *entity,
>>>> }
>>>> if (!entity) {
>>>> - entity = &adev->mman.clear_entities[0];
>>>> resv = &bo->tbo.base._resv;
>>>> - r = dma_resv_reserve_fences(resv, 1);
>>>> +
>>>> + /* Determine how much fences we're going to add to the
>>>> + * resv object.
>>>> + */
>>>> + n_fences = 0;
>>>> + amdgpu_res_first(bo->tbo.resource, 0, amdgpu_bo_size(bo), &dst);
>>>> + while (dst.remaining) {
>>>> + cur_size = min(dst.size, 256ULL << 20);
>>>> +
>>>> + n_fences += 1;
>>>> + amdgpu_res_next(&dst, cur_size);
>>>> + }
>>>> + if (n_fences == 0)
>>>> + return 0;
>>>> +
>>>> + /* One slot per entity at most. */
>>>> + n_fences = MIN(n_fences, adev->mman.num_clear_entities);
>>>> +
>>>> + r = dma_resv_reserve_fences(resv, n_fences);
>>>> if (r)
>>>> return r;
>>>> + } else {
>>>> + mutex_lock(&entity->gart_window_lock);
>>>> }
>>>> amdgpu_res_first(bo->tbo.resource, 0, amdgpu_bo_size(bo), &dst);
>>>> - mutex_lock(&entity->gart_window_lock);
>>>> while (dst.remaining) {
>>>> - struct dma_fence *next;
>>>> - uint64_t cur_size, to;
>>>> -
>>>> /* Never fill more than 256MiB at once to avoid timeouts */
>>>> cur_size = min(dst.size, 256ULL << 20);
>>>> + if (resv) {
>>>> + /* Pick a new entity for each partial clear so they can
>>>> + * execute in parallel.
>>>> + */
>>>> + e = atomic_inc_return(&adev->mman.next_clear_entity) %
>>>> + adev->mman.num_clear_entities;
>>>> + entity = &adev->mman.clear_entities[e];
>>>> + mutex_lock(&entity->gart_window_lock);
>>>> + }
>>>> +
>>>> r = amdgpu_ttm_map_buffer(&entity->base,
>>>> &bo->tbo, bo->tbo.resource, &dst,
>>>> entity->gart_window_id1, ring, false,
>>>> &cur_size, &to,
>>>> dependency,
>>>> resv);
>>>> - if (r)
>>>> + if (r) {
>>>> + mutex_unlock(&entity->gart_window_lock);
>>>> goto error;
>>>> + }
>>>> r = amdgpu_ttm_fill_mem(ring, &entity->base,
>>>> src_data, to, cur_size, resv,
>>>> - &next, true, k_job_id);
>>>> - if (r)
>>>> + &fence, true, k_job_id);
>>>> + if (r) {
>>>> + mutex_unlock(&entity->gart_window_lock);
>>>> goto error;
>>>> -
>>>> - if (resv) {
>>>> - dma_resv_add_fence(resv, next, DMA_RESV_USAGE_KERNEL);
>>>> - dma_fence_put(next);
>>>> - } else {
>>>> - dma_fence_put(fence);
>>>> - fence = next;
>>>> }
>>>> amdgpu_res_next(&dst, cur_size);
>>>> +
>>>> + if (resv) {
>>>> + /* Delay the addition of the fences to resv, otherwise the next partial
>>>> + * clears will depend on this one.
>>>> + */
>>>> + fences[e] = fence;
>>>> + mutex_unlock(&entity->gart_window_lock);
>>>> + } else {
>>>> + dma_fence_put(*f);
>>>> + *f = fence;
>>>> + }
>>>> }
>>>> error:
>>>> - mutex_unlock(&entity->gart_window_lock);
>>>> - if (f)
>>>> - *f = dma_fence_get(fence);
>>>> - dma_fence_put(fence);
>>>> + if (resv) {
>>>> + for (e = 0; e < adev->mman.num_clear_entities; e++) {
>>>> + if (fences[e]) {
>>>> + dma_resv_add_fence(resv, fences[e], DMA_RESV_USAGE_KERNEL);
>>>> + dma_fence_put(fences[e]);
>>>> + }
>>>> + }
>>>> + } else {
>>>> + mutex_unlock(&entity->gart_window_lock);
>>>> + }
>>>> +
>>>> return r;
>>>> }
>>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
>>>> index 38df2b5b4bc7..3fc31c7c6bfe 100644
>>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
>>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
>>>> @@ -73,6 +73,7 @@ struct amdgpu_mman {
>>>> struct amdgpu_ttm_entity default_entity; /* has no gart windows */
>>>> struct amdgpu_ttm_entity *clear_entities;
>>>> + atomic_t next_clear_entity;
>>>> u32 num_clear_entities;
>>>> struct amdgpu_ttm_entity move_entities[TTM_FENCES_MAX_SLOT_COUNT];
>>>> u32 num_move_entities;
^ permalink raw reply [flat|nested] 40+ messages in thread
* [PATCH v1 12/20] drm/amdgpu: use TTM_FENCES_MAX_SLOT_COUNT
2025-11-04 8:35 [PATCH v1 00/20] drm/amdgpu: use all SDMA instances for TTM clears and moves Pierre-Eric Pelloux-Prayer
` (10 preceding siblings ...)
2025-11-04 8:35 ` [PATCH v1 11/20] drm/amdgpu: use multiple entities in amdgpu_fill_buffer Pierre-Eric Pelloux-Prayer
@ 2025-11-04 8:35 ` Pierre-Eric Pelloux-Prayer
2025-11-05 8:36 ` Christian König
2025-11-04 8:35 ` [PATCH v1 13/20] drm/amdgpu: use multiple entities in amdgpu_move_blit Pierre-Eric Pelloux-Prayer
` (7 subsequent siblings)
19 siblings, 1 reply; 40+ messages in thread
From: Pierre-Eric Pelloux-Prayer @ 2025-11-04 8:35 UTC (permalink / raw)
To: Alex Deucher, Christian König, David Airlie, Simona Vetter,
Felix Kuehling, Harry Wentland, Leo Li, Rodrigo Siqueira
Cc: Pierre-Eric Pelloux-Prayer, amd-gfx, dri-devel, linux-kernel
Use TTM_FENCES_MAX_SLOT_COUNT as an upperbound of how many fences
ttm might need to deal with moves/evictions.
Signed-off-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 5 ++---
drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 3 ++-
drivers/gpu/drm/amd/amdkfd/kfd_svm.c | 2 +-
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c | 2 +-
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_wb.c | 2 +-
7 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index ecdfe6cb36cc..b232ed28872b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -916,9 +916,8 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p,
goto out_free_user_pages;
amdgpu_bo_list_for_each_entry(e, p->bo_list) {
- /* One fence for TTM and one for each CS job */
r = drm_exec_prepare_obj(&p->exec, &e->bo->tbo.base,
- 1 + p->gang_size);
+ TTM_FENCES_MAX_SLOT_COUNT + p->gang_size);
drm_exec_retry_on_contention(&p->exec);
if (unlikely(r))
goto out_free_user_pages;
@@ -928,7 +927,7 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p,
if (p->uf_bo) {
r = drm_exec_prepare_obj(&p->exec, &p->uf_bo->tbo.base,
- 1 + p->gang_size);
+ TTM_FENCES_MAX_SLOT_COUNT + p->gang_size);
drm_exec_retry_on_contention(&p->exec);
if (unlikely(r))
goto out_free_user_pages;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
index ce073e894584..f773b06dd135 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
@@ -353,7 +353,7 @@ static void amdgpu_gem_object_close(struct drm_gem_object *obj,
drm_exec_init(&exec, DRM_EXEC_IGNORE_DUPLICATES, 0);
drm_exec_until_all_locked(&exec) {
- r = drm_exec_prepare_obj(&exec, &bo->tbo.base, 1);
+ r = drm_exec_prepare_obj(&exec, &bo->tbo.base, TTM_FENCES_MAX_SLOT_COUNT);
drm_exec_retry_on_contention(&exec);
if (unlikely(r))
goto out_unlock;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c
index 79bad9cbe2ab..d9bb16186e1f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c
@@ -326,7 +326,7 @@ static int amdgpu_vkms_prepare_fb(struct drm_plane *plane,
return r;
}
- r = dma_resv_reserve_fences(rbo->tbo.base.resv, 1);
+ r = dma_resv_reserve_fences(rbo->tbo.base.resv, TTM_FENCES_MAX_SLOT_COUNT);
if (r) {
dev_err(adev->dev, "allocating fence slot failed (%d)\n", r);
goto error_unlock;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 2f8e83f840a8..bc11e212f08c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -2630,7 +2630,8 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
}
amdgpu_vm_bo_base_init(&vm->root, vm, root_bo);
- r = dma_resv_reserve_fences(root_bo->tbo.base.resv, 1);
+ r = dma_resv_reserve_fences(root_bo->tbo.base.resv,
+ TTM_FENCES_MAX_SLOT_COUNT);
if (r)
goto error_free_root;
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
index ffb7b36e577c..ea8dd17e2852 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
@@ -627,7 +627,7 @@ svm_range_vram_node_new(struct kfd_node *node, struct svm_range *prange,
}
}
- r = dma_resv_reserve_fences(bo->tbo.base.resv, 1);
+ r = dma_resv_reserve_fences(bo->tbo.base.resv, TTM_FENCES_MAX_SLOT_COUNT);
if (r) {
pr_debug("failed %d to reserve bo\n", r);
amdgpu_bo_unreserve(bo);
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
index 56cb866ac6f8..1f2a5dcfa3e5 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
@@ -952,7 +952,7 @@ static int amdgpu_dm_plane_helper_prepare_fb(struct drm_plane *plane,
return r;
}
- r = dma_resv_reserve_fences(rbo->tbo.base.resv, 1);
+ r = dma_resv_reserve_fences(rbo->tbo.base.resv, TTM_FENCES_MAX_SLOT_COUNT);
if (r) {
drm_err(adev_to_drm(adev), "reserving fence slot failed (%d)\n", r);
goto error_unlock;
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_wb.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_wb.c
index d9527c05fc87..60b57d213bdd 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_wb.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_wb.c
@@ -106,7 +106,7 @@ static int amdgpu_dm_wb_prepare_job(struct drm_writeback_connector *wb_connector
return r;
}
- r = dma_resv_reserve_fences(rbo->tbo.base.resv, 1);
+ r = dma_resv_reserve_fences(rbo->tbo.base.resv, TTM_FENCES_MAX_SLOT_COUNT);
if (r) {
drm_err(adev_to_drm(adev), "reserving fence slot failed (%d)\n", r);
goto error_unlock;
--
2.43.0
^ permalink raw reply [flat|nested] 40+ messages in thread* Re: [PATCH v1 12/20] drm/amdgpu: use TTM_FENCES_MAX_SLOT_COUNT
2025-11-04 8:35 ` [PATCH v1 12/20] drm/amdgpu: use TTM_FENCES_MAX_SLOT_COUNT Pierre-Eric Pelloux-Prayer
@ 2025-11-05 8:36 ` Christian König
0 siblings, 0 replies; 40+ messages in thread
From: Christian König @ 2025-11-05 8:36 UTC (permalink / raw)
To: Pierre-Eric Pelloux-Prayer, Alex Deucher, David Airlie,
Simona Vetter, Felix Kuehling, Harry Wentland, Leo Li,
Rodrigo Siqueira
Cc: amd-gfx, dri-devel, linux-kernel
On 11/4/25 09:35, Pierre-Eric Pelloux-Prayer wrote:
> Use TTM_FENCES_MAX_SLOT_COUNT as an upperbound of how many fences
> ttm might need to deal with moves/evictions.
>
> Signed-off-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 5 ++---
> drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 3 ++-
> drivers/gpu/drm/amd/amdkfd/kfd_svm.c | 2 +-
> drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c | 2 +-
> drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_wb.c | 2 +-
> 7 files changed, 9 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
> index ecdfe6cb36cc..b232ed28872b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
> @@ -916,9 +916,8 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p,
> goto out_free_user_pages;
>
> amdgpu_bo_list_for_each_entry(e, p->bo_list) {
> - /* One fence for TTM and one for each CS job */
> r = drm_exec_prepare_obj(&p->exec, &e->bo->tbo.base,
> - 1 + p->gang_size);
> + TTM_FENCES_MAX_SLOT_COUNT + p->gang_size);
> drm_exec_retry_on_contention(&p->exec);
> if (unlikely(r))
> goto out_free_user_pages;
> @@ -928,7 +927,7 @@ static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p,
>
> if (p->uf_bo) {
> r = drm_exec_prepare_obj(&p->exec, &p->uf_bo->tbo.base,
> - 1 + p->gang_size);
> + TTM_FENCES_MAX_SLOT_COUNT + p->gang_size);
> drm_exec_retry_on_contention(&p->exec);
> if (unlikely(r))
> goto out_free_user_pages;
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
> index ce073e894584..f773b06dd135 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
> @@ -353,7 +353,7 @@ static void amdgpu_gem_object_close(struct drm_gem_object *obj,
>
> drm_exec_init(&exec, DRM_EXEC_IGNORE_DUPLICATES, 0);
> drm_exec_until_all_locked(&exec) {
> - r = drm_exec_prepare_obj(&exec, &bo->tbo.base, 1);
> + r = drm_exec_prepare_obj(&exec, &bo->tbo.base, TTM_FENCES_MAX_SLOT_COUNT);
> drm_exec_retry_on_contention(&exec);
> if (unlikely(r))
> goto out_unlock;
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c
> index 79bad9cbe2ab..d9bb16186e1f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c
> @@ -326,7 +326,7 @@ static int amdgpu_vkms_prepare_fb(struct drm_plane *plane,
> return r;
> }
>
> - r = dma_resv_reserve_fences(rbo->tbo.base.resv, 1);
> + r = dma_resv_reserve_fences(rbo->tbo.base.resv, TTM_FENCES_MAX_SLOT_COUNT);
> if (r) {
> dev_err(adev->dev, "allocating fence slot failed (%d)\n", r);
While at it please also drop this error message. It is absolutely not helpful at all.
> goto error_unlock;
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> index 2f8e83f840a8..bc11e212f08c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> @@ -2630,7 +2630,8 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
> }
>
> amdgpu_vm_bo_base_init(&vm->root, vm, root_bo);
> - r = dma_resv_reserve_fences(root_bo->tbo.base.resv, 1);
> + r = dma_resv_reserve_fences(root_bo->tbo.base.resv,
> + TTM_FENCES_MAX_SLOT_COUNT);
> if (r)
> goto error_free_root;
>
> diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
> index ffb7b36e577c..ea8dd17e2852 100644
> --- a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
> +++ b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
> @@ -627,7 +627,7 @@ svm_range_vram_node_new(struct kfd_node *node, struct svm_range *prange,
> }
> }
>
> - r = dma_resv_reserve_fences(bo->tbo.base.resv, 1);
> + r = dma_resv_reserve_fences(bo->tbo.base.resv, TTM_FENCES_MAX_SLOT_COUNT);
> if (r) {
> pr_debug("failed %d to reserve bo\n", r);
Same here.
> amdgpu_bo_unreserve(bo);
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
> index 56cb866ac6f8..1f2a5dcfa3e5 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_plane.c
> @@ -952,7 +952,7 @@ static int amdgpu_dm_plane_helper_prepare_fb(struct drm_plane *plane,
> return r;
> }
>
> - r = dma_resv_reserve_fences(rbo->tbo.base.resv, 1);
> + r = dma_resv_reserve_fences(rbo->tbo.base.resv, TTM_FENCES_MAX_SLOT_COUNT);
> if (r) {
> drm_err(adev_to_drm(adev), "reserving fence slot failed (%d)\n", r);
And here.
> goto error_unlock;
> diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_wb.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_wb.c
> index d9527c05fc87..60b57d213bdd 100644
> --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_wb.c
> +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_wb.c
> @@ -106,7 +106,7 @@ static int amdgpu_dm_wb_prepare_job(struct drm_writeback_connector *wb_connector
> return r;
> }
>
> - r = dma_resv_reserve_fences(rbo->tbo.base.resv, 1);
> + r = dma_resv_reserve_fences(rbo->tbo.base.resv, TTM_FENCES_MAX_SLOT_COUNT);
> if (r) {
> drm_err(adev_to_drm(adev), "reserving fence slot failed (%d)\n", r);
And here.
Regards,
Christian.
> goto error_unlock;
^ permalink raw reply [flat|nested] 40+ messages in thread
* [PATCH v1 13/20] drm/amdgpu: use multiple entities in amdgpu_move_blit
2025-11-04 8:35 [PATCH v1 00/20] drm/amdgpu: use all SDMA instances for TTM clears and moves Pierre-Eric Pelloux-Prayer
` (11 preceding siblings ...)
2025-11-04 8:35 ` [PATCH v1 12/20] drm/amdgpu: use TTM_FENCES_MAX_SLOT_COUNT Pierre-Eric Pelloux-Prayer
@ 2025-11-04 8:35 ` Pierre-Eric Pelloux-Prayer
2025-11-04 8:35 ` [PATCH v1 14/20] drm/amdgpu: pass all the sdma rings to amdgpu_mman Pierre-Eric Pelloux-Prayer
` (6 subsequent siblings)
19 siblings, 0 replies; 40+ messages in thread
From: Pierre-Eric Pelloux-Prayer @ 2025-11-04 8:35 UTC (permalink / raw)
To: Alex Deucher, Christian König, David Airlie, Simona Vetter
Cc: Pierre-Eric Pelloux-Prayer, amd-gfx, dri-devel, linux-kernel
Thanks to "drm/ttm: rework pipelined eviction fence handling", ttm
can deal correctly with moves and evictions being executed from
different contexts.
Create several entities and use them in a round-robin fashion.
Signed-off-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 14 +++++++++++---
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 1 +
2 files changed, 12 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 839ea8c7f6be..c3a88574f143 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -401,6 +401,7 @@ static int amdgpu_move_blit(struct ttm_buffer_object *bo,
{
struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
struct amdgpu_bo *abo = ttm_to_amdgpu_bo(bo);
+ struct amdgpu_ttm_entity *entity;
struct amdgpu_copy_mem src, dst;
struct dma_fence *fence = NULL;
int r;
@@ -412,8 +413,12 @@ static int amdgpu_move_blit(struct ttm_buffer_object *bo,
src.offset = 0;
dst.offset = 0;
+ int e = atomic_inc_return(&adev->mman.next_move_entity) %
+ adev->mman.num_move_entities;
+ entity = &adev->mman.move_entities[e];
+
r = amdgpu_ttm_copy_mem_to_mem(adev,
- &adev->mman.move_entities[0],
+ entity,
&src, &dst,
new_mem->size,
amdgpu_bo_encrypted(abo),
@@ -426,7 +431,7 @@ static int amdgpu_move_blit(struct ttm_buffer_object *bo,
(abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE)) {
struct dma_fence *wipe_fence = NULL;
- r = amdgpu_fill_buffer(&adev->mman.move_entities[0],
+ r = amdgpu_fill_buffer(entity,
abo, 0, &wipe_fence, fence,
AMDGPU_KERNEL_JOB_ID_MOVE_BLIT);
if (r) {
@@ -2179,10 +2184,12 @@ u32 amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable)
struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM);
uint64_t size;
int r, i, j;
- u32 num_clear_entities, num_move_entities, windows, w;
+ u32 num_clear_entities, num_move_entities;
+ u32 windows, w;
num_clear_entities = adev->sdma.num_instances;
num_move_entities = MIN(adev->sdma.num_instances, TTM_FENCES_MAX_SLOT_COUNT);
+ man->pipelined_eviction.n_fences = num_move_entities;
windows = adev->gmc.is_app_apu ? 0 : (2 * num_move_entities + num_clear_entities);
if (!adev->mman.initialized || amdgpu_in_reset(adev) ||
@@ -2205,6 +2212,7 @@ u32 amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable)
}
adev->mman.num_move_entities = num_move_entities;
+ atomic_set(&adev->mman.next_move_entity, 0);
for (i = 0; i < num_move_entities; i++) {
r = drm_sched_entity_init(&adev->mman.move_entities[i].base,
DRM_SCHED_PRIORITY_NORMAL, &sched,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
index 3fc31c7c6bfe..c3df9d24fb96 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
@@ -76,6 +76,7 @@ struct amdgpu_mman {
atomic_t next_clear_entity;
u32 num_clear_entities;
struct amdgpu_ttm_entity move_entities[TTM_FENCES_MAX_SLOT_COUNT];
+ atomic_t next_move_entity;
u32 num_move_entities;
struct amdgpu_vram_mgr vram_mgr;
--
2.43.0
^ permalink raw reply [flat|nested] 40+ messages in thread* [PATCH v1 14/20] drm/amdgpu: pass all the sdma rings to amdgpu_mman
2025-11-04 8:35 [PATCH v1 00/20] drm/amdgpu: use all SDMA instances for TTM clears and moves Pierre-Eric Pelloux-Prayer
` (12 preceding siblings ...)
2025-11-04 8:35 ` [PATCH v1 13/20] drm/amdgpu: use multiple entities in amdgpu_move_blit Pierre-Eric Pelloux-Prayer
@ 2025-11-04 8:35 ` Pierre-Eric Pelloux-Prayer
2025-11-04 8:35 ` [PATCH v1 15/20] drm/amdgpu: introduce amdgpu_sdma_set_vm_pte_scheds Pierre-Eric Pelloux-Prayer
` (5 subsequent siblings)
19 siblings, 0 replies; 40+ messages in thread
From: Pierre-Eric Pelloux-Prayer @ 2025-11-04 8:35 UTC (permalink / raw)
To: Alex Deucher, Christian König, David Airlie, Simona Vetter,
Felix Kuehling
Cc: Pierre-Eric Pelloux-Prayer, amd-gfx, dri-devel, linux-kernel
This will allow the use of all of them for clear/fill buffer
operations.
Since the code is the same for all sdma versions, add a new
helper amdgpu_sdma_set_buffer_funcs_rings to set buffer_funcs_rings
based on the number of sdma instances.
Signed-off-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 8 +++----
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 2 +-
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 22 ++++++++++++++-----
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 3 ++-
drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 2 +-
drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 2 +-
drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 5 +----
drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c | 5 +----
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 2 +-
drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/si_dma.c | 2 +-
drivers/gpu/drm/amd/amdkfd/kfd_migrate.c | 2 +-
17 files changed, 37 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 50079209c472..a9dc13659899 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1613,6 +1613,7 @@ struct dma_fence *amdgpu_device_enforce_isolation(struct amdgpu_device *adev,
bool amdgpu_device_has_display_hardware(struct amdgpu_device *adev);
ssize_t amdgpu_get_soft_full_reset_mask(struct amdgpu_ring *ring);
ssize_t amdgpu_show_reset_mask(char *buf, uint32_t supported_reset);
+void amdgpu_sdma_set_buffer_funcs_rings(struct amdgpu_device *adev);
/* atpx handler */
#if defined(CONFIG_VGA_SWITCHEROO)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c
index b59040a8771f..7147ac477996 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.c
@@ -37,7 +37,7 @@ static int amdgpu_benchmark_do_move(struct amdgpu_device *adev, unsigned size,
stime = ktime_get();
for (i = 0; i < n; i++) {
- struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
+ struct amdgpu_ring *ring = adev->mman.buffer_funcs_rings[0];
r = amdgpu_copy_buffer(ring, &adev->mman.default_entity.base,
saddr, daddr, size, NULL, &fence,
false, 0);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index b92234d63562..34e9e898568f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -3303,7 +3303,7 @@ static int amdgpu_device_ip_init(struct amdgpu_device *adev)
if (r)
goto init_failed;
- if (adev->mman.buffer_funcs_ring->sched.ready)
+ if (adev->mman.buffer_funcs_rings[0]->sched.ready)
amdgpu_ttm_set_buffer_funcs_status(adev, true);
/* Don't init kfd if whole hive need to be reset during init */
@@ -4143,7 +4143,7 @@ static int amdgpu_device_ip_resume(struct amdgpu_device *adev)
r = amdgpu_device_ip_resume_phase2(adev);
- if (adev->mman.buffer_funcs_ring->sched.ready)
+ if (adev->mman.buffer_funcs_rings[0]->sched.ready)
amdgpu_ttm_set_buffer_funcs_status(adev, true);
if (r)
@@ -4493,7 +4493,7 @@ int amdgpu_device_init(struct amdgpu_device *adev,
adev->num_rings = 0;
RCU_INIT_POINTER(adev->gang_submit, dma_fence_get_stub());
adev->mman.buffer_funcs = NULL;
- adev->mman.buffer_funcs_ring = NULL;
+ adev->mman.num_buffer_funcs_rings = 0;
adev->vm_manager.vm_pte_funcs = NULL;
adev->vm_manager.vm_pte_num_scheds = 0;
adev->gmc.gmc_funcs = NULL;
@@ -5965,7 +5965,7 @@ int amdgpu_device_reinit_after_reset(struct amdgpu_reset_context *reset_context)
if (r)
goto out;
- if (tmp_adev->mman.buffer_funcs_ring->sched.ready)
+ if (tmp_adev->mman.buffer_funcs_rings[0]->sched.ready)
amdgpu_ttm_set_buffer_funcs_status(tmp_adev, true);
r = amdgpu_device_ip_resume_phase3(tmp_adev);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
index 2713dd51ab9a..e21ab1542298 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
@@ -651,7 +651,7 @@ int amdgpu_gmc_allocate_vm_inv_eng(struct amdgpu_device *adev)
void amdgpu_gmc_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
uint32_t vmhub, uint32_t flush_type)
{
- struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
+ struct amdgpu_ring *ring = adev->mman.buffer_funcs_rings[0];
struct amdgpu_vmhub *hub = &adev->vmhub[vmhub];
struct dma_fence *fence;
struct amdgpu_job *job;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index c3a88574f143..47eaab9350ae 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -308,7 +308,7 @@ static int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
struct dma_resv *resv,
struct dma_fence **f)
{
- struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
+ struct amdgpu_ring *ring = adev->mman.buffer_funcs_rings[0];
struct amdgpu_res_cursor src_mm, dst_mm;
struct dma_fence *fence = NULL;
int r = 0;
@@ -1530,7 +1530,7 @@ static int amdgpu_ttm_access_memory_sdma(struct ttm_buffer_object *bo,
amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr, dst_addr,
PAGE_SIZE, 0);
- amdgpu_ring_pad_ib(adev->mman.buffer_funcs_ring, &job->ibs[0]);
+ amdgpu_ring_pad_ib(adev->mman.buffer_funcs_rings[0], &job->ibs[0]);
WARN_ON(job->ibs[0].length_dw > num_dw);
fence = amdgpu_job_submit(job);
@@ -2200,7 +2200,7 @@ u32 amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable)
struct amdgpu_ring *ring;
struct drm_gpu_scheduler *sched;
- ring = adev->mman.buffer_funcs_ring;
+ ring = adev->mman.buffer_funcs_rings[0];
sched = &ring->sched;
r = drm_sched_entity_init(&adev->mman.default_entity.base,
DRM_SCHED_PRIORITY_KERNEL, &sched,
@@ -2433,7 +2433,7 @@ int amdgpu_ttm_clear_buffer(struct amdgpu_bo *bo,
struct dma_fence **fence)
{
struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
- struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
+ struct amdgpu_ring *ring = adev->mman.buffer_funcs_rings[0];
struct amdgpu_ttm_entity *entity;
struct amdgpu_res_cursor cursor;
u64 addr;
@@ -2506,7 +2506,7 @@ int amdgpu_fill_buffer(struct amdgpu_ttm_entity *entity,
u64 k_job_id)
{
struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
- struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
+ struct amdgpu_ring *ring = adev->mman.buffer_funcs_rings[0];
struct dma_fence *fences[TTM_FENCES_MAX_SLOT_COUNT] = {};
struct dma_fence *fence = NULL;
struct dma_resv *resv = NULL;
@@ -2645,6 +2645,18 @@ int amdgpu_ttm_evict_resources(struct amdgpu_device *adev, int mem_type)
return ttm_resource_manager_evict_all(&adev->mman.bdev, man);
}
+void amdgpu_sdma_set_buffer_funcs_rings(struct amdgpu_device *adev)
+{
+ struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)];
+ int i;
+
+ for (i = 0; i < adev->sdma.num_instances; i++)
+ adev->mman.buffer_funcs_rings[i] = &adev->sdma.instance[i].ring;
+
+ adev->mman.num_buffer_funcs_rings = hub->sdma_invalidation_workaround ?
+ 1 : adev->sdma.num_instances;
+}
+
#if defined(CONFIG_DEBUG_FS)
static int amdgpu_ttm_page_pool_show(struct seq_file *m, void *unused)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
index c3df9d24fb96..d7fee371b814 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
@@ -66,7 +66,8 @@ struct amdgpu_mman {
/* buffer handling */
const struct amdgpu_buffer_funcs *buffer_funcs;
- struct amdgpu_ring *buffer_funcs_ring;
+ struct amdgpu_ring *buffer_funcs_rings[AMDGPU_MAX_RINGS];
+ u32 num_buffer_funcs_rings;
bool buffer_funcs_enabled;
struct mutex gtt_window_lock;
diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
index 9e8715b4739d..25040997c367 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
@@ -1334,7 +1334,7 @@ static const struct amdgpu_buffer_funcs cik_sdma_buffer_funcs = {
static void cik_sdma_set_buffer_funcs(struct amdgpu_device *adev)
{
adev->mman.buffer_funcs = &cik_sdma_buffer_funcs;
- adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
+ amdgpu_sdma_set_buffer_funcs_rings(adev);
}
static const struct amdgpu_vm_pte_funcs cik_sdma_vm_pte_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
index 92ce580647cd..149356c9346a 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
@@ -1229,7 +1229,7 @@ static const struct amdgpu_buffer_funcs sdma_v2_4_buffer_funcs = {
static void sdma_v2_4_set_buffer_funcs(struct amdgpu_device *adev)
{
adev->mman.buffer_funcs = &sdma_v2_4_buffer_funcs;
- adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
+ amdgpu_sdma_set_buffer_funcs_rings(adev);
}
static const struct amdgpu_vm_pte_funcs sdma_v2_4_vm_pte_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
index 1c076bd1cf73..6b538b6bd18f 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
@@ -1671,7 +1671,7 @@ static const struct amdgpu_buffer_funcs sdma_v3_0_buffer_funcs = {
static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev)
{
adev->mman.buffer_funcs = &sdma_v3_0_buffer_funcs;
- adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
+ amdgpu_sdma_set_buffer_funcs_rings(adev);
}
static const struct amdgpu_vm_pte_funcs sdma_v3_0_vm_pte_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index f38004e6064e..60a97d1a82f2 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -2609,10 +2609,7 @@ static const struct amdgpu_buffer_funcs sdma_v4_0_buffer_funcs = {
static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev)
{
adev->mman.buffer_funcs = &sdma_v4_0_buffer_funcs;
- if (adev->sdma.has_page_queue)
- adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].page;
- else
- adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
+ amdgpu_sdma_set_buffer_funcs_rings(adev);
}
static const struct amdgpu_vm_pte_funcs sdma_v4_0_vm_pte_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
index 36b1ca73c2ed..d265157bc4e1 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
@@ -2310,10 +2310,7 @@ static const struct amdgpu_buffer_funcs sdma_v4_4_2_buffer_funcs = {
static void sdma_v4_4_2_set_buffer_funcs(struct amdgpu_device *adev)
{
adev->mman.buffer_funcs = &sdma_v4_4_2_buffer_funcs;
- if (adev->sdma.has_page_queue)
- adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].page;
- else
- adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
+ amdgpu_sdma_set_buffer_funcs_rings(adev);
}
static const struct amdgpu_vm_pte_funcs sdma_v4_4_2_vm_pte_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
index 7dc67a22a7a0..127f001ebb5a 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
@@ -2068,7 +2068,7 @@ static void sdma_v5_0_set_buffer_funcs(struct amdgpu_device *adev)
{
if (adev->mman.buffer_funcs == NULL) {
adev->mman.buffer_funcs = &sdma_v5_0_buffer_funcs;
- adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
+ amdgpu_sdma_set_buffer_funcs_rings(adev);
}
}
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
index 3bd44c24f692..78654ac3047d 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
@@ -2078,7 +2078,7 @@ static void sdma_v5_2_set_buffer_funcs(struct amdgpu_device *adev)
{
if (adev->mman.buffer_funcs == NULL) {
adev->mman.buffer_funcs = &sdma_v5_2_buffer_funcs;
- adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
+ amdgpu_sdma_set_buffer_funcs_rings(adev);
}
}
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
index db6e41967f12..d1a7eb6e7ce2 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
@@ -1885,7 +1885,7 @@ static const struct amdgpu_buffer_funcs sdma_v6_0_buffer_funcs = {
static void sdma_v6_0_set_buffer_funcs(struct amdgpu_device *adev)
{
adev->mman.buffer_funcs = &sdma_v6_0_buffer_funcs;
- adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
+ amdgpu_sdma_set_buffer_funcs_rings(adev);
}
static const struct amdgpu_vm_pte_funcs sdma_v6_0_vm_pte_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c
index 326ecc8d37d2..9f15aa1df636 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c
@@ -1827,7 +1827,7 @@ static const struct amdgpu_buffer_funcs sdma_v7_0_buffer_funcs = {
static void sdma_v7_0_set_buffer_funcs(struct amdgpu_device *adev)
{
adev->mman.buffer_funcs = &sdma_v7_0_buffer_funcs;
- adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
+ amdgpu_sdma_set_buffer_funcs_rings(adev);
}
static const struct amdgpu_vm_pte_funcs sdma_v7_0_vm_pte_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/si_dma.c b/drivers/gpu/drm/amd/amdgpu/si_dma.c
index 7f18e4875287..621c6c17e6dd 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_dma.c
+++ b/drivers/gpu/drm/amd/amdgpu/si_dma.c
@@ -827,7 +827,7 @@ static const struct amdgpu_buffer_funcs si_dma_buffer_funcs = {
static void si_dma_set_buffer_funcs(struct amdgpu_device *adev)
{
adev->mman.buffer_funcs = &si_dma_buffer_funcs;
- adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
+ amdgpu_sdma_set_buffer_funcs_rings(adev);
}
static const struct amdgpu_vm_pte_funcs si_dma_vm_pte_funcs = {
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
index 5daacb816cf7..852b9df0a0dc 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
@@ -129,7 +129,7 @@ svm_migrate_copy_memory_gart(struct amdgpu_device *adev, dma_addr_t *sys,
struct dma_fence **mfence)
{
const u64 GTT_MAX_PAGES = AMDGPU_GTT_MAX_TRANSFER_SIZE;
- struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
+ struct amdgpu_ring *ring = adev->mman.buffer_funcs_rings[0];
struct amdgpu_ttm_entity *entity;
u64 gart_s, gart_d;
struct dma_fence *next;
--
2.43.0
^ permalink raw reply [flat|nested] 40+ messages in thread* [PATCH v1 15/20] drm/amdgpu: introduce amdgpu_sdma_set_vm_pte_scheds
2025-11-04 8:35 [PATCH v1 00/20] drm/amdgpu: use all SDMA instances for TTM clears and moves Pierre-Eric Pelloux-Prayer
` (13 preceding siblings ...)
2025-11-04 8:35 ` [PATCH v1 14/20] drm/amdgpu: pass all the sdma rings to amdgpu_mman Pierre-Eric Pelloux-Prayer
@ 2025-11-04 8:35 ` Pierre-Eric Pelloux-Prayer
2025-11-05 8:41 ` Christian König
2025-11-04 8:35 ` [PATCH v1 16/20] drm/amdgpu: give ttm entities access to all the sdma scheds Pierre-Eric Pelloux-Prayer
` (4 subsequent siblings)
19 siblings, 1 reply; 40+ messages in thread
From: Pierre-Eric Pelloux-Prayer @ 2025-11-04 8:35 UTC (permalink / raw)
To: Alex Deucher, Christian König, David Airlie, Simona Vetter
Cc: Pierre-Eric Pelloux-Prayer, amd-gfx, dri-devel, linux-kernel
All sdma versions used the same logic, so add a helper and move the
common code to a single place.
Signed-off-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 15 +++++++++++++++
drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 8 +-------
drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 8 +-------
drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 8 +-------
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 12 +-----------
drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c | 12 +-----------
drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 8 +-------
drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 8 +-------
drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c | 8 +-------
drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c | 8 +-------
drivers/gpu/drm/amd/amdgpu/si_dma.c | 8 +-------
12 files changed, 26 insertions(+), 78 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index a9dc13659899..dead938a59a4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1614,6 +1614,7 @@ bool amdgpu_device_has_display_hardware(struct amdgpu_device *adev);
ssize_t amdgpu_get_soft_full_reset_mask(struct amdgpu_ring *ring);
ssize_t amdgpu_show_reset_mask(char *buf, uint32_t supported_reset);
void amdgpu_sdma_set_buffer_funcs_rings(struct amdgpu_device *adev);
+void amdgpu_sdma_set_vm_pte_scheds(struct amdgpu_device *adev);
/* atpx handler */
#if defined(CONFIG_VGA_SWITCHEROO)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index bc11e212f08c..b66e41e979ad 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -3210,3 +3210,18 @@ void amdgpu_vm_print_task_info(struct amdgpu_device *adev,
task_info->process_name, task_info->tgid,
task_info->task.comm, task_info->task.pid);
}
+
+void amdgpu_sdma_set_vm_pte_scheds(struct amdgpu_device *adev)
+{
+ struct drm_gpu_scheduler *sched;
+ int i;
+
+ for (i = 0; i < adev->sdma.num_instances; i++) {
+ if (adev->sdma.has_page_queue)
+ sched = &adev->sdma.instance[i].page.sched;
+ else
+ sched = &adev->sdma.instance[i].ring.sched;
+ adev->vm_manager.vm_pte_scheds[i] = sched;
+ }
+ adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
+}
diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
index 25040997c367..f2515de65597 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
@@ -1347,14 +1347,8 @@ static const struct amdgpu_vm_pte_funcs cik_sdma_vm_pte_funcs = {
static void cik_sdma_set_vm_pte_funcs(struct amdgpu_device *adev)
{
- unsigned i;
-
adev->vm_manager.vm_pte_funcs = &cik_sdma_vm_pte_funcs;
- for (i = 0; i < adev->sdma.num_instances; i++) {
- adev->vm_manager.vm_pte_scheds[i] =
- &adev->sdma.instance[i].ring.sched;
- }
- adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
+ amdgpu_sdma_set_vm_pte_scheds(adev);
}
const struct amdgpu_ip_block_version cik_sdma_ip_block =
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
index 149356c9346a..4b2c7f75eadb 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
@@ -1242,14 +1242,8 @@ static const struct amdgpu_vm_pte_funcs sdma_v2_4_vm_pte_funcs = {
static void sdma_v2_4_set_vm_pte_funcs(struct amdgpu_device *adev)
{
- unsigned i;
-
adev->vm_manager.vm_pte_funcs = &sdma_v2_4_vm_pte_funcs;
- for (i = 0; i < adev->sdma.num_instances; i++) {
- adev->vm_manager.vm_pte_scheds[i] =
- &adev->sdma.instance[i].ring.sched;
- }
- adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
+ amdgpu_sdma_set_vm_pte_scheds(adev);
}
const struct amdgpu_ip_block_version sdma_v2_4_ip_block = {
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
index 6b538b6bd18f..fe0c855a803a 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
@@ -1684,14 +1684,8 @@ static const struct amdgpu_vm_pte_funcs sdma_v3_0_vm_pte_funcs = {
static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev)
{
- unsigned i;
-
adev->vm_manager.vm_pte_funcs = &sdma_v3_0_vm_pte_funcs;
- for (i = 0; i < adev->sdma.num_instances; i++) {
- adev->vm_manager.vm_pte_scheds[i] =
- &adev->sdma.instance[i].ring.sched;
- }
- adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
+ amdgpu_sdma_set_vm_pte_scheds(adev);
}
const struct amdgpu_ip_block_version sdma_v3_0_ip_block =
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index 60a97d1a82f2..405ccdfbafad 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -2622,18 +2622,8 @@ static const struct amdgpu_vm_pte_funcs sdma_v4_0_vm_pte_funcs = {
static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev)
{
- struct drm_gpu_scheduler *sched;
- unsigned i;
-
adev->vm_manager.vm_pte_funcs = &sdma_v4_0_vm_pte_funcs;
- for (i = 0; i < adev->sdma.num_instances; i++) {
- if (adev->sdma.has_page_queue)
- sched = &adev->sdma.instance[i].page.sched;
- else
- sched = &adev->sdma.instance[i].ring.sched;
- adev->vm_manager.vm_pte_scheds[i] = sched;
- }
- adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
+ amdgpu_sdma_set_vm_pte_scheds(adev);
}
static void sdma_v4_0_get_ras_error_count(uint32_t value,
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
index d265157bc4e1..1b2868b16859 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
@@ -2323,18 +2323,8 @@ static const struct amdgpu_vm_pte_funcs sdma_v4_4_2_vm_pte_funcs = {
static void sdma_v4_4_2_set_vm_pte_funcs(struct amdgpu_device *adev)
{
- struct drm_gpu_scheduler *sched;
- unsigned i;
-
adev->vm_manager.vm_pte_funcs = &sdma_v4_4_2_vm_pte_funcs;
- for (i = 0; i < adev->sdma.num_instances; i++) {
- if (adev->sdma.has_page_queue)
- sched = &adev->sdma.instance[i].page.sched;
- else
- sched = &adev->sdma.instance[i].ring.sched;
- adev->vm_manager.vm_pte_scheds[i] = sched;
- }
- adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
+ amdgpu_sdma_set_vm_pte_scheds(adev);
}
/**
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
index 127f001ebb5a..af920e100400 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
@@ -2081,15 +2081,9 @@ static const struct amdgpu_vm_pte_funcs sdma_v5_0_vm_pte_funcs = {
static void sdma_v5_0_set_vm_pte_funcs(struct amdgpu_device *adev)
{
- unsigned i;
-
if (adev->vm_manager.vm_pte_funcs == NULL) {
adev->vm_manager.vm_pte_funcs = &sdma_v5_0_vm_pte_funcs;
- for (i = 0; i < adev->sdma.num_instances; i++) {
- adev->vm_manager.vm_pte_scheds[i] =
- &adev->sdma.instance[i].ring.sched;
- }
- adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
+ amdgpu_sdma_set_vm_pte_scheds(adev);
}
}
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
index 78654ac3047d..29f597d56bcb 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
@@ -2091,15 +2091,9 @@ static const struct amdgpu_vm_pte_funcs sdma_v5_2_vm_pte_funcs = {
static void sdma_v5_2_set_vm_pte_funcs(struct amdgpu_device *adev)
{
- unsigned i;
-
if (adev->vm_manager.vm_pte_funcs == NULL) {
adev->vm_manager.vm_pte_funcs = &sdma_v5_2_vm_pte_funcs;
- for (i = 0; i < adev->sdma.num_instances; i++) {
- adev->vm_manager.vm_pte_scheds[i] =
- &adev->sdma.instance[i].ring.sched;
- }
- adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
+ amdgpu_sdma_set_vm_pte_scheds(adev);
}
}
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
index d1a7eb6e7ce2..03365db70d9c 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
@@ -1897,14 +1897,8 @@ static const struct amdgpu_vm_pte_funcs sdma_v6_0_vm_pte_funcs = {
static void sdma_v6_0_set_vm_pte_funcs(struct amdgpu_device *adev)
{
- unsigned i;
-
adev->vm_manager.vm_pte_funcs = &sdma_v6_0_vm_pte_funcs;
- for (i = 0; i < adev->sdma.num_instances; i++) {
- adev->vm_manager.vm_pte_scheds[i] =
- &adev->sdma.instance[i].ring.sched;
- }
- adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
+ amdgpu_sdma_set_vm_pte_scheds(adev);
}
const struct amdgpu_ip_block_version sdma_v6_0_ip_block = {
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c
index 9f15aa1df636..90d291c304d3 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c
@@ -1839,14 +1839,8 @@ static const struct amdgpu_vm_pte_funcs sdma_v7_0_vm_pte_funcs = {
static void sdma_v7_0_set_vm_pte_funcs(struct amdgpu_device *adev)
{
- unsigned i;
-
adev->vm_manager.vm_pte_funcs = &sdma_v7_0_vm_pte_funcs;
- for (i = 0; i < adev->sdma.num_instances; i++) {
- adev->vm_manager.vm_pte_scheds[i] =
- &adev->sdma.instance[i].ring.sched;
- }
- adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
+ amdgpu_sdma_set_vm_pte_scheds(adev);
}
const struct amdgpu_ip_block_version sdma_v7_0_ip_block = {
diff --git a/drivers/gpu/drm/amd/amdgpu/si_dma.c b/drivers/gpu/drm/amd/amdgpu/si_dma.c
index 621c6c17e6dd..4422aaeb99e3 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_dma.c
+++ b/drivers/gpu/drm/amd/amdgpu/si_dma.c
@@ -840,14 +840,8 @@ static const struct amdgpu_vm_pte_funcs si_dma_vm_pte_funcs = {
static void si_dma_set_vm_pte_funcs(struct amdgpu_device *adev)
{
- unsigned i;
-
adev->vm_manager.vm_pte_funcs = &si_dma_vm_pte_funcs;
- for (i = 0; i < adev->sdma.num_instances; i++) {
- adev->vm_manager.vm_pte_scheds[i] =
- &adev->sdma.instance[i].ring.sched;
- }
- adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
+ amdgpu_sdma_set_vm_pte_scheds(adev);
}
const struct amdgpu_ip_block_version si_dma_ip_block =
--
2.43.0
^ permalink raw reply [flat|nested] 40+ messages in thread* Re: [PATCH v1 15/20] drm/amdgpu: introduce amdgpu_sdma_set_vm_pte_scheds
2025-11-04 8:35 ` [PATCH v1 15/20] drm/amdgpu: introduce amdgpu_sdma_set_vm_pte_scheds Pierre-Eric Pelloux-Prayer
@ 2025-11-05 8:41 ` Christian König
0 siblings, 0 replies; 40+ messages in thread
From: Christian König @ 2025-11-05 8:41 UTC (permalink / raw)
To: Pierre-Eric Pelloux-Prayer, Alex Deucher, David Airlie, Simona Vetter
Cc: amd-gfx, dri-devel, linux-kernel
On 11/4/25 09:35, Pierre-Eric Pelloux-Prayer wrote:
> All sdma versions used the same logic, so add a helper and move the
> common code to a single place.
>
> Signed-off-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
> drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 15 +++++++++++++++
> drivers/gpu/drm/amd/amdgpu/cik_sdma.c | 8 +-------
> drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c | 8 +-------
> drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c | 8 +-------
> drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c | 12 +-----------
> drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c | 12 +-----------
> drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c | 8 +-------
> drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c | 8 +-------
> drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c | 8 +-------
> drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c | 8 +-------
> drivers/gpu/drm/amd/amdgpu/si_dma.c | 8 +-------
> 12 files changed, 26 insertions(+), 78 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index a9dc13659899..dead938a59a4 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -1614,6 +1614,7 @@ bool amdgpu_device_has_display_hardware(struct amdgpu_device *adev);
> ssize_t amdgpu_get_soft_full_reset_mask(struct amdgpu_ring *ring);
> ssize_t amdgpu_show_reset_mask(char *buf, uint32_t supported_reset);
> void amdgpu_sdma_set_buffer_funcs_rings(struct amdgpu_device *adev);
> +void amdgpu_sdma_set_vm_pte_scheds(struct amdgpu_device *adev);
>
> /* atpx handler */
> #if defined(CONFIG_VGA_SWITCHEROO)
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> index bc11e212f08c..b66e41e979ad 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> @@ -3210,3 +3210,18 @@ void amdgpu_vm_print_task_info(struct amdgpu_device *adev,
> task_info->process_name, task_info->tgid,
> task_info->task.comm, task_info->task.pid);
> }
> +
> +void amdgpu_sdma_set_vm_pte_scheds(struct amdgpu_device *adev)
Please also add the vm_pte_funcs as parameters since those should always be set at the same time as the scheduler instances.
Apart from that looks good to me.
Regards,
Christian.
> +{
> + struct drm_gpu_scheduler *sched;
> + int i;
> +
> + for (i = 0; i < adev->sdma.num_instances; i++) {
> + if (adev->sdma.has_page_queue)
> + sched = &adev->sdma.instance[i].page.sched;
> + else
> + sched = &adev->sdma.instance[i].ring.sched;
> + adev->vm_manager.vm_pte_scheds[i] = sched;
> + }
> + adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
> +}
> diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
> index 25040997c367..f2515de65597 100644
> --- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
> +++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
> @@ -1347,14 +1347,8 @@ static const struct amdgpu_vm_pte_funcs cik_sdma_vm_pte_funcs = {
>
> static void cik_sdma_set_vm_pte_funcs(struct amdgpu_device *adev)
> {
> - unsigned i;
> -
> adev->vm_manager.vm_pte_funcs = &cik_sdma_vm_pte_funcs;
> - for (i = 0; i < adev->sdma.num_instances; i++) {
> - adev->vm_manager.vm_pte_scheds[i] =
> - &adev->sdma.instance[i].ring.sched;
> - }
> - adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
> + amdgpu_sdma_set_vm_pte_scheds(adev);
> }
>
> const struct amdgpu_ip_block_version cik_sdma_ip_block =
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
> index 149356c9346a..4b2c7f75eadb 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
> @@ -1242,14 +1242,8 @@ static const struct amdgpu_vm_pte_funcs sdma_v2_4_vm_pte_funcs = {
>
> static void sdma_v2_4_set_vm_pte_funcs(struct amdgpu_device *adev)
> {
> - unsigned i;
> -
> adev->vm_manager.vm_pte_funcs = &sdma_v2_4_vm_pte_funcs;
> - for (i = 0; i < adev->sdma.num_instances; i++) {
> - adev->vm_manager.vm_pte_scheds[i] =
> - &adev->sdma.instance[i].ring.sched;
> - }
> - adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
> + amdgpu_sdma_set_vm_pte_scheds(adev);
> }
>
> const struct amdgpu_ip_block_version sdma_v2_4_ip_block = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
> index 6b538b6bd18f..fe0c855a803a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
> @@ -1684,14 +1684,8 @@ static const struct amdgpu_vm_pte_funcs sdma_v3_0_vm_pte_funcs = {
>
> static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev)
> {
> - unsigned i;
> -
> adev->vm_manager.vm_pte_funcs = &sdma_v3_0_vm_pte_funcs;
> - for (i = 0; i < adev->sdma.num_instances; i++) {
> - adev->vm_manager.vm_pte_scheds[i] =
> - &adev->sdma.instance[i].ring.sched;
> - }
> - adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
> + amdgpu_sdma_set_vm_pte_scheds(adev);
> }
>
> const struct amdgpu_ip_block_version sdma_v3_0_ip_block =
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> index 60a97d1a82f2..405ccdfbafad 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
> @@ -2622,18 +2622,8 @@ static const struct amdgpu_vm_pte_funcs sdma_v4_0_vm_pte_funcs = {
>
> static void sdma_v4_0_set_vm_pte_funcs(struct amdgpu_device *adev)
> {
> - struct drm_gpu_scheduler *sched;
> - unsigned i;
> -
> adev->vm_manager.vm_pte_funcs = &sdma_v4_0_vm_pte_funcs;
> - for (i = 0; i < adev->sdma.num_instances; i++) {
> - if (adev->sdma.has_page_queue)
> - sched = &adev->sdma.instance[i].page.sched;
> - else
> - sched = &adev->sdma.instance[i].ring.sched;
> - adev->vm_manager.vm_pte_scheds[i] = sched;
> - }
> - adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
> + amdgpu_sdma_set_vm_pte_scheds(adev);
> }
>
> static void sdma_v4_0_get_ras_error_count(uint32_t value,
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
> index d265157bc4e1..1b2868b16859 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
> @@ -2323,18 +2323,8 @@ static const struct amdgpu_vm_pte_funcs sdma_v4_4_2_vm_pte_funcs = {
>
> static void sdma_v4_4_2_set_vm_pte_funcs(struct amdgpu_device *adev)
> {
> - struct drm_gpu_scheduler *sched;
> - unsigned i;
> -
> adev->vm_manager.vm_pte_funcs = &sdma_v4_4_2_vm_pte_funcs;
> - for (i = 0; i < adev->sdma.num_instances; i++) {
> - if (adev->sdma.has_page_queue)
> - sched = &adev->sdma.instance[i].page.sched;
> - else
> - sched = &adev->sdma.instance[i].ring.sched;
> - adev->vm_manager.vm_pte_scheds[i] = sched;
> - }
> - adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
> + amdgpu_sdma_set_vm_pte_scheds(adev);
> }
>
> /**
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
> index 127f001ebb5a..af920e100400 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
> @@ -2081,15 +2081,9 @@ static const struct amdgpu_vm_pte_funcs sdma_v5_0_vm_pte_funcs = {
>
> static void sdma_v5_0_set_vm_pte_funcs(struct amdgpu_device *adev)
> {
> - unsigned i;
> -
> if (adev->vm_manager.vm_pte_funcs == NULL) {
> adev->vm_manager.vm_pte_funcs = &sdma_v5_0_vm_pte_funcs;
> - for (i = 0; i < adev->sdma.num_instances; i++) {
> - adev->vm_manager.vm_pte_scheds[i] =
> - &adev->sdma.instance[i].ring.sched;
> - }
> - adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
> + amdgpu_sdma_set_vm_pte_scheds(adev);
> }
> }
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
> index 78654ac3047d..29f597d56bcb 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
> @@ -2091,15 +2091,9 @@ static const struct amdgpu_vm_pte_funcs sdma_v5_2_vm_pte_funcs = {
>
> static void sdma_v5_2_set_vm_pte_funcs(struct amdgpu_device *adev)
> {
> - unsigned i;
> -
> if (adev->vm_manager.vm_pte_funcs == NULL) {
> adev->vm_manager.vm_pte_funcs = &sdma_v5_2_vm_pte_funcs;
> - for (i = 0; i < adev->sdma.num_instances; i++) {
> - adev->vm_manager.vm_pte_scheds[i] =
> - &adev->sdma.instance[i].ring.sched;
> - }
> - adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
> + amdgpu_sdma_set_vm_pte_scheds(adev);
> }
> }
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
> index d1a7eb6e7ce2..03365db70d9c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
> @@ -1897,14 +1897,8 @@ static const struct amdgpu_vm_pte_funcs sdma_v6_0_vm_pte_funcs = {
>
> static void sdma_v6_0_set_vm_pte_funcs(struct amdgpu_device *adev)
> {
> - unsigned i;
> -
> adev->vm_manager.vm_pte_funcs = &sdma_v6_0_vm_pte_funcs;
> - for (i = 0; i < adev->sdma.num_instances; i++) {
> - adev->vm_manager.vm_pte_scheds[i] =
> - &adev->sdma.instance[i].ring.sched;
> - }
> - adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
> + amdgpu_sdma_set_vm_pte_scheds(adev);
> }
>
> const struct amdgpu_ip_block_version sdma_v6_0_ip_block = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c
> index 9f15aa1df636..90d291c304d3 100644
> --- a/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c
> @@ -1839,14 +1839,8 @@ static const struct amdgpu_vm_pte_funcs sdma_v7_0_vm_pte_funcs = {
>
> static void sdma_v7_0_set_vm_pte_funcs(struct amdgpu_device *adev)
> {
> - unsigned i;
> -
> adev->vm_manager.vm_pte_funcs = &sdma_v7_0_vm_pte_funcs;
> - for (i = 0; i < adev->sdma.num_instances; i++) {
> - adev->vm_manager.vm_pte_scheds[i] =
> - &adev->sdma.instance[i].ring.sched;
> - }
> - adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
> + amdgpu_sdma_set_vm_pte_scheds(adev);
> }
>
> const struct amdgpu_ip_block_version sdma_v7_0_ip_block = {
> diff --git a/drivers/gpu/drm/amd/amdgpu/si_dma.c b/drivers/gpu/drm/amd/amdgpu/si_dma.c
> index 621c6c17e6dd..4422aaeb99e3 100644
> --- a/drivers/gpu/drm/amd/amdgpu/si_dma.c
> +++ b/drivers/gpu/drm/amd/amdgpu/si_dma.c
> @@ -840,14 +840,8 @@ static const struct amdgpu_vm_pte_funcs si_dma_vm_pte_funcs = {
>
> static void si_dma_set_vm_pte_funcs(struct amdgpu_device *adev)
> {
> - unsigned i;
> -
> adev->vm_manager.vm_pte_funcs = &si_dma_vm_pte_funcs;
> - for (i = 0; i < adev->sdma.num_instances; i++) {
> - adev->vm_manager.vm_pte_scheds[i] =
> - &adev->sdma.instance[i].ring.sched;
> - }
> - adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
> + amdgpu_sdma_set_vm_pte_scheds(adev);
> }
>
> const struct amdgpu_ip_block_version si_dma_ip_block =
^ permalink raw reply [flat|nested] 40+ messages in thread
* [PATCH v1 16/20] drm/amdgpu: give ttm entities access to all the sdma scheds
2025-11-04 8:35 [PATCH v1 00/20] drm/amdgpu: use all SDMA instances for TTM clears and moves Pierre-Eric Pelloux-Prayer
` (14 preceding siblings ...)
2025-11-04 8:35 ` [PATCH v1 15/20] drm/amdgpu: introduce amdgpu_sdma_set_vm_pte_scheds Pierre-Eric Pelloux-Prayer
@ 2025-11-04 8:35 ` Pierre-Eric Pelloux-Prayer
2025-11-05 8:45 ` Christian König
2025-11-04 8:35 ` [PATCH v1 17/20] drm/amdgpu: get rid of amdgpu_ttm_clear_buffer Pierre-Eric Pelloux-Prayer
` (3 subsequent siblings)
19 siblings, 1 reply; 40+ messages in thread
From: Pierre-Eric Pelloux-Prayer @ 2025-11-04 8:35 UTC (permalink / raw)
To: Alex Deucher, Christian König, David Airlie, Simona Vetter
Cc: Pierre-Eric Pelloux-Prayer, amd-gfx, dri-devel, linux-kernel
Signed-off-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 23 ++++++++++-------------
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 1 +
2 files changed, 11 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 47eaab9350ae..d88bdb2ac083 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -2187,8 +2187,8 @@ u32 amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable)
u32 num_clear_entities, num_move_entities;
u32 windows, w;
- num_clear_entities = adev->sdma.num_instances;
- num_move_entities = MIN(adev->sdma.num_instances, TTM_FENCES_MAX_SLOT_COUNT);
+ num_clear_entities = MIN(adev->mman.num_buffer_funcs_rings, TTM_FENCES_MAX_SLOT_COUNT);
+ num_move_entities = MIN(adev->mman.num_buffer_funcs_rings, TTM_FENCES_MAX_SLOT_COUNT);
man->pipelined_eviction.n_fences = num_move_entities;
windows = adev->gmc.is_app_apu ? 0 : (2 * num_move_entities + num_clear_entities);
@@ -2197,13 +2197,8 @@ u32 amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable)
return windows;
if (enable) {
- struct amdgpu_ring *ring;
- struct drm_gpu_scheduler *sched;
-
- ring = adev->mman.buffer_funcs_rings[0];
- sched = &ring->sched;
r = drm_sched_entity_init(&adev->mman.default_entity.base,
- DRM_SCHED_PRIORITY_KERNEL, &sched,
+ DRM_SCHED_PRIORITY_KERNEL, adev->mman.scheds,
1, NULL);
if (r) {
dev_err(adev->dev, "Failed setting up entity (%d)\n",
@@ -2215,8 +2210,8 @@ u32 amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable)
atomic_set(&adev->mman.next_move_entity, 0);
for (i = 0; i < num_move_entities; i++) {
r = drm_sched_entity_init(&adev->mman.move_entities[i].base,
- DRM_SCHED_PRIORITY_NORMAL, &sched,
- 1, NULL);
+ DRM_SCHED_PRIORITY_NORMAL, adev->mman.scheds,
+ adev->mman.num_buffer_funcs_rings, NULL);
if (r) {
dev_err(adev->dev,
"Failed setting up TTM BO move entities (%d)\n",
@@ -2238,8 +2233,8 @@ u32 amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable)
for (i = 0; i < num_clear_entities; i++) {
r = drm_sched_entity_init(&adev->mman.clear_entities[i].base,
- DRM_SCHED_PRIORITY_NORMAL, &sched,
- 1, NULL);
+ DRM_SCHED_PRIORITY_NORMAL, adev->mman.scheds,
+ adev->mman.num_buffer_funcs_rings, NULL);
if (r) {
for (j = 0; j < num_move_entities; j++)
drm_sched_entity_destroy(
@@ -2650,8 +2645,10 @@ void amdgpu_sdma_set_buffer_funcs_rings(struct amdgpu_device *adev)
struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)];
int i;
- for (i = 0; i < adev->sdma.num_instances; i++)
+ for (i = 0; i < adev->sdma.num_instances; i++) {
adev->mman.buffer_funcs_rings[i] = &adev->sdma.instance[i].ring;
+ adev->mman.scheds[i] = &adev->sdma.instance[i].ring.sched;
+ }
adev->mman.num_buffer_funcs_rings = hub->sdma_invalidation_workaround ?
1 : adev->sdma.num_instances;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
index d7fee371b814..c059a3d52b57 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
@@ -68,6 +68,7 @@ struct amdgpu_mman {
const struct amdgpu_buffer_funcs *buffer_funcs;
struct amdgpu_ring *buffer_funcs_rings[AMDGPU_MAX_RINGS];
u32 num_buffer_funcs_rings;
+ struct drm_gpu_scheduler *scheds[AMDGPU_MAX_RINGS];
bool buffer_funcs_enabled;
struct mutex gtt_window_lock;
--
2.43.0
^ permalink raw reply [flat|nested] 40+ messages in thread* Re: [PATCH v1 16/20] drm/amdgpu: give ttm entities access to all the sdma scheds
2025-11-04 8:35 ` [PATCH v1 16/20] drm/amdgpu: give ttm entities access to all the sdma scheds Pierre-Eric Pelloux-Prayer
@ 2025-11-05 8:45 ` Christian König
2025-11-05 10:17 ` Pierre-Eric Pelloux-Prayer
0 siblings, 1 reply; 40+ messages in thread
From: Christian König @ 2025-11-05 8:45 UTC (permalink / raw)
To: Pierre-Eric Pelloux-Prayer, Alex Deucher, David Airlie, Simona Vetter
Cc: amd-gfx, dri-devel, linux-kernel
On 11/4/25 09:35, Pierre-Eric Pelloux-Prayer wrote:
> Signed-off-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 23 ++++++++++-------------
> drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 1 +
> 2 files changed, 11 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> index 47eaab9350ae..d88bdb2ac083 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> @@ -2187,8 +2187,8 @@ u32 amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable)
> u32 num_clear_entities, num_move_entities;
> u32 windows, w;
>
> - num_clear_entities = adev->sdma.num_instances;
> - num_move_entities = MIN(adev->sdma.num_instances, TTM_FENCES_MAX_SLOT_COUNT);
> + num_clear_entities = MIN(adev->mman.num_buffer_funcs_rings, TTM_FENCES_MAX_SLOT_COUNT);
> + num_move_entities = MIN(adev->mman.num_buffer_funcs_rings, TTM_FENCES_MAX_SLOT_COUNT);
> man->pipelined_eviction.n_fences = num_move_entities;
> windows = adev->gmc.is_app_apu ? 0 : (2 * num_move_entities + num_clear_entities);
>
> @@ -2197,13 +2197,8 @@ u32 amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable)
> return windows;
>
> if (enable) {
> - struct amdgpu_ring *ring;
> - struct drm_gpu_scheduler *sched;
> -
> - ring = adev->mman.buffer_funcs_rings[0];
> - sched = &ring->sched;
> r = drm_sched_entity_init(&adev->mman.default_entity.base,
> - DRM_SCHED_PRIORITY_KERNEL, &sched,
> + DRM_SCHED_PRIORITY_KERNEL, adev->mman.scheds,
> 1, NULL);
> if (r) {
> dev_err(adev->dev, "Failed setting up entity (%d)\n",
> @@ -2215,8 +2210,8 @@ u32 amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable)
> atomic_set(&adev->mman.next_move_entity, 0);
> for (i = 0; i < num_move_entities; i++) {
> r = drm_sched_entity_init(&adev->mman.move_entities[i].base,
> - DRM_SCHED_PRIORITY_NORMAL, &sched,
> - 1, NULL);
> + DRM_SCHED_PRIORITY_NORMAL, adev->mman.scheds,
> + adev->mman.num_buffer_funcs_rings, NULL);
> if (r) {
> dev_err(adev->dev,
> "Failed setting up TTM BO move entities (%d)\n",
> @@ -2238,8 +2233,8 @@ u32 amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable)
>
> for (i = 0; i < num_clear_entities; i++) {
> r = drm_sched_entity_init(&adev->mman.clear_entities[i].base,
> - DRM_SCHED_PRIORITY_NORMAL, &sched,
> - 1, NULL);
> + DRM_SCHED_PRIORITY_NORMAL, adev->mman.scheds,
> + adev->mman.num_buffer_funcs_rings, NULL);
> if (r) {
> for (j = 0; j < num_move_entities; j++)
> drm_sched_entity_destroy(
> @@ -2650,8 +2645,10 @@ void amdgpu_sdma_set_buffer_funcs_rings(struct amdgpu_device *adev)
> struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)];
> int i;
>
> - for (i = 0; i < adev->sdma.num_instances; i++)
> + for (i = 0; i < adev->sdma.num_instances; i++) {
> adev->mman.buffer_funcs_rings[i] = &adev->sdma.instance[i].ring;
> + adev->mman.scheds[i] = &adev->sdma.instance[i].ring.sched;
> + }
>
> adev->mman.num_buffer_funcs_rings = hub->sdma_invalidation_workaround ?
> 1 : adev->sdma.num_instances;
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
> index d7fee371b814..c059a3d52b57 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
> @@ -68,6 +68,7 @@ struct amdgpu_mman {
> const struct amdgpu_buffer_funcs *buffer_funcs;
> struct amdgpu_ring *buffer_funcs_rings[AMDGPU_MAX_RINGS];
> u32 num_buffer_funcs_rings;
> + struct drm_gpu_scheduler *scheds[AMDGPU_MAX_RINGS];
That looks like you are duplicating the data of buffer_funcs_rings. Why?
Regards,
Christian.
> bool buffer_funcs_enabled;
>
> struct mutex gtt_window_lock;
^ permalink raw reply [flat|nested] 40+ messages in thread* Re: [PATCH v1 16/20] drm/amdgpu: give ttm entities access to all the sdma scheds
2025-11-05 8:45 ` Christian König
@ 2025-11-05 10:17 ` Pierre-Eric Pelloux-Prayer
0 siblings, 0 replies; 40+ messages in thread
From: Pierre-Eric Pelloux-Prayer @ 2025-11-05 10:17 UTC (permalink / raw)
To: Christian König, Pierre-Eric Pelloux-Prayer, Alex Deucher,
David Airlie, Simona Vetter
Cc: amd-gfx, dri-devel, linux-kernel
Le 05/11/2025 à 09:45, Christian König a écrit :
>
>
> On 11/4/25 09:35, Pierre-Eric Pelloux-Prayer wrote:
>> Signed-off-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
>> ---
>> drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 23 ++++++++++-------------
>> drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 1 +
>> 2 files changed, 11 insertions(+), 13 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
>> index 47eaab9350ae..d88bdb2ac083 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
>> @@ -2187,8 +2187,8 @@ u32 amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable)
>> u32 num_clear_entities, num_move_entities;
>> u32 windows, w;
>>
>> - num_clear_entities = adev->sdma.num_instances;
>> - num_move_entities = MIN(adev->sdma.num_instances, TTM_FENCES_MAX_SLOT_COUNT);
>> + num_clear_entities = MIN(adev->mman.num_buffer_funcs_rings, TTM_FENCES_MAX_SLOT_COUNT);
>> + num_move_entities = MIN(adev->mman.num_buffer_funcs_rings, TTM_FENCES_MAX_SLOT_COUNT);
>> man->pipelined_eviction.n_fences = num_move_entities;
>> windows = adev->gmc.is_app_apu ? 0 : (2 * num_move_entities + num_clear_entities);
>>
>> @@ -2197,13 +2197,8 @@ u32 amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable)
>> return windows;
>>
>> if (enable) {
>> - struct amdgpu_ring *ring;
>> - struct drm_gpu_scheduler *sched;
>> -
>> - ring = adev->mman.buffer_funcs_rings[0];
>> - sched = &ring->sched;
>> r = drm_sched_entity_init(&adev->mman.default_entity.base,
>> - DRM_SCHED_PRIORITY_KERNEL, &sched,
>> + DRM_SCHED_PRIORITY_KERNEL, adev->mman.scheds,
>> 1, NULL);
>> if (r) {
>> dev_err(adev->dev, "Failed setting up entity (%d)\n",
>> @@ -2215,8 +2210,8 @@ u32 amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable)
>> atomic_set(&adev->mman.next_move_entity, 0);
>> for (i = 0; i < num_move_entities; i++) {
>> r = drm_sched_entity_init(&adev->mman.move_entities[i].base,
>> - DRM_SCHED_PRIORITY_NORMAL, &sched,
>> - 1, NULL);
>> + DRM_SCHED_PRIORITY_NORMAL, adev->mman.scheds,
>> + adev->mman.num_buffer_funcs_rings, NULL);
>> if (r) {
>> dev_err(adev->dev,
>> "Failed setting up TTM BO move entities (%d)\n",
>> @@ -2238,8 +2233,8 @@ u32 amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable)
>>
>> for (i = 0; i < num_clear_entities; i++) {
>> r = drm_sched_entity_init(&adev->mman.clear_entities[i].base,
>> - DRM_SCHED_PRIORITY_NORMAL, &sched,
>> - 1, NULL);
>> + DRM_SCHED_PRIORITY_NORMAL, adev->mman.scheds,
>> + adev->mman.num_buffer_funcs_rings, NULL);
>> if (r) {
>> for (j = 0; j < num_move_entities; j++)
>> drm_sched_entity_destroy(
>> @@ -2650,8 +2645,10 @@ void amdgpu_sdma_set_buffer_funcs_rings(struct amdgpu_device *adev)
>> struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)];
>> int i;
>>
>> - for (i = 0; i < adev->sdma.num_instances; i++)
>> + for (i = 0; i < adev->sdma.num_instances; i++) {
>> adev->mman.buffer_funcs_rings[i] = &adev->sdma.instance[i].ring;
>> + adev->mman.scheds[i] = &adev->sdma.instance[i].ring.sched;
>> + }
>>
>> adev->mman.num_buffer_funcs_rings = hub->sdma_invalidation_workaround ?
>> 1 : adev->sdma.num_instances;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
>> index d7fee371b814..c059a3d52b57 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
>> @@ -68,6 +68,7 @@ struct amdgpu_mman {
>> const struct amdgpu_buffer_funcs *buffer_funcs;
>> struct amdgpu_ring *buffer_funcs_rings[AMDGPU_MAX_RINGS];
>> u32 num_buffer_funcs_rings;
>> + struct drm_gpu_scheduler *scheds[AMDGPU_MAX_RINGS];
>
> That looks like you are duplicating the data of buffer_funcs_rings. Why?
I need a sched array to pass to drm_sched_entity_init.
That being said, I think buffer_funcs_rings could be dropped and its users be
updated to use scheds.
Pierre-Eric
^ permalink raw reply [flat|nested] 40+ messages in thread
* [PATCH v1 17/20] drm/amdgpu: get rid of amdgpu_ttm_clear_buffer
2025-11-04 8:35 [PATCH v1 00/20] drm/amdgpu: use all SDMA instances for TTM clears and moves Pierre-Eric Pelloux-Prayer
` (15 preceding siblings ...)
2025-11-04 8:35 ` [PATCH v1 16/20] drm/amdgpu: give ttm entities access to all the sdma scheds Pierre-Eric Pelloux-Prayer
@ 2025-11-04 8:35 ` Pierre-Eric Pelloux-Prayer
2025-11-05 8:46 ` Christian König
2025-11-04 8:35 ` [PATCH v1 18/20] drm/amdgpu: rename amdgpu_fill_buffer as amdgpu_clear_buffer Pierre-Eric Pelloux-Prayer
` (2 subsequent siblings)
19 siblings, 1 reply; 40+ messages in thread
From: Pierre-Eric Pelloux-Prayer @ 2025-11-04 8:35 UTC (permalink / raw)
To: Alex Deucher, Christian König, David Airlie, Simona Vetter,
Sumit Semwal
Cc: Pierre-Eric Pelloux-Prayer, amd-gfx, dri-devel, linux-kernel,
linux-media, linaro-mm-sig
It's doing the same thing as amdgpu_fill_buffer(src_data=0), so drop it.
The only caveat is that amdgpu_res_cleared() return value is only valid
right after allocation.
Signed-off-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 9 +--
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 86 ++++------------------
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 3 -
3 files changed, 18 insertions(+), 80 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 4a69324bb730..410e9b68ff81 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -723,15 +723,10 @@ int amdgpu_bo_create(struct amdgpu_device *adev,
if (bp->flags & AMDGPU_GEM_CREATE_VRAM_CLEARED &&
bo->tbo.resource->mem_type == TTM_PL_VRAM) {
- struct dma_fence *fence;
-
- r = amdgpu_ttm_clear_buffer(bo, bo->tbo.base.resv, &fence);
+ r = amdgpu_fill_buffer(NULL, bo, 0, NULL,
+ NULL, AMDGPU_KERNEL_JOB_ID_TTM_CLEAR_BUFFER);
if (unlikely(r))
goto fail_unreserve;
-
- dma_resv_add_fence(bo->tbo.base.resv, fence,
- DMA_RESV_USAGE_KERNEL);
- dma_fence_put(fence);
}
if (!bp->resv)
amdgpu_bo_unreserve(bo);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index d88bdb2ac083..1f553c56f31d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -2412,75 +2412,6 @@ static int amdgpu_ttm_fill_mem(struct amdgpu_ring *ring,
return 0;
}
-/**
- * amdgpu_ttm_clear_buffer - clear memory buffers
- * @bo: amdgpu buffer object
- * @resv: reservation object
- * @fence: dma_fence associated with the operation
- *
- * Clear the memory buffer resource.
- *
- * Returns:
- * 0 for success or a negative error code on failure.
- */
-int amdgpu_ttm_clear_buffer(struct amdgpu_bo *bo,
- struct dma_resv *resv,
- struct dma_fence **fence)
-{
- struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
- struct amdgpu_ring *ring = adev->mman.buffer_funcs_rings[0];
- struct amdgpu_ttm_entity *entity;
- struct amdgpu_res_cursor cursor;
- u64 addr;
- int r = 0;
-
- if (!adev->mman.buffer_funcs_enabled)
- return -EINVAL;
-
- if (!fence)
- return -EINVAL;
- entity = &adev->mman.clear_entities[0];
- *fence = dma_fence_get_stub();
-
- amdgpu_res_first(bo->tbo.resource, 0, amdgpu_bo_size(bo), &cursor);
-
- mutex_lock(&entity->gart_window_lock);
- while (cursor.remaining) {
- struct dma_fence *next = NULL;
- u64 size;
-
- if (amdgpu_res_cleared(&cursor)) {
- amdgpu_res_next(&cursor, cursor.size);
- continue;
- }
-
- /* Never clear more than 256MiB at once to avoid timeouts */
- size = min(cursor.size, 256ULL << 20);
-
- r = amdgpu_ttm_map_buffer(&entity->base,
- &bo->tbo, bo->tbo.resource, &cursor,
- entity->gart_window_id1, ring, false, &size, &addr,
- NULL, NULL);
- if (r)
- goto err;
-
- r = amdgpu_ttm_fill_mem(ring, &entity->base, 0, addr, size, resv,
- &next, true,
- AMDGPU_KERNEL_JOB_ID_TTM_CLEAR_BUFFER);
- if (r)
- goto err;
-
- dma_fence_put(*fence);
- *fence = next;
-
- amdgpu_res_next(&cursor, size);
- }
-err:
- mutex_unlock(&entity->gart_window_lock);
-
- return r;
-}
-
/**
* amdgpu_fill_buffer - fill a buffer with a given value
* @entity: optional entity to use. If NULL, the clearing entities will be
@@ -2508,6 +2439,9 @@ int amdgpu_fill_buffer(struct amdgpu_ttm_entity *entity,
struct amdgpu_res_cursor dst;
uint64_t cur_size, to;
int r, e, n_fences;
+ /* The clear flag is only valid directly after allocation. */
+ bool consider_clear_flag =
+ src_data == 0 && k_job_id == AMDGPU_KERNEL_JOB_ID_TTM_CLEAR_BUFFER;
/* The fences will be either added to the resv object or the last fence
* will be returned to the caller. In the latter case, all fill jobs will
@@ -2531,6 +2465,11 @@ int amdgpu_fill_buffer(struct amdgpu_ttm_entity *entity,
while (dst.remaining) {
cur_size = min(dst.size, 256ULL << 20);
+ if (consider_clear_flag && amdgpu_res_cleared(&dst)) {
+ amdgpu_res_next(&dst, dst.size);
+ continue;
+ }
+
n_fences += 1;
amdgpu_res_next(&dst, cur_size);
}
@@ -2550,6 +2489,11 @@ int amdgpu_fill_buffer(struct amdgpu_ttm_entity *entity,
amdgpu_res_first(bo->tbo.resource, 0, amdgpu_bo_size(bo), &dst);
while (dst.remaining) {
+ if (consider_clear_flag && amdgpu_res_cleared(&dst)) {
+ amdgpu_res_next(&dst, dst.size);
+ continue;
+ }
+
/* Never fill more than 256MiB at once to avoid timeouts */
cur_size = min(dst.size, 256ULL << 20);
@@ -2574,8 +2518,10 @@ int amdgpu_fill_buffer(struct amdgpu_ttm_entity *entity,
goto error;
}
+
r = amdgpu_ttm_fill_mem(ring, &entity->base,
- src_data, to, cur_size, resv,
+ src_data, to, cur_size,
+ resv,
&fence, true, k_job_id);
if (r) {
mutex_unlock(&entity->gart_window_lock);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
index c059a3d52b57..97e73919cb0c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
@@ -182,9 +182,6 @@ int amdgpu_copy_buffer(struct amdgpu_ring *ring,
struct dma_resv *resv,
struct dma_fence **fence,
bool vm_needs_flush, uint32_t copy_flags);
-int amdgpu_ttm_clear_buffer(struct amdgpu_bo *bo,
- struct dma_resv *resv,
- struct dma_fence **fence);
int amdgpu_fill_buffer(struct amdgpu_ttm_entity *entity,
struct amdgpu_bo *bo,
uint32_t src_data,
--
2.43.0
^ permalink raw reply [flat|nested] 40+ messages in thread* Re: [PATCH v1 17/20] drm/amdgpu: get rid of amdgpu_ttm_clear_buffer
2025-11-04 8:35 ` [PATCH v1 17/20] drm/amdgpu: get rid of amdgpu_ttm_clear_buffer Pierre-Eric Pelloux-Prayer
@ 2025-11-05 8:46 ` Christian König
2025-11-05 9:30 ` Pierre-Eric Pelloux-Prayer
0 siblings, 1 reply; 40+ messages in thread
From: Christian König @ 2025-11-05 8:46 UTC (permalink / raw)
To: Pierre-Eric Pelloux-Prayer, Alex Deucher, David Airlie,
Simona Vetter, Sumit Semwal
Cc: amd-gfx, dri-devel, linux-kernel, linux-media, linaro-mm-sig
On 11/4/25 09:35, Pierre-Eric Pelloux-Prayer wrote:
> It's doing the same thing as amdgpu_fill_buffer(src_data=0), so drop it.
>
> The only caveat is that amdgpu_res_cleared() return value is only valid
> right after allocation.
>
> Signed-off-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 9 +--
> drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 86 ++++------------------
> drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 3 -
> 3 files changed, 18 insertions(+), 80 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> index 4a69324bb730..410e9b68ff81 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> @@ -723,15 +723,10 @@ int amdgpu_bo_create(struct amdgpu_device *adev,
>
> if (bp->flags & AMDGPU_GEM_CREATE_VRAM_CLEARED &&
> bo->tbo.resource->mem_type == TTM_PL_VRAM) {
> - struct dma_fence *fence;
> -
> - r = amdgpu_ttm_clear_buffer(bo, bo->tbo.base.resv, &fence);
> + r = amdgpu_fill_buffer(NULL, bo, 0, NULL,
> + NULL, AMDGPU_KERNEL_JOB_ID_TTM_CLEAR_BUFFER);
> if (unlikely(r))
> goto fail_unreserve;
> -
> - dma_resv_add_fence(bo->tbo.base.resv, fence,
> - DMA_RESV_USAGE_KERNEL);
> - dma_fence_put(fence);
> }
> if (!bp->resv)
> amdgpu_bo_unreserve(bo);
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> index d88bdb2ac083..1f553c56f31d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> @@ -2412,75 +2412,6 @@ static int amdgpu_ttm_fill_mem(struct amdgpu_ring *ring,
> return 0;
> }
>
> -/**
> - * amdgpu_ttm_clear_buffer - clear memory buffers
> - * @bo: amdgpu buffer object
> - * @resv: reservation object
> - * @fence: dma_fence associated with the operation
> - *
> - * Clear the memory buffer resource.
> - *
> - * Returns:
> - * 0 for success or a negative error code on failure.
> - */
> -int amdgpu_ttm_clear_buffer(struct amdgpu_bo *bo,
> - struct dma_resv *resv,
> - struct dma_fence **fence)
> -{
> - struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
> - struct amdgpu_ring *ring = adev->mman.buffer_funcs_rings[0];
> - struct amdgpu_ttm_entity *entity;
> - struct amdgpu_res_cursor cursor;
> - u64 addr;
> - int r = 0;
> -
> - if (!adev->mman.buffer_funcs_enabled)
> - return -EINVAL;
> -
> - if (!fence)
> - return -EINVAL;
> - entity = &adev->mman.clear_entities[0];
> - *fence = dma_fence_get_stub();
> -
> - amdgpu_res_first(bo->tbo.resource, 0, amdgpu_bo_size(bo), &cursor);
> -
> - mutex_lock(&entity->gart_window_lock);
> - while (cursor.remaining) {
> - struct dma_fence *next = NULL;
> - u64 size;
> -
> - if (amdgpu_res_cleared(&cursor)) {
> - amdgpu_res_next(&cursor, cursor.size);
> - continue;
> - }
> -
> - /* Never clear more than 256MiB at once to avoid timeouts */
> - size = min(cursor.size, 256ULL << 20);
> -
> - r = amdgpu_ttm_map_buffer(&entity->base,
> - &bo->tbo, bo->tbo.resource, &cursor,
> - entity->gart_window_id1, ring, false, &size, &addr,
> - NULL, NULL);
> - if (r)
> - goto err;
> -
> - r = amdgpu_ttm_fill_mem(ring, &entity->base, 0, addr, size, resv,
> - &next, true,
> - AMDGPU_KERNEL_JOB_ID_TTM_CLEAR_BUFFER);
> - if (r)
> - goto err;
> -
> - dma_fence_put(*fence);
> - *fence = next;
> -
> - amdgpu_res_next(&cursor, size);
> - }
> -err:
> - mutex_unlock(&entity->gart_window_lock);
> -
> - return r;
> -}
> -
> /**
> * amdgpu_fill_buffer - fill a buffer with a given value
> * @entity: optional entity to use. If NULL, the clearing entities will be
> @@ -2508,6 +2439,9 @@ int amdgpu_fill_buffer(struct amdgpu_ttm_entity *entity,
> struct amdgpu_res_cursor dst;
> uint64_t cur_size, to;
> int r, e, n_fences;
> + /* The clear flag is only valid directly after allocation. */
> + bool consider_clear_flag =
> + src_data == 0 && k_job_id == AMDGPU_KERNEL_JOB_ID_TTM_CLEAR_BUFFER;
Absolutely clear NAK to that.
Christian.
>
> /* The fences will be either added to the resv object or the last fence
> * will be returned to the caller. In the latter case, all fill jobs will
> @@ -2531,6 +2465,11 @@ int amdgpu_fill_buffer(struct amdgpu_ttm_entity *entity,
> while (dst.remaining) {
> cur_size = min(dst.size, 256ULL << 20);
>
> + if (consider_clear_flag && amdgpu_res_cleared(&dst)) {
> + amdgpu_res_next(&dst, dst.size);
> + continue;
> + }
> +
> n_fences += 1;
> amdgpu_res_next(&dst, cur_size);
> }
> @@ -2550,6 +2489,11 @@ int amdgpu_fill_buffer(struct amdgpu_ttm_entity *entity,
> amdgpu_res_first(bo->tbo.resource, 0, amdgpu_bo_size(bo), &dst);
>
> while (dst.remaining) {
> + if (consider_clear_flag && amdgpu_res_cleared(&dst)) {
> + amdgpu_res_next(&dst, dst.size);
> + continue;
> + }
> +
> /* Never fill more than 256MiB at once to avoid timeouts */
> cur_size = min(dst.size, 256ULL << 20);
>
> @@ -2574,8 +2518,10 @@ int amdgpu_fill_buffer(struct amdgpu_ttm_entity *entity,
> goto error;
> }
>
> +
> r = amdgpu_ttm_fill_mem(ring, &entity->base,
> - src_data, to, cur_size, resv,
> + src_data, to, cur_size,
> + resv,
> &fence, true, k_job_id);
> if (r) {
> mutex_unlock(&entity->gart_window_lock);
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
> index c059a3d52b57..97e73919cb0c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
> @@ -182,9 +182,6 @@ int amdgpu_copy_buffer(struct amdgpu_ring *ring,
> struct dma_resv *resv,
> struct dma_fence **fence,
> bool vm_needs_flush, uint32_t copy_flags);
> -int amdgpu_ttm_clear_buffer(struct amdgpu_bo *bo,
> - struct dma_resv *resv,
> - struct dma_fence **fence);
> int amdgpu_fill_buffer(struct amdgpu_ttm_entity *entity,
> struct amdgpu_bo *bo,
> uint32_t src_data,
^ permalink raw reply [flat|nested] 40+ messages in thread* Re: [PATCH v1 17/20] drm/amdgpu: get rid of amdgpu_ttm_clear_buffer
2025-11-05 8:46 ` Christian König
@ 2025-11-05 9:30 ` Pierre-Eric Pelloux-Prayer
2025-11-05 10:07 ` Christian König
0 siblings, 1 reply; 40+ messages in thread
From: Pierre-Eric Pelloux-Prayer @ 2025-11-05 9:30 UTC (permalink / raw)
To: Christian König, Pierre-Eric Pelloux-Prayer, Alex Deucher,
David Airlie, Simona Vetter, Sumit Semwal
Cc: amd-gfx, dri-devel, linux-kernel, linux-media, linaro-mm-sig
Le 05/11/2025 à 09:46, Christian König a écrit :
>
>
> On 11/4/25 09:35, Pierre-Eric Pelloux-Prayer wrote:
>> It's doing the same thing as amdgpu_fill_buffer(src_data=0), so drop it.
>>
>> The only caveat is that amdgpu_res_cleared() return value is only valid
>> right after allocation.
>>
>> Signed-off-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
>> ---
>> drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 9 +--
>> drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 86 ++++------------------
>> drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 3 -
>> 3 files changed, 18 insertions(+), 80 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
>> index 4a69324bb730..410e9b68ff81 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
>> @@ -723,15 +723,10 @@ int amdgpu_bo_create(struct amdgpu_device *adev,
>>
>> if (bp->flags & AMDGPU_GEM_CREATE_VRAM_CLEARED &&
>> bo->tbo.resource->mem_type == TTM_PL_VRAM) {
>> - struct dma_fence *fence;
>> -
>> - r = amdgpu_ttm_clear_buffer(bo, bo->tbo.base.resv, &fence);
>> + r = amdgpu_fill_buffer(NULL, bo, 0, NULL,
>> + NULL, AMDGPU_KERNEL_JOB_ID_TTM_CLEAR_BUFFER);
>> if (unlikely(r))
>> goto fail_unreserve;
>> -
>> - dma_resv_add_fence(bo->tbo.base.resv, fence,
>> - DMA_RESV_USAGE_KERNEL);
>> - dma_fence_put(fence);
>> }
>> if (!bp->resv)
>> amdgpu_bo_unreserve(bo);
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
>> index d88bdb2ac083..1f553c56f31d 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
>> @@ -2412,75 +2412,6 @@ static int amdgpu_ttm_fill_mem(struct amdgpu_ring *ring,
>> return 0;
>> }
>>
>> -/**
>> - * amdgpu_ttm_clear_buffer - clear memory buffers
>> - * @bo: amdgpu buffer object
>> - * @resv: reservation object
>> - * @fence: dma_fence associated with the operation
>> - *
>> - * Clear the memory buffer resource.
>> - *
>> - * Returns:
>> - * 0 for success or a negative error code on failure.
>> - */
>> -int amdgpu_ttm_clear_buffer(struct amdgpu_bo *bo,
>> - struct dma_resv *resv,
>> - struct dma_fence **fence)
>> -{
>> - struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
>> - struct amdgpu_ring *ring = adev->mman.buffer_funcs_rings[0];
>> - struct amdgpu_ttm_entity *entity;
>> - struct amdgpu_res_cursor cursor;
>> - u64 addr;
>> - int r = 0;
>> -
>> - if (!adev->mman.buffer_funcs_enabled)
>> - return -EINVAL;
>> -
>> - if (!fence)
>> - return -EINVAL;
>> - entity = &adev->mman.clear_entities[0];
>> - *fence = dma_fence_get_stub();
>> -
>> - amdgpu_res_first(bo->tbo.resource, 0, amdgpu_bo_size(bo), &cursor);
>> -
>> - mutex_lock(&entity->gart_window_lock);
>> - while (cursor.remaining) {
>> - struct dma_fence *next = NULL;
>> - u64 size;
>> -
>> - if (amdgpu_res_cleared(&cursor)) {
>> - amdgpu_res_next(&cursor, cursor.size);
>> - continue;
>> - }
>> -
>> - /* Never clear more than 256MiB at once to avoid timeouts */
>> - size = min(cursor.size, 256ULL << 20);
>> -
>> - r = amdgpu_ttm_map_buffer(&entity->base,
>> - &bo->tbo, bo->tbo.resource, &cursor,
>> - entity->gart_window_id1, ring, false, &size, &addr,
>> - NULL, NULL);
>> - if (r)
>> - goto err;
>> -
>> - r = amdgpu_ttm_fill_mem(ring, &entity->base, 0, addr, size, resv,
>> - &next, true,
>> - AMDGPU_KERNEL_JOB_ID_TTM_CLEAR_BUFFER);
>> - if (r)
>> - goto err;
>> -
>> - dma_fence_put(*fence);
>> - *fence = next;
>> -
>> - amdgpu_res_next(&cursor, size);
>> - }
>> -err:
>> - mutex_unlock(&entity->gart_window_lock);
>> -
>> - return r;
>> -}
>> -
>> /**
>> * amdgpu_fill_buffer - fill a buffer with a given value
>> * @entity: optional entity to use. If NULL, the clearing entities will be
>> @@ -2508,6 +2439,9 @@ int amdgpu_fill_buffer(struct amdgpu_ttm_entity *entity,
>> struct amdgpu_res_cursor dst;
>> uint64_t cur_size, to;
>> int r, e, n_fences;
>
>> + /* The clear flag is only valid directly after allocation. */
>> + bool consider_clear_flag =
>> + src_data == 0 && k_job_id == AMDGPU_KERNEL_JOB_ID_TTM_CLEAR_BUFFER;
>
> Absolutely clear NAK to that.
I suppose the NAK applies to the check, not the general idea of the patch?
In that case, would passing "bool consider_clear_flag" as a parameter be ok ?
Pierre-Eric
>
> Christian.
>
>>
>> /* The fences will be either added to the resv object or the last fence
>> * will be returned to the caller. In the latter case, all fill jobs will
>> @@ -2531,6 +2465,11 @@ int amdgpu_fill_buffer(struct amdgpu_ttm_entity *entity,
>> while (dst.remaining) {
>> cur_size = min(dst.size, 256ULL << 20);
>>
>> + if (consider_clear_flag && amdgpu_res_cleared(&dst)) {
>> + amdgpu_res_next(&dst, dst.size);
>> + continue;
>> + }
>> +
>> n_fences += 1;
>> amdgpu_res_next(&dst, cur_size);
>> }
>> @@ -2550,6 +2489,11 @@ int amdgpu_fill_buffer(struct amdgpu_ttm_entity *entity,
>> amdgpu_res_first(bo->tbo.resource, 0, amdgpu_bo_size(bo), &dst);
>>
>> while (dst.remaining) {
>> + if (consider_clear_flag && amdgpu_res_cleared(&dst)) {
>> + amdgpu_res_next(&dst, dst.size);
>> + continue;
>> + }
>> +
>> /* Never fill more than 256MiB at once to avoid timeouts */
>> cur_size = min(dst.size, 256ULL << 20);
>>
>> @@ -2574,8 +2518,10 @@ int amdgpu_fill_buffer(struct amdgpu_ttm_entity *entity,
>> goto error;
>> }
>>
>> +
>> r = amdgpu_ttm_fill_mem(ring, &entity->base,
>> - src_data, to, cur_size, resv,
>> + src_data, to, cur_size,
>> + resv,
>> &fence, true, k_job_id);
>> if (r) {
>> mutex_unlock(&entity->gart_window_lock);
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
>> index c059a3d52b57..97e73919cb0c 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
>> @@ -182,9 +182,6 @@ int amdgpu_copy_buffer(struct amdgpu_ring *ring,
>> struct dma_resv *resv,
>> struct dma_fence **fence,
>> bool vm_needs_flush, uint32_t copy_flags);
>> -int amdgpu_ttm_clear_buffer(struct amdgpu_bo *bo,
>> - struct dma_resv *resv,
>> - struct dma_fence **fence);
>> int amdgpu_fill_buffer(struct amdgpu_ttm_entity *entity,
>> struct amdgpu_bo *bo,
>> uint32_t src_data,
^ permalink raw reply [flat|nested] 40+ messages in thread* Re: [PATCH v1 17/20] drm/amdgpu: get rid of amdgpu_ttm_clear_buffer
2025-11-05 9:30 ` Pierre-Eric Pelloux-Prayer
@ 2025-11-05 10:07 ` Christian König
0 siblings, 0 replies; 40+ messages in thread
From: Christian König @ 2025-11-05 10:07 UTC (permalink / raw)
To: Pierre-Eric Pelloux-Prayer, Pierre-Eric Pelloux-Prayer,
Alex Deucher, David Airlie, Simona Vetter, Sumit Semwal
Cc: amd-gfx, dri-devel, linux-kernel, linux-media, linaro-mm-sig
On 11/5/25 10:30, Pierre-Eric Pelloux-Prayer wrote:
>
>
> Le 05/11/2025 à 09:46, Christian König a écrit :
>>
>>
>> On 11/4/25 09:35, Pierre-Eric Pelloux-Prayer wrote:
>>> It's doing the same thing as amdgpu_fill_buffer(src_data=0), so drop it.
>>>
>>> The only caveat is that amdgpu_res_cleared() return value is only valid
>>> right after allocation.
>>>
>>> Signed-off-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
>>> ---
>>> drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 9 +--
>>> drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 86 ++++------------------
>>> drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 3 -
>>> 3 files changed, 18 insertions(+), 80 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
>>> index 4a69324bb730..410e9b68ff81 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
>>> @@ -723,15 +723,10 @@ int amdgpu_bo_create(struct amdgpu_device *adev,
>>> if (bp->flags & AMDGPU_GEM_CREATE_VRAM_CLEARED &&
>>> bo->tbo.resource->mem_type == TTM_PL_VRAM) {
>>> - struct dma_fence *fence;
>>> -
>>> - r = amdgpu_ttm_clear_buffer(bo, bo->tbo.base.resv, &fence);
>>> + r = amdgpu_fill_buffer(NULL, bo, 0, NULL,
>>> + NULL, AMDGPU_KERNEL_JOB_ID_TTM_CLEAR_BUFFER);
>>> if (unlikely(r))
>>> goto fail_unreserve;
>>> -
>>> - dma_resv_add_fence(bo->tbo.base.resv, fence,
>>> - DMA_RESV_USAGE_KERNEL);
>>> - dma_fence_put(fence);
>>> }
>>> if (!bp->resv)
>>> amdgpu_bo_unreserve(bo);
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
>>> index d88bdb2ac083..1f553c56f31d 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
>>> @@ -2412,75 +2412,6 @@ static int amdgpu_ttm_fill_mem(struct amdgpu_ring *ring,
>>> return 0;
>>> }
>>> -/**
>>> - * amdgpu_ttm_clear_buffer - clear memory buffers
>>> - * @bo: amdgpu buffer object
>>> - * @resv: reservation object
>>> - * @fence: dma_fence associated with the operation
>>> - *
>>> - * Clear the memory buffer resource.
>>> - *
>>> - * Returns:
>>> - * 0 for success or a negative error code on failure.
>>> - */
>>> -int amdgpu_ttm_clear_buffer(struct amdgpu_bo *bo,
>>> - struct dma_resv *resv,
>>> - struct dma_fence **fence)
>>> -{
>>> - struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
>>> - struct amdgpu_ring *ring = adev->mman.buffer_funcs_rings[0];
>>> - struct amdgpu_ttm_entity *entity;
>>> - struct amdgpu_res_cursor cursor;
>>> - u64 addr;
>>> - int r = 0;
>>> -
>>> - if (!adev->mman.buffer_funcs_enabled)
>>> - return -EINVAL;
>>> -
>>> - if (!fence)
>>> - return -EINVAL;
>>> - entity = &adev->mman.clear_entities[0];
>>> - *fence = dma_fence_get_stub();
>>> -
>>> - amdgpu_res_first(bo->tbo.resource, 0, amdgpu_bo_size(bo), &cursor);
>>> -
>>> - mutex_lock(&entity->gart_window_lock);
>>> - while (cursor.remaining) {
>>> - struct dma_fence *next = NULL;
>>> - u64 size;
>>> -
>>> - if (amdgpu_res_cleared(&cursor)) {
>>> - amdgpu_res_next(&cursor, cursor.size);
>>> - continue;
>>> - }
>>> -
>>> - /* Never clear more than 256MiB at once to avoid timeouts */
>>> - size = min(cursor.size, 256ULL << 20);
>>> -
>>> - r = amdgpu_ttm_map_buffer(&entity->base,
>>> - &bo->tbo, bo->tbo.resource, &cursor,
>>> - entity->gart_window_id1, ring, false, &size, &addr,
>>> - NULL, NULL);
>>> - if (r)
>>> - goto err;
>>> -
>>> - r = amdgpu_ttm_fill_mem(ring, &entity->base, 0, addr, size, resv,
>>> - &next, true,
>>> - AMDGPU_KERNEL_JOB_ID_TTM_CLEAR_BUFFER);
>>> - if (r)
>>> - goto err;
>>> -
>>> - dma_fence_put(*fence);
>>> - *fence = next;
>>> -
>>> - amdgpu_res_next(&cursor, size);
>>> - }
>>> -err:
>>> - mutex_unlock(&entity->gart_window_lock);
>>> -
>>> - return r;
>>> -}
>>> -
>>> /**
>>> * amdgpu_fill_buffer - fill a buffer with a given value
>>> * @entity: optional entity to use. If NULL, the clearing entities will be
>>> @@ -2508,6 +2439,9 @@ int amdgpu_fill_buffer(struct amdgpu_ttm_entity *entity,
>>> struct amdgpu_res_cursor dst;
>>> uint64_t cur_size, to;
>>> int r, e, n_fences;
>>
>>> + /* The clear flag is only valid directly after allocation. */
>>> + bool consider_clear_flag =
>>> + src_data == 0 && k_job_id == AMDGPU_KERNEL_JOB_ID_TTM_CLEAR_BUFFER;
>>
>> Absolutely clear NAK to that.
>
> I suppose the NAK applies to the check, not the general idea of the patch?
Correct.
> In that case, would passing "bool consider_clear_flag" as a parameter be ok ?
And then determining the k_job_id based on this new flag? Yeah, that sounds much cleaner.
Christian.
>
> Pierre-Eric
>
>>
>> Christian.
>>
>>> /* The fences will be either added to the resv object or the last fence
>>> * will be returned to the caller. In the latter case, all fill jobs will
>>> @@ -2531,6 +2465,11 @@ int amdgpu_fill_buffer(struct amdgpu_ttm_entity *entity,
>>> while (dst.remaining) {
>>> cur_size = min(dst.size, 256ULL << 20);
>>> + if (consider_clear_flag && amdgpu_res_cleared(&dst)) {
>>> + amdgpu_res_next(&dst, dst.size);
>>> + continue;
>>> + }
>>> +
>>> n_fences += 1;
>>> amdgpu_res_next(&dst, cur_size);
>>> }
>>> @@ -2550,6 +2489,11 @@ int amdgpu_fill_buffer(struct amdgpu_ttm_entity *entity,
>>> amdgpu_res_first(bo->tbo.resource, 0, amdgpu_bo_size(bo), &dst);
>>> while (dst.remaining) {
>>> + if (consider_clear_flag && amdgpu_res_cleared(&dst)) {
>>> + amdgpu_res_next(&dst, dst.size);
>>> + continue;
>>> + }
>>> +
>>> /* Never fill more than 256MiB at once to avoid timeouts */
>>> cur_size = min(dst.size, 256ULL << 20);
>>> @@ -2574,8 +2518,10 @@ int amdgpu_fill_buffer(struct amdgpu_ttm_entity *entity,
>>> goto error;
>>> }
>>> +
>>> r = amdgpu_ttm_fill_mem(ring, &entity->base,
>>> - src_data, to, cur_size, resv,
>>> + src_data, to, cur_size,
>>> + resv,
>>> &fence, true, k_job_id);
>>> if (r) {
>>> mutex_unlock(&entity->gart_window_lock);
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
>>> index c059a3d52b57..97e73919cb0c 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
>>> @@ -182,9 +182,6 @@ int amdgpu_copy_buffer(struct amdgpu_ring *ring,
>>> struct dma_resv *resv,
>>> struct dma_fence **fence,
>>> bool vm_needs_flush, uint32_t copy_flags);
>>> -int amdgpu_ttm_clear_buffer(struct amdgpu_bo *bo,
>>> - struct dma_resv *resv,
>>> - struct dma_fence **fence);
>>> int amdgpu_fill_buffer(struct amdgpu_ttm_entity *entity,
>>> struct amdgpu_bo *bo,
>>> uint32_t src_data,
^ permalink raw reply [flat|nested] 40+ messages in thread
* [PATCH v1 18/20] drm/amdgpu: rename amdgpu_fill_buffer as amdgpu_clear_buffer
2025-11-04 8:35 [PATCH v1 00/20] drm/amdgpu: use all SDMA instances for TTM clears and moves Pierre-Eric Pelloux-Prayer
` (16 preceding siblings ...)
2025-11-04 8:35 ` [PATCH v1 17/20] drm/amdgpu: get rid of amdgpu_ttm_clear_buffer Pierre-Eric Pelloux-Prayer
@ 2025-11-04 8:35 ` Pierre-Eric Pelloux-Prayer
2025-11-05 8:47 ` Christian König
2025-11-04 8:35 ` [PATCH v1 19/20] drm/amdgpu: use larger gart window when possible Pierre-Eric Pelloux-Prayer
2025-11-04 8:35 ` [PATCH v1 20/20] drm/amdgpu: double AMDGPU_GTT_MAX_TRANSFER_SIZE Pierre-Eric Pelloux-Prayer
19 siblings, 1 reply; 40+ messages in thread
From: Pierre-Eric Pelloux-Prayer @ 2025-11-04 8:35 UTC (permalink / raw)
To: Alex Deucher, Christian König, David Airlie, Simona Vetter,
Sumit Semwal
Cc: Pierre-Eric Pelloux-Prayer, amd-gfx, dri-devel, linux-kernel,
linux-media, linaro-mm-sig
This is the only use case for this function.
Signed-off-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 8 +++----
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 25 ++++++++++------------
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 11 +++++-----
3 files changed, 20 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index 410e9b68ff81..9dc262cac39f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -723,8 +723,8 @@ int amdgpu_bo_create(struct amdgpu_device *adev,
if (bp->flags & AMDGPU_GEM_CREATE_VRAM_CLEARED &&
bo->tbo.resource->mem_type == TTM_PL_VRAM) {
- r = amdgpu_fill_buffer(NULL, bo, 0, NULL,
- NULL, AMDGPU_KERNEL_JOB_ID_TTM_CLEAR_BUFFER);
+ r = amdgpu_clear_buffer(NULL, bo, NULL,
+ NULL, AMDGPU_KERNEL_JOB_ID_TTM_CLEAR_BUFFER);
if (unlikely(r))
goto fail_unreserve;
}
@@ -1311,8 +1311,8 @@ void amdgpu_bo_release_notify(struct ttm_buffer_object *bo)
adev->in_suspend || drm_dev_is_unplugged(adev_to_drm(adev)))
goto out;
- r = amdgpu_fill_buffer(NULL, abo, 0, NULL,
- NULL, AMDGPU_KERNEL_JOB_ID_CLEAR_ON_RELEASE);
+ r = amdgpu_clear_buffer(NULL, abo, NULL,
+ NULL, AMDGPU_KERNEL_JOB_ID_CLEAR_ON_RELEASE);
if (WARN_ON(r))
goto out;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 1f553c56f31d..ac2857314d68 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -431,9 +431,9 @@ static int amdgpu_move_blit(struct ttm_buffer_object *bo,
(abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE)) {
struct dma_fence *wipe_fence = NULL;
- r = amdgpu_fill_buffer(entity,
- abo, 0, &wipe_fence, fence,
- AMDGPU_KERNEL_JOB_ID_MOVE_BLIT);
+ r = amdgpu_clear_buffer(entity,
+ abo, &wipe_fence, fence,
+ AMDGPU_KERNEL_JOB_ID_MOVE_BLIT);
if (r) {
goto error;
} else if (wipe_fence) {
@@ -2413,23 +2413,21 @@ static int amdgpu_ttm_fill_mem(struct amdgpu_ring *ring,
}
/**
- * amdgpu_fill_buffer - fill a buffer with a given value
+ * amdgpu_clear_buffer - fill a buffer with 0
* @entity: optional entity to use. If NULL, the clearing entities will be
* used to load-balance the partial clears
* @bo: the bo to fill
- * @src_data: the value to set
* @f: optional out fence. If @entity is NULL, this must be NULL and the
* fences from each partial clear will be added to the &dma_resv.
* @dependency: optional input dependency fence.
* @k_job_id: trace id
*
*/
-int amdgpu_fill_buffer(struct amdgpu_ttm_entity *entity,
- struct amdgpu_bo *bo,
- uint32_t src_data,
- struct dma_fence **f,
- struct dma_fence *dependency,
- u64 k_job_id)
+int amdgpu_clear_buffer(struct amdgpu_ttm_entity *entity,
+ struct amdgpu_bo *bo,
+ struct dma_fence **f,
+ struct dma_fence *dependency,
+ u64 k_job_id)
{
struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
struct amdgpu_ring *ring = adev->mman.buffer_funcs_rings[0];
@@ -2440,8 +2438,7 @@ int amdgpu_fill_buffer(struct amdgpu_ttm_entity *entity,
uint64_t cur_size, to;
int r, e, n_fences;
/* The clear flag is only valid directly after allocation. */
- bool consider_clear_flag =
- src_data == 0 && k_job_id == AMDGPU_KERNEL_JOB_ID_TTM_CLEAR_BUFFER;
+ bool consider_clear_flag = k_job_id == AMDGPU_KERNEL_JOB_ID_TTM_CLEAR_BUFFER;
/* The fences will be either added to the resv object or the last fence
* will be returned to the caller. In the latter case, all fill jobs will
@@ -2520,7 +2517,7 @@ int amdgpu_fill_buffer(struct amdgpu_ttm_entity *entity,
r = amdgpu_ttm_fill_mem(ring, &entity->base,
- src_data, to, cur_size,
+ 0, to, cur_size,
resv,
&fence, true, k_job_id);
if (r) {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
index 97e73919cb0c..b685bf207e43 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
@@ -182,12 +182,11 @@ int amdgpu_copy_buffer(struct amdgpu_ring *ring,
struct dma_resv *resv,
struct dma_fence **fence,
bool vm_needs_flush, uint32_t copy_flags);
-int amdgpu_fill_buffer(struct amdgpu_ttm_entity *entity,
- struct amdgpu_bo *bo,
- uint32_t src_data,
- struct dma_fence **f,
- struct dma_fence *dependency,
- u64 k_job_id);
+int amdgpu_clear_buffer(struct amdgpu_ttm_entity *entity,
+ struct amdgpu_bo *bo,
+ struct dma_fence **f,
+ struct dma_fence *dependency,
+ u64 k_job_id);
int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo);
void amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo);
--
2.43.0
^ permalink raw reply [flat|nested] 40+ messages in thread* Re: [PATCH v1 18/20] drm/amdgpu: rename amdgpu_fill_buffer as amdgpu_clear_buffer
2025-11-04 8:35 ` [PATCH v1 18/20] drm/amdgpu: rename amdgpu_fill_buffer as amdgpu_clear_buffer Pierre-Eric Pelloux-Prayer
@ 2025-11-05 8:47 ` Christian König
0 siblings, 0 replies; 40+ messages in thread
From: Christian König @ 2025-11-05 8:47 UTC (permalink / raw)
To: Pierre-Eric Pelloux-Prayer, Alex Deucher, David Airlie,
Simona Vetter, Sumit Semwal
Cc: amd-gfx, dri-devel, linux-kernel, linux-media, linaro-mm-sig
On 11/4/25 09:35, Pierre-Eric Pelloux-Prayer wrote:
> This is the only use case for this function.
amdgpu_ttm_clear_buffer please, but apart from that looks good to me.
Regards,
Christian.
>
> Signed-off-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_object.c | 8 +++----
> drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 25 ++++++++++------------
> drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 11 +++++-----
> 3 files changed, 20 insertions(+), 24 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> index 410e9b68ff81..9dc262cac39f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
> @@ -723,8 +723,8 @@ int amdgpu_bo_create(struct amdgpu_device *adev,
>
> if (bp->flags & AMDGPU_GEM_CREATE_VRAM_CLEARED &&
> bo->tbo.resource->mem_type == TTM_PL_VRAM) {
> - r = amdgpu_fill_buffer(NULL, bo, 0, NULL,
> - NULL, AMDGPU_KERNEL_JOB_ID_TTM_CLEAR_BUFFER);
> + r = amdgpu_clear_buffer(NULL, bo, NULL,
> + NULL, AMDGPU_KERNEL_JOB_ID_TTM_CLEAR_BUFFER);
> if (unlikely(r))
> goto fail_unreserve;
> }
> @@ -1311,8 +1311,8 @@ void amdgpu_bo_release_notify(struct ttm_buffer_object *bo)
> adev->in_suspend || drm_dev_is_unplugged(adev_to_drm(adev)))
> goto out;
>
> - r = amdgpu_fill_buffer(NULL, abo, 0, NULL,
> - NULL, AMDGPU_KERNEL_JOB_ID_CLEAR_ON_RELEASE);
> + r = amdgpu_clear_buffer(NULL, abo, NULL,
> + NULL, AMDGPU_KERNEL_JOB_ID_CLEAR_ON_RELEASE);
> if (WARN_ON(r))
> goto out;
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> index 1f553c56f31d..ac2857314d68 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> @@ -431,9 +431,9 @@ static int amdgpu_move_blit(struct ttm_buffer_object *bo,
> (abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE)) {
> struct dma_fence *wipe_fence = NULL;
>
> - r = amdgpu_fill_buffer(entity,
> - abo, 0, &wipe_fence, fence,
> - AMDGPU_KERNEL_JOB_ID_MOVE_BLIT);
> + r = amdgpu_clear_buffer(entity,
> + abo, &wipe_fence, fence,
> + AMDGPU_KERNEL_JOB_ID_MOVE_BLIT);
> if (r) {
> goto error;
> } else if (wipe_fence) {
> @@ -2413,23 +2413,21 @@ static int amdgpu_ttm_fill_mem(struct amdgpu_ring *ring,
> }
>
> /**
> - * amdgpu_fill_buffer - fill a buffer with a given value
> + * amdgpu_clear_buffer - fill a buffer with 0
> * @entity: optional entity to use. If NULL, the clearing entities will be
> * used to load-balance the partial clears
> * @bo: the bo to fill
> - * @src_data: the value to set
> * @f: optional out fence. If @entity is NULL, this must be NULL and the
> * fences from each partial clear will be added to the &dma_resv.
> * @dependency: optional input dependency fence.
> * @k_job_id: trace id
> *
> */
> -int amdgpu_fill_buffer(struct amdgpu_ttm_entity *entity,
> - struct amdgpu_bo *bo,
> - uint32_t src_data,
> - struct dma_fence **f,
> - struct dma_fence *dependency,
> - u64 k_job_id)
> +int amdgpu_clear_buffer(struct amdgpu_ttm_entity *entity,
> + struct amdgpu_bo *bo,
> + struct dma_fence **f,
> + struct dma_fence *dependency,
> + u64 k_job_id)
> {
> struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
> struct amdgpu_ring *ring = adev->mman.buffer_funcs_rings[0];
> @@ -2440,8 +2438,7 @@ int amdgpu_fill_buffer(struct amdgpu_ttm_entity *entity,
> uint64_t cur_size, to;
> int r, e, n_fences;
> /* The clear flag is only valid directly after allocation. */
> - bool consider_clear_flag =
> - src_data == 0 && k_job_id == AMDGPU_KERNEL_JOB_ID_TTM_CLEAR_BUFFER;
> + bool consider_clear_flag = k_job_id == AMDGPU_KERNEL_JOB_ID_TTM_CLEAR_BUFFER;
>
> /* The fences will be either added to the resv object or the last fence
> * will be returned to the caller. In the latter case, all fill jobs will
> @@ -2520,7 +2517,7 @@ int amdgpu_fill_buffer(struct amdgpu_ttm_entity *entity,
>
>
> r = amdgpu_ttm_fill_mem(ring, &entity->base,
> - src_data, to, cur_size,
> + 0, to, cur_size,
> resv,
> &fence, true, k_job_id);
> if (r) {
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
> index 97e73919cb0c..b685bf207e43 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
> @@ -182,12 +182,11 @@ int amdgpu_copy_buffer(struct amdgpu_ring *ring,
> struct dma_resv *resv,
> struct dma_fence **fence,
> bool vm_needs_flush, uint32_t copy_flags);
> -int amdgpu_fill_buffer(struct amdgpu_ttm_entity *entity,
> - struct amdgpu_bo *bo,
> - uint32_t src_data,
> - struct dma_fence **f,
> - struct dma_fence *dependency,
> - u64 k_job_id);
> +int amdgpu_clear_buffer(struct amdgpu_ttm_entity *entity,
> + struct amdgpu_bo *bo,
> + struct dma_fence **f,
> + struct dma_fence *dependency,
> + u64 k_job_id);
>
> int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo);
> void amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo);
^ permalink raw reply [flat|nested] 40+ messages in thread
* [PATCH v1 19/20] drm/amdgpu: use larger gart window when possible
2025-11-04 8:35 [PATCH v1 00/20] drm/amdgpu: use all SDMA instances for TTM clears and moves Pierre-Eric Pelloux-Prayer
` (17 preceding siblings ...)
2025-11-04 8:35 ` [PATCH v1 18/20] drm/amdgpu: rename amdgpu_fill_buffer as amdgpu_clear_buffer Pierre-Eric Pelloux-Prayer
@ 2025-11-04 8:35 ` Pierre-Eric Pelloux-Prayer
2025-11-04 8:35 ` [PATCH v1 20/20] drm/amdgpu: double AMDGPU_GTT_MAX_TRANSFER_SIZE Pierre-Eric Pelloux-Prayer
19 siblings, 0 replies; 40+ messages in thread
From: Pierre-Eric Pelloux-Prayer @ 2025-11-04 8:35 UTC (permalink / raw)
To: Alex Deucher, Christian König, David Airlie, Simona Vetter
Cc: Pierre-Eric Pelloux-Prayer, amd-gfx, dri-devel, linux-kernel
Entities' gart windows are contiguous so when copying a buffer
and src doesn't need a gart window, its window can be used to
extend dst one (and vice versa).
This doubles the gart window size and reduces the number of jobs
required.
Signed-off-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 85 ++++++++++++++++++-------
1 file changed, 63 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index ac2857314d68..3bfdce1ef5c8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -162,6 +162,23 @@ static void amdgpu_evict_flags(struct ttm_buffer_object *bo,
*placement = abo->placement;
}
+static bool amdgpu_ttm_needs_gart_window(struct amdgpu_ring *ring,
+ struct ttm_resource *mem,
+ struct amdgpu_res_cursor *mm_cur,
+ bool tmz,
+ uint64_t *addr)
+{
+ struct amdgpu_device *adev = ring->adev;
+
+ /* Map only what can't be accessed directly */
+ if (!tmz && mem->start != AMDGPU_BO_INVALID_OFFSET) {
+ *addr = amdgpu_ttm_domain_start(adev, mem->mem_type) +
+ mm_cur->start;
+ return false;
+ }
+ return true;
+}
+
/**
* amdgpu_ttm_map_buffer - Map memory into the GART windows
* @entity: entity to run the window setup job
@@ -169,6 +186,7 @@ static void amdgpu_evict_flags(struct ttm_buffer_object *bo,
* @mem: memory object to map
* @mm_cur: range to map
* @window: which GART window to use
+ * @use_two_windows: if true, use a double window
* @ring: DMA ring to use for the copy
* @tmz: if we should setup a TMZ enabled mapping
* @size: in number of bytes to map, out number of bytes mapped
@@ -182,7 +200,9 @@ static int amdgpu_ttm_map_buffer(struct drm_sched_entity *entity,
struct ttm_buffer_object *bo,
struct ttm_resource *mem,
struct amdgpu_res_cursor *mm_cur,
- unsigned int window, struct amdgpu_ring *ring,
+ unsigned int window,
+ bool use_two_windows,
+ struct amdgpu_ring *ring,
bool tmz, uint64_t *size, uint64_t *addr,
struct dma_fence *dep,
struct dma_resv *resv)
@@ -202,13 +222,8 @@ static int amdgpu_ttm_map_buffer(struct drm_sched_entity *entity,
if (WARN_ON(mem->mem_type == AMDGPU_PL_PREEMPT))
return -EINVAL;
- /* Map only what can't be accessed directly */
- if (!tmz && mem->start != AMDGPU_BO_INVALID_OFFSET) {
- *addr = amdgpu_ttm_domain_start(adev, mem->mem_type) +
- mm_cur->start;
+ if (!amdgpu_ttm_needs_gart_window(ring, mem, mm_cur, tmz, addr))
return 0;
- }
-
/*
* If start begins at an offset inside the page, then adjust the size
@@ -217,7 +232,8 @@ static int amdgpu_ttm_map_buffer(struct drm_sched_entity *entity,
offset = mm_cur->start & ~PAGE_MASK;
num_pages = PFN_UP(*size + offset);
- num_pages = min_t(uint32_t, num_pages, AMDGPU_GTT_MAX_TRANSFER_SIZE);
+ num_pages = min_t(uint32_t,
+ num_pages, AMDGPU_GTT_MAX_TRANSFER_SIZE * (use_two_windows ? 2 : 1));
*size = min(*size, (uint64_t)num_pages * PAGE_SIZE - offset);
@@ -308,8 +324,10 @@ static int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
struct dma_resv *resv,
struct dma_fence **f)
{
+ bool src_needs_gart_window, dst_needs_gart_window, use_two_gart_windows;
struct amdgpu_ring *ring = adev->mman.buffer_funcs_rings[0];
struct amdgpu_res_cursor src_mm, dst_mm;
+ int src_gart_window, dst_gart_window;
struct dma_fence *fence = NULL;
int r = 0;
uint32_t copy_flags = 0;
@@ -333,20 +351,43 @@ static int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
/* Never copy more than 256MiB at once to avoid a timeout */
cur_size = min3(src_mm.size, dst_mm.size, 256ULL << 20);
- /* Map src to window 0 and dst to window 1. */
- r = amdgpu_ttm_map_buffer(&entity->base,
- src->bo, src->mem, &src_mm,
- entity->gart_window_id0, ring, tmz, &cur_size, &from,
- NULL, NULL);
- if (r)
- goto error;
+ /* If only one direction needs a gart window to access memory, use both
+ * windows for it.
+ */
+ src_needs_gart_window =
+ amdgpu_ttm_needs_gart_window(ring, src->mem, &src_mm, tmz, &from);
+ dst_needs_gart_window =
+ amdgpu_ttm_needs_gart_window(ring, dst->mem, &dst_mm, tmz, &to);
- r = amdgpu_ttm_map_buffer(&entity->base,
- dst->bo, dst->mem, &dst_mm,
- entity->gart_window_id1, ring, tmz, &cur_size, &to,
- NULL, NULL);
- if (r)
- goto error;
+ if (src_needs_gart_window) {
+ src_gart_window = entity->gart_window_id0;
+ use_two_gart_windows = !dst_needs_gart_window;
+ }
+ if (dst_needs_gart_window) {
+ dst_gart_window = src_needs_gart_window ?
+ entity->gart_window_id1 : entity->gart_window_id0;
+ use_two_gart_windows = !src_needs_gart_window;
+ }
+
+ if (src_needs_gart_window) {
+ r = amdgpu_ttm_map_buffer(&entity->base,
+ src->bo, src->mem, &src_mm,
+ src_gart_window, use_two_gart_windows,
+ ring, tmz, &cur_size, &from,
+ NULL, NULL);
+ if (r)
+ goto error;
+ }
+
+ if (dst_needs_gart_window) {
+ r = amdgpu_ttm_map_buffer(&entity->base,
+ dst->bo, dst->mem, &dst_mm,
+ dst_gart_window, use_two_gart_windows,
+ ring, tmz, &cur_size, &to,
+ NULL, NULL);
+ if (r)
+ goto error;
+ }
abo_src = ttm_to_amdgpu_bo(src->bo);
abo_dst = ttm_to_amdgpu_bo(dst->bo);
@@ -2506,7 +2547,7 @@ int amdgpu_clear_buffer(struct amdgpu_ttm_entity *entity,
r = amdgpu_ttm_map_buffer(&entity->base,
&bo->tbo, bo->tbo.resource, &dst,
- entity->gart_window_id1, ring, false,
+ entity->gart_window_id1, false, ring, false,
&cur_size, &to,
dependency,
resv);
--
2.43.0
^ permalink raw reply [flat|nested] 40+ messages in thread* [PATCH v1 20/20] drm/amdgpu: double AMDGPU_GTT_MAX_TRANSFER_SIZE
2025-11-04 8:35 [PATCH v1 00/20] drm/amdgpu: use all SDMA instances for TTM clears and moves Pierre-Eric Pelloux-Prayer
` (18 preceding siblings ...)
2025-11-04 8:35 ` [PATCH v1 19/20] drm/amdgpu: use larger gart window when possible Pierre-Eric Pelloux-Prayer
@ 2025-11-04 8:35 ` Pierre-Eric Pelloux-Prayer
2025-11-04 13:56 ` Christian König
19 siblings, 1 reply; 40+ messages in thread
From: Pierre-Eric Pelloux-Prayer @ 2025-11-04 8:35 UTC (permalink / raw)
To: Alex Deucher, Christian König, David Airlie, Simona Vetter
Cc: Pierre-Eric Pelloux-Prayer, amd-gfx, dri-devel, linux-kernel
Makes copies/evictions faster when gart windows are required.
Signed-off-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
index b685bf207e43..82276eff511d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
@@ -38,7 +38,7 @@
#define AMDGPU_PL_MMIO_REMAP (TTM_PL_PRIV + 5)
#define __AMDGPU_PL_NUM (TTM_PL_PRIV + 6)
-#define AMDGPU_GTT_MAX_TRANSFER_SIZE 512
+#define AMDGPU_GTT_MAX_TRANSFER_SIZE 1024
extern const struct attribute_group amdgpu_vram_mgr_attr_group;
extern const struct attribute_group amdgpu_gtt_mgr_attr_group;
--
2.43.0
^ permalink raw reply [flat|nested] 40+ messages in thread* Re: [PATCH v1 20/20] drm/amdgpu: double AMDGPU_GTT_MAX_TRANSFER_SIZE
2025-11-04 8:35 ` [PATCH v1 20/20] drm/amdgpu: double AMDGPU_GTT_MAX_TRANSFER_SIZE Pierre-Eric Pelloux-Prayer
@ 2025-11-04 13:56 ` Christian König
0 siblings, 0 replies; 40+ messages in thread
From: Christian König @ 2025-11-04 13:56 UTC (permalink / raw)
To: Pierre-Eric Pelloux-Prayer, Alex Deucher, David Airlie, Simona Vetter
Cc: amd-gfx, dri-devel, linux-kernel
On 11/4/25 09:35, Pierre-Eric Pelloux-Prayer wrote:
> Makes copies/evictions faster when gart windows are required.
>
> Signed-off-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
> index b685bf207e43..82276eff511d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
> @@ -38,7 +38,7 @@
> #define AMDGPU_PL_MMIO_REMAP (TTM_PL_PRIV + 5)
> #define __AMDGPU_PL_NUM (TTM_PL_PRIV + 6)
>
> -#define AMDGPU_GTT_MAX_TRANSFER_SIZE 512
> +#define AMDGPU_GTT_MAX_TRANSFER_SIZE 1024
>
> extern const struct attribute_group amdgpu_vram_mgr_attr_group;
> extern const struct attribute_group amdgpu_gtt_mgr_attr_group;
^ permalink raw reply [flat|nested] 40+ messages in thread