From: Jie Luo <quic_luoj@quicinc.com>
To: Andrew Lunn <andrew@lunn.ch>
Cc: <agross@kernel.org>, <andersson@kernel.org>,
<konrad.dybcio@linaro.org>, <davem@davemloft.net>,
<edumazet@google.com>, <kuba@kernel.org>, <pabeni@redhat.com>,
<robh+dt@kernel.org>, <krzysztof.kozlowski+dt@linaro.org>,
<conor+dt@kernel.org>, <hkallweit1@gmail.com>,
<linux@armlinux.org.uk>, <robert.marko@sartura.hr>,
<linux-arm-msm@vger.kernel.org>, <netdev@vger.kernel.org>,
<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<quic_srichara@quicinc.com>
Subject: Re: [PATCH 8/9] net: mdio: ipq4019: add qca8084 configurations
Date: Thu, 16 Nov 2023 18:47:08 +0800 [thread overview]
Message-ID: <2ca3c6eb-93da-4e44-aa6b-c426b8baecb9@quicinc.com> (raw)
In-Reply-To: <a1954855-f82d-434b-afd1-aa05c7a1b39b@lunn.ch>
On 11/16/2023 12:20 AM, Andrew Lunn wrote:
> On Wed, Nov 15, 2023 at 11:25:14AM +0800, Luo Jie wrote:
>> The PHY & PCS clocks need to be enabled and the reset
>> sequence needs to be completed to make qca8084 PHY
>> probeable by MDIO bus.
>
> Is all this guaranteed to be the same between different boards? Can
> the board be wired differently and need a different configuration?
>
> Andrew
Hi Andrew,
This configuration sequence is specified to the qca8084 chip,
not related with the platform(such as ipq5332).
All these configured registers are located in qca8084 chip, we need
to complete these configurations to make MDIO bus being able to
scan the qca8084 PHY(PHY registers can be accessed).
next prev parent reply other threads:[~2023-11-16 10:47 UTC|newest]
Thread overview: 55+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-15 3:25 [PATCH 0/9] add MDIO changes on ipq5332 platform Luo Jie
2023-11-15 3:25 ` [PATCH 1/9] net: mdio: ipq4019: increase eth_ldo_rdy for " Luo Jie
2023-11-15 13:44 ` Andrew Lunn
2023-11-16 9:35 ` Jie Luo
2023-11-16 11:57 ` Krzysztof Kozlowski
2023-11-17 9:56 ` Jie Luo
2023-11-15 3:25 ` [PATCH 2/9] net: mdio: ipq4019: Enable the clocks " Luo Jie
2023-11-20 14:22 ` Konrad Dybcio
2023-11-21 10:28 ` Jie Luo
2023-11-21 14:04 ` Andrew Lunn
2023-11-23 11:02 ` Jie Luo
2023-11-27 9:37 ` Simon Horman
2023-11-28 7:07 ` Jie Luo
2023-11-15 3:25 ` [PATCH 3/9] net: mdio: ipq4019: Enable GPIO reset " Luo Jie
2023-11-15 15:11 ` Andrew Lunn
2023-11-16 11:13 ` Jie Luo
2023-11-16 11:19 ` Robert Marko
2023-11-16 11:29 ` Jie Luo
2023-11-16 17:20 ` Andrew Lunn
2023-11-17 9:59 ` Jie Luo
2023-12-04 8:53 ` Jie Luo
2023-11-15 3:25 ` [PATCH 4/9] net: mdio: ipq4019: configure CMN PLL clock for ipq5332 Luo Jie
2023-11-15 15:19 ` Andrew Lunn
2023-11-16 10:48 ` Jie Luo
2023-11-22 20:24 ` Konrad Dybcio
2023-11-15 3:25 ` [PATCH 5/9] net: mdio: ipq4019: support MDIO clock frequency divider Luo Jie
2023-11-15 15:22 ` Andrew Lunn
2023-11-16 10:47 ` Jie Luo
2023-11-15 3:25 ` [PATCH 6/9] net: mdio: ipq4019: Support qca8084 switch register access Luo Jie
2023-11-15 3:25 ` [PATCH 7/9] net: mdio: ipq4019: program phy address when "fixup" defined Luo Jie
2023-11-15 16:17 ` Andrew Lunn
2023-11-16 11:17 ` Jie Luo
2023-11-15 3:25 ` [PATCH 8/9] net: mdio: ipq4019: add qca8084 configurations Luo Jie
2023-11-15 16:20 ` Andrew Lunn
2023-11-15 17:01 ` Konrad Dybcio
2023-11-15 17:03 ` Robert Marko
2023-11-16 10:45 ` Jie Luo
2023-11-16 17:08 ` Andrew Lunn
2023-11-17 10:05 ` Jie Luo
2023-11-16 10:44 ` Jie Luo
2023-11-16 10:47 ` Jie Luo [this message]
2023-11-16 17:12 ` Andrew Lunn
2023-11-17 10:15 ` Jie Luo
2023-11-15 3:25 ` [PATCH 9/9] dt-bindings: net: ipq4019-mdio: Document ipq5332 platform Luo Jie
2023-11-15 4:20 ` Rob Herring
2023-11-15 14:35 ` Andrew Lunn
2023-11-16 11:22 ` Jie Luo
2023-11-16 11:56 ` Krzysztof Kozlowski
2023-11-17 10:36 ` Jie Luo
2023-11-17 10:40 ` Krzysztof Kozlowski
2023-11-17 11:20 ` Jie Luo
2023-11-17 12:43 ` Krzysztof Kozlowski
2023-11-18 8:07 ` Jie Luo
2023-11-18 15:36 ` Andrew Lunn
2023-11-20 9:00 ` Jie Luo
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=2ca3c6eb-93da-4e44-aa6b-c426b8baecb9@quicinc.com \
--to=quic_luoj@quicinc.com \
--cc=agross@kernel.org \
--cc=andersson@kernel.org \
--cc=andrew@lunn.ch \
--cc=conor+dt@kernel.org \
--cc=davem@davemloft.net \
--cc=devicetree@vger.kernel.org \
--cc=edumazet@google.com \
--cc=hkallweit1@gmail.com \
--cc=konrad.dybcio@linaro.org \
--cc=krzysztof.kozlowski+dt@linaro.org \
--cc=kuba@kernel.org \
--cc=linux-arm-msm@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux@armlinux.org.uk \
--cc=netdev@vger.kernel.org \
--cc=pabeni@redhat.com \
--cc=quic_srichara@quicinc.com \
--cc=robert.marko@sartura.hr \
--cc=robh+dt@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox
all inboxes | Powered by JetHome®