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From: Jie Luo <quic_luoj@quicinc.com>
To: Andrew Lunn <andrew@lunn.ch>
Cc: <agross@kernel.org>, <andersson@kernel.org>,
	<konrad.dybcio@linaro.org>, <davem@davemloft.net>,
	<edumazet@google.com>, <kuba@kernel.org>, <pabeni@redhat.com>,
	<robh+dt@kernel.org>, <krzysztof.kozlowski+dt@linaro.org>,
	<conor+dt@kernel.org>, <hkallweit1@gmail.com>,
	<linux@armlinux.org.uk>, <robert.marko@sartura.hr>,
	<linux-arm-msm@vger.kernel.org>, <netdev@vger.kernel.org>,
	<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
	<quic_srichara@quicinc.com>
Subject: Re: [PATCH 4/9] net: mdio: ipq4019: configure CMN PLL clock for ipq5332
Date: Thu, 16 Nov 2023 18:48:34 +0800	[thread overview]
Message-ID: <4cdaf41c-6cc0-470f-97a7-8b08fdde7f6c@quicinc.com> (raw)
In-Reply-To: <e1fecfd7-3de1-4719-879b-fd486fdc3815@lunn.ch>



On 11/15/2023 11:19 PM, Andrew Lunn wrote:
>> +static void ipq_cmn_clock_config(struct mii_bus *bus)
>> +{
>> +	u32 reg_val;
>> +	const char *cmn_ref_clk;
>> +	struct ipq4019_mdio_data *priv = bus->priv;
> 
> Reverse christmass tree place.

will fix it in the next patch set.

> 
>> +
>> +	if (priv && priv->cmn_membase) {
> 
> Can priv be NULL? Can cmn_membase be NULL?

priv can't be NULL, cmn_membase is optional, the legacy chip does not
provide the cmn_membase in device node.

will remove the priv check here.

> 
>> +		reg_val = readl(priv->cmn_membase + CMN_PLL_REFERENCE_CLOCK);
>> +		reg_val &= ~(CMN_PLL_REFCLK_EXTERNAL | CMN_PLL_REFCLK_INDEX);
>> +
>> +		/* Select reference clock source */
>> +		cmn_ref_clk = of_get_property(bus->parent->of_node, "cmn_ref_clk", NULL);
>> +		if (!cmn_ref_clk) {
>> +			/* Internal 48MHZ selected by default */
>> +			reg_val |= FIELD_PREP(CMN_PLL_REFCLK_INDEX, 7);
>> +		} else {
>> +			if (!strcmp(cmn_ref_clk, "external_25MHz"))
> 
> Not strings, please use u32 values. You can then list the valid values
> in the yaml file, and get te tools to verify the DT.

will update this in the next patch.

> 
>> +				reg_val |= (CMN_PLL_REFCLK_EXTERNAL |
>> +					    FIELD_PREP(CMN_PLL_REFCLK_INDEX, 3));
>> +			else if (!strcmp(cmn_ref_clk, "external_31250KHz"))
>> +				reg_val |= (CMN_PLL_REFCLK_EXTERNAL |
>> +					    FIELD_PREP(CMN_PLL_REFCLK_INDEX, 4));
>> +			else if (!strcmp(cmn_ref_clk, "external_40MHz"))
>> +				reg_val |= (CMN_PLL_REFCLK_EXTERNAL |
>> +					    FIELD_PREP(CMN_PLL_REFCLK_INDEX, 6));
>> +			else if (!strcmp(cmn_ref_clk, "external_48MHz"))
>> +				reg_val |= (CMN_PLL_REFCLK_EXTERNAL |
>> +					    FIELD_PREP(CMN_PLL_REFCLK_INDEX, 7));
>> +			else if (!strcmp(cmn_ref_clk, "external_50MHz"))
>> +				reg_val |= (CMN_PLL_REFCLK_EXTERNAL |
>> +					    FIELD_PREP(CMN_PLL_REFCLK_INDEX, 8));
>> +			else
>> +				reg_val |= FIELD_PREP(CMN_PLL_REFCLK_INDEX, 7);
> 
> If the value is not valid, return -EINVAL.

will add it in the next patch set.

> 
>     Andrew

  reply	other threads:[~2023-11-16 10:48 UTC|newest]

Thread overview: 55+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-11-15  3:25 [PATCH 0/9] add MDIO changes on ipq5332 platform Luo Jie
2023-11-15  3:25 ` [PATCH 1/9] net: mdio: ipq4019: increase eth_ldo_rdy for " Luo Jie
2023-11-15 13:44   ` Andrew Lunn
2023-11-16  9:35     ` Jie Luo
2023-11-16 11:57   ` Krzysztof Kozlowski
2023-11-17  9:56     ` Jie Luo
2023-11-15  3:25 ` [PATCH 2/9] net: mdio: ipq4019: Enable the clocks " Luo Jie
2023-11-20 14:22   ` Konrad Dybcio
2023-11-21 10:28     ` Jie Luo
2023-11-21 14:04       ` Andrew Lunn
2023-11-23 11:02         ` Jie Luo
2023-11-27  9:37   ` Simon Horman
2023-11-28  7:07     ` Jie Luo
2023-11-15  3:25 ` [PATCH 3/9] net: mdio: ipq4019: Enable GPIO reset " Luo Jie
2023-11-15 15:11   ` Andrew Lunn
2023-11-16 11:13     ` Jie Luo
2023-11-16 11:19       ` Robert Marko
2023-11-16 11:29         ` Jie Luo
2023-11-16 17:20       ` Andrew Lunn
2023-11-17  9:59         ` Jie Luo
2023-12-04  8:53         ` Jie Luo
2023-11-15  3:25 ` [PATCH 4/9] net: mdio: ipq4019: configure CMN PLL clock for ipq5332 Luo Jie
2023-11-15 15:19   ` Andrew Lunn
2023-11-16 10:48     ` Jie Luo [this message]
2023-11-22 20:24   ` Konrad Dybcio
2023-11-15  3:25 ` [PATCH 5/9] net: mdio: ipq4019: support MDIO clock frequency divider Luo Jie
2023-11-15 15:22   ` Andrew Lunn
2023-11-16 10:47     ` Jie Luo
2023-11-15  3:25 ` [PATCH 6/9] net: mdio: ipq4019: Support qca8084 switch register access Luo Jie
2023-11-15  3:25 ` [PATCH 7/9] net: mdio: ipq4019: program phy address when "fixup" defined Luo Jie
2023-11-15 16:17   ` Andrew Lunn
2023-11-16 11:17     ` Jie Luo
2023-11-15  3:25 ` [PATCH 8/9] net: mdio: ipq4019: add qca8084 configurations Luo Jie
2023-11-15 16:20   ` Andrew Lunn
2023-11-15 17:01     ` Konrad Dybcio
2023-11-15 17:03       ` Robert Marko
2023-11-16 10:45         ` Jie Luo
2023-11-16 17:08           ` Andrew Lunn
2023-11-17 10:05             ` Jie Luo
2023-11-16 10:44       ` Jie Luo
2023-11-16 10:47     ` Jie Luo
2023-11-16 17:12       ` Andrew Lunn
2023-11-17 10:15         ` Jie Luo
2023-11-15  3:25 ` [PATCH 9/9] dt-bindings: net: ipq4019-mdio: Document ipq5332 platform Luo Jie
2023-11-15  4:20   ` Rob Herring
2023-11-15 14:35   ` Andrew Lunn
2023-11-16 11:22     ` Jie Luo
2023-11-16 11:56   ` Krzysztof Kozlowski
2023-11-17 10:36     ` Jie Luo
2023-11-17 10:40       ` Krzysztof Kozlowski
2023-11-17 11:20         ` Jie Luo
2023-11-17 12:43           ` Krzysztof Kozlowski
2023-11-18  8:07             ` Jie Luo
2023-11-18 15:36               ` Andrew Lunn
2023-11-20  9:00                 ` Jie Luo

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