From: Andrew Lunn <andrew@lunn.ch>
To: Jie Luo <quic_luoj@quicinc.com>
Cc: hkallweit1@gmail.com, davem@davemloft.net, edumazet@google.com,
kuba@kernel.org, pabeni@redhat.com, linux@armlinux.org.uk,
netdev@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 3/3] net: phy: at803x: add qca8081 fifo reset on the link down
Date: Sat, 1 Jul 2023 18:21:14 +0200 [thread overview]
Message-ID: <34ef466e-df95-4be4-8366-64baf5f04cca@lunn.ch> (raw)
In-Reply-To: <49f8ca40-e079-ad00-256e-08a61ffced22@quicinc.com>
> Hi Andrew,
> it is the PLL related registers, there is no PHY ID existed in MII register
> 2, 3 of this block, so it can't be instantiated as the generic PHY device.
Well, phylib is going to scan those ID registers, and if it finds
something other than 0xffff 0xffff in those two ID registers it is
going to think a PHY is there. And then if there is no driver using
that ID, it will instantiate a generic PHY.
You might be able to see this in /sys/bus/mdio_bus, especially if you
don't have a DT node representing the MDIO bus.
Andrew
next prev parent reply other threads:[~2023-07-01 16:21 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-29 3:48 [PATCH 0/3] net: phy: at803x: support qca8081 1G version chip Luo Jie
2023-06-29 3:48 ` [PATCH 1/3] net: phy: at803x: support qca8081 1G chip type Luo Jie
2023-06-29 13:14 ` Andrew Lunn
2023-06-30 6:39 ` Jie Luo
2023-06-30 13:16 ` Andrew Lunn
2023-07-01 8:00 ` Jie Luo
2023-07-01 14:30 ` Andrew Lunn
2023-07-01 15:42 ` Jie Luo
2023-06-29 3:48 ` [PATCH 2/3] net: phy: at803x: remove 1000BaseX mode of qca8081 Luo Jie
2023-06-29 13:16 ` Andrew Lunn
2023-06-29 3:48 ` [PATCH 3/3] net: phy: at803x: add qca8081 fifo reset on the link down Luo Jie
2023-06-29 13:23 ` Andrew Lunn
2023-06-30 6:54 ` Jie Luo
2023-06-30 13:21 ` Andrew Lunn
2023-07-01 8:04 ` Jie Luo
2023-07-01 14:34 ` Andrew Lunn
2023-07-01 15:44 ` Jie Luo
2023-07-01 16:21 ` Andrew Lunn [this message]
2023-07-02 10:00 ` Jie Luo
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