From: Jie Luo <quic_luoj@quicinc.com>
To: Andrew Lunn <andrew@lunn.ch>
Cc: <hkallweit1@gmail.com>, <davem@davemloft.net>,
<edumazet@google.com>, <kuba@kernel.org>, <pabeni@redhat.com>,
<linux@armlinux.org.uk>, <netdev@vger.kernel.org>,
<linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 3/3] net: phy: at803x: add qca8081 fifo reset on the link down
Date: Sat, 1 Jul 2023 23:44:34 +0800 [thread overview]
Message-ID: <49f8ca40-e079-ad00-256e-08a61ffced22@quicinc.com> (raw)
In-Reply-To: <d4043e1f-d683-48c2-af79-9fea14ab7cc1@lunn.ch>
On 7/1/2023 10:34 PM, Andrew Lunn wrote:
>> Hi Andrew,
>> This block includes MII and MMD1 registers, which mainly configure the PLL
>> clocks, reset and calibration of the interface sgmii, there is no related
>> Clause 73 control register in this block.
>
> O.K. What does it have in the MII ID registers? Does Linux think it is
> a PHY and instantiating an generic PHY driver for it?
>
> Andrew
Hi Andrew,
it is the PLL related registers, there is no PHY ID existed in MII
register 2, 3 of this block, so it can't be instantiated as the generic
PHY device.
next prev parent reply other threads:[~2023-07-01 15:45 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-29 3:48 [PATCH 0/3] net: phy: at803x: support qca8081 1G version chip Luo Jie
2023-06-29 3:48 ` [PATCH 1/3] net: phy: at803x: support qca8081 1G chip type Luo Jie
2023-06-29 13:14 ` Andrew Lunn
2023-06-30 6:39 ` Jie Luo
2023-06-30 13:16 ` Andrew Lunn
2023-07-01 8:00 ` Jie Luo
2023-07-01 14:30 ` Andrew Lunn
2023-07-01 15:42 ` Jie Luo
2023-06-29 3:48 ` [PATCH 2/3] net: phy: at803x: remove 1000BaseX mode of qca8081 Luo Jie
2023-06-29 13:16 ` Andrew Lunn
2023-06-29 3:48 ` [PATCH 3/3] net: phy: at803x: add qca8081 fifo reset on the link down Luo Jie
2023-06-29 13:23 ` Andrew Lunn
2023-06-30 6:54 ` Jie Luo
2023-06-30 13:21 ` Andrew Lunn
2023-07-01 8:04 ` Jie Luo
2023-07-01 14:34 ` Andrew Lunn
2023-07-01 15:44 ` Jie Luo [this message]
2023-07-01 16:21 ` Andrew Lunn
2023-07-02 10:00 ` Jie Luo
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