* [PATCH 0/2] arm64: dts: qcom: sm8350: Scale L3 and memory bandwidth with the CPUs
@ 2026-10-16 6:01 Demeter Barna via B4 Relay
2026-10-16 6:01 ` [PATCH 1/2] arm64: dts: qcom: sm8350: Add the EPSS L3 provider Demeter Barna via B4 Relay
2026-10-16 6:01 ` [PATCH 2/2] arm64: dts: qcom: sm8350: Add CPU OPP tables with memory bandwidth Demeter Barna via B4 Relay
0 siblings, 2 replies; 5+ messages in thread
From: Demeter Barna via B4 Relay @ 2026-10-16 6:01 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Abel Vesa, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Demeter Barna
Add the EPSS L3 provider and CPU OPP tables that vote for LLCC, DDR and
L3 bandwidth with the CPU frequency, as on SM8550 and SM8650.
Tested on a Razer Edge 5G, whose board support is not upstream yet:
copy bandwidth on the A78 and X1 cores goes from 8 to 22-33 GB/s and
DDR latency from 200 to 125 ns. Idle power with the screen off does not
change; with the X1 busy on compute alone it rises by about 0.3 W.
---
Demeter Barna (2):
arm64: dts: qcom: sm8350: Add the EPSS L3 provider
arm64: dts: qcom: sm8350: Add CPU OPP tables with memory bandwidth
arch/arm64/boot/dts/qcom/sm8350.dtsi | 347 +++++++++++++++++++++++++++++++++++
1 file changed, 347 insertions(+)
---
base-commit: 4eb2586bd40db27d77cc5b724ca9386ed0c71d53
change-id: 20261016-sm8350-cpu-bw-7ce3e07fbe3a
Best regards,
--
Demeter Barna <me@fromdisposition.org>
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH 1/2] arm64: dts: qcom: sm8350: Add the EPSS L3 provider
2026-10-16 6:01 [PATCH 0/2] arm64: dts: qcom: sm8350: Scale L3 and memory bandwidth with the CPUs Demeter Barna via B4 Relay
@ 2026-10-16 6:01 ` Demeter Barna via B4 Relay
2026-10-16 8:45 ` Konrad Dybcio
2026-10-16 6:01 ` [PATCH 2/2] arm64: dts: qcom: sm8350: Add CPU OPP tables with memory bandwidth Demeter Barna via B4 Relay
1 sibling, 1 reply; 5+ messages in thread
From: Demeter Barna via B4 Relay @ 2026-10-16 6:01 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Abel Vesa, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Demeter Barna
From: Demeter Barna <me@fromdisposition.org>
Add the EPSS L3 block, already documented as qcom,sm8350-epss-l3, so
that the CPUs can vote for the L3 frequency.
Unlike on SM8250, the L3 is voted through the L3_VOTE register, as the
downstream driver for this SoC does. The generic qcom,epss-l3 fallback
selects that, so no driver change is needed.
Assisted-by: LLM
Signed-off-by: Demeter Barna <me@fromdisposition.org>
---
arch/arm64/boot/dts/qcom/sm8350.dtsi | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index 55b32050c..52e8c2963 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -15,6 +15,7 @@
#include <dt-bindings/firmware/qcom,scm.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interconnect/qcom,icc.h>
+#include <dt-bindings/interconnect/qcom,osm-l3.h>
#include <dt-bindings/interconnect/qcom,sm8350.h>
#include <dt-bindings/mailbox/qcom-ipcc.h>
#include <dt-bindings/phy/phy-qcom-qmp.h>
@@ -3798,6 +3799,16 @@ apps_bcm_voter: bcm-voter {
};
};
+ epss_l3: interconnect@18590000 {
+ compatible = "qcom,sm8350-epss-l3", "qcom,epss-l3";
+ reg = <0 0x18590000 0 0x1000>;
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
+ clock-names = "xo", "alternate";
+
+ #interconnect-cells = <1>;
+ };
+
cpufreq_hw: cpufreq@18591000 {
compatible = "qcom,sm8350-cpufreq-epss", "qcom,cpufreq-epss";
reg = <0 0x18591000 0 0x1000>,
--
2.53.0
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH 2/2] arm64: dts: qcom: sm8350: Add CPU OPP tables with memory bandwidth
2026-10-16 6:01 [PATCH 0/2] arm64: dts: qcom: sm8350: Scale L3 and memory bandwidth with the CPUs Demeter Barna via B4 Relay
2026-10-16 6:01 ` [PATCH 1/2] arm64: dts: qcom: sm8350: Add the EPSS L3 provider Demeter Barna via B4 Relay
@ 2026-10-16 6:01 ` Demeter Barna via B4 Relay
2026-10-16 8:45 ` Konrad Dybcio
1 sibling, 1 reply; 5+ messages in thread
From: Demeter Barna via B4 Relay @ 2026-10-16 6:01 UTC (permalink / raw)
To: Bjorn Andersson, Konrad Dybcio, Abel Vesa, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Demeter Barna
From: Demeter Barna <me@fromdisposition.org>
Without them nothing votes for the CPUs' memory paths and DDR stays at
what other clients request. Vote for CPU-to-LLCC, LLCC-to-DDR and L3
with the CPU frequency, as on SM8550 and SM8650.
The frequencies are the cpufreq-hw LUT; the LLCC, DDR (LPDDR5) and L3
levels follow the downstream memory latency tables.
Assisted-by: LLM
Signed-off-by: Demeter Barna <me@fromdisposition.org>
---
arch/arm64/boot/dts/qcom/sm8350.dtsi | 336 +++++++++++++++++++++++++++++++++++
1 file changed, 336 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index 52e8c2963..4e33a1e10 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -65,6 +65,13 @@ cpu0: cpu@0 {
qcom,freq-domain = <&cpufreq_hw 0>;
power-domains = <&cpu_pd0>;
power-domain-names = "psci";
+ operating-points-v2 = <&cpu0_opp_table>;
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&epss_l3 MASTER_EPSS_L3_APPS
+ &epss_l3 SLAVE_EPSS_L3_SHARED>;
#cooling-cells = <2>;
l2_0: l2-cache {
compatible = "cache";
@@ -89,6 +96,13 @@ cpu1: cpu@100 {
qcom,freq-domain = <&cpufreq_hw 0>;
power-domains = <&cpu_pd1>;
power-domain-names = "psci";
+ operating-points-v2 = <&cpu0_opp_table>;
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&epss_l3 MASTER_EPSS_L3_APPS
+ &epss_l3 SLAVE_EPSS_L3_SHARED>;
#cooling-cells = <2>;
l2_100: l2-cache {
compatible = "cache";
@@ -108,6 +122,13 @@ cpu2: cpu@200 {
qcom,freq-domain = <&cpufreq_hw 0>;
power-domains = <&cpu_pd2>;
power-domain-names = "psci";
+ operating-points-v2 = <&cpu0_opp_table>;
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&epss_l3 MASTER_EPSS_L3_APPS
+ &epss_l3 SLAVE_EPSS_L3_SHARED>;
#cooling-cells = <2>;
l2_200: l2-cache {
compatible = "cache";
@@ -127,6 +148,13 @@ cpu3: cpu@300 {
qcom,freq-domain = <&cpufreq_hw 0>;
power-domains = <&cpu_pd3>;
power-domain-names = "psci";
+ operating-points-v2 = <&cpu0_opp_table>;
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&epss_l3 MASTER_EPSS_L3_APPS
+ &epss_l3 SLAVE_EPSS_L3_SHARED>;
#cooling-cells = <2>;
l2_300: l2-cache {
compatible = "cache";
@@ -146,6 +174,13 @@ cpu4: cpu@400 {
qcom,freq-domain = <&cpufreq_hw 1>;
power-domains = <&cpu_pd4>;
power-domain-names = "psci";
+ operating-points-v2 = <&cpu4_opp_table>;
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&epss_l3 MASTER_EPSS_L3_APPS
+ &epss_l3 SLAVE_EPSS_L3_SHARED>;
#cooling-cells = <2>;
l2_400: l2-cache {
compatible = "cache";
@@ -165,6 +200,13 @@ cpu5: cpu@500 {
qcom,freq-domain = <&cpufreq_hw 1>;
power-domains = <&cpu_pd5>;
power-domain-names = "psci";
+ operating-points-v2 = <&cpu4_opp_table>;
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&epss_l3 MASTER_EPSS_L3_APPS
+ &epss_l3 SLAVE_EPSS_L3_SHARED>;
#cooling-cells = <2>;
l2_500: l2-cache {
compatible = "cache";
@@ -184,6 +226,13 @@ cpu6: cpu@600 {
qcom,freq-domain = <&cpufreq_hw 1>;
power-domains = <&cpu_pd6>;
power-domain-names = "psci";
+ operating-points-v2 = <&cpu4_opp_table>;
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&epss_l3 MASTER_EPSS_L3_APPS
+ &epss_l3 SLAVE_EPSS_L3_SHARED>;
#cooling-cells = <2>;
l2_600: l2-cache {
compatible = "cache";
@@ -203,6 +252,13 @@ cpu7: cpu@700 {
qcom,freq-domain = <&cpufreq_hw 2>;
power-domains = <&cpu_pd7>;
power-domain-names = "psci";
+ operating-points-v2 = <&cpu7_opp_table>;
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&epss_l3 MASTER_EPSS_L3_APPS
+ &epss_l3 SLAVE_EPSS_L3_SHARED>;
#cooling-cells = <2>;
l2_700: l2-cache {
compatible = "cache";
@@ -379,6 +435,286 @@ cluster_pd: power-domain-cpu-cluster0 {
};
};
+ cpu0_opp_table: opp-table-cpu0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ opp-peak-kBps = <(150000 * 16) (200000 * 4) (300000 * 32)>;
+ };
+
+ opp-403200000 {
+ opp-hz = /bits/ 64 <403200000>;
+ opp-peak-kBps = <(300000 * 16) (451000 * 4) (403200 * 32)>;
+ };
+
+ opp-499200000 {
+ opp-hz = /bits/ 64 <499200000>;
+ opp-peak-kBps = <(300000 * 16) (451000 * 4) (499200 * 32)>;
+ };
+
+ opp-595200000 {
+ opp-hz = /bits/ 64 <595200000>;
+ opp-peak-kBps = <(300000 * 16) (451000 * 4) (614400 * 32)>;
+ };
+
+ opp-691200000 {
+ opp-hz = /bits/ 64 <691200000>;
+ opp-peak-kBps = <(300000 * 16) (451000 * 4) (614400 * 32)>;
+ };
+
+ opp-806400000 {
+ opp-hz = /bits/ 64 <806400000>;
+ opp-peak-kBps = <(300000 * 16) (451000 * 4) (710400 * 32)>;
+ };
+
+ opp-902400000 {
+ opp-hz = /bits/ 64 <902400000>;
+ opp-peak-kBps = <(466000 * 16) (547000 * 4) (883200 * 32)>;
+ };
+
+ opp-998400000 {
+ opp-hz = /bits/ 64 <998400000>;
+ opp-peak-kBps = <(466000 * 16) (547000 * 4) (979200 * 32)>;
+ };
+
+ opp-1094400000 {
+ opp-hz = /bits/ 64 <1094400000>;
+ opp-peak-kBps = <(466000 * 16) (547000 * 4) (979200 * 32)>;
+ };
+
+ opp-1209600000 {
+ opp-hz = /bits/ 64 <1209600000>;
+ opp-peak-kBps = <(466000 * 16) (547000 * 4) (1056000 * 32)>;
+ };
+
+ opp-1305600000 {
+ opp-hz = /bits/ 64 <1305600000>;
+ opp-peak-kBps = <(466000 * 16) (768000 * 4) (1152000 * 32)>;
+ };
+
+ opp-1401600000 {
+ opp-hz = /bits/ 64 <1401600000>;
+ opp-peak-kBps = <(466000 * 16) (768000 * 4) (1248000 * 32)>;
+ };
+
+ opp-1497600000 {
+ opp-hz = /bits/ 64 <1497600000>;
+ opp-peak-kBps = <(466000 * 16) (768000 * 4) (1324800 * 32)>;
+ };
+
+ opp-1612800000 {
+ opp-hz = /bits/ 64 <1612800000>;
+ opp-peak-kBps = <(600000 * 16) (1555000 * 4) (1420800 * 32)>;
+ };
+
+ opp-1708800000 {
+ opp-hz = /bits/ 64 <1708800000>;
+ opp-peak-kBps = <(600000 * 16) (1555000 * 4) (1516800 * 32)>;
+ };
+
+ opp-1804800000 {
+ opp-hz = /bits/ 64 <1804800000>;
+ opp-peak-kBps = <(600000 * 16) (1555000 * 4) (1593600 * 32)>;
+ };
+ };
+
+ cpu4_opp_table: opp-table-cpu4 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-710400000 {
+ opp-hz = /bits/ 64 <710400000>;
+ opp-peak-kBps = <(300000 * 16) (451000 * 4) (499200 * 32)>;
+ };
+
+ opp-844800000 {
+ opp-hz = /bits/ 64 <844800000>;
+ opp-peak-kBps = <(466000 * 16) (547000 * 4) (614400 * 32)>;
+ };
+
+ opp-960000000 {
+ opp-hz = /bits/ 64 <960000000>;
+ opp-peak-kBps = <(466000 * 16) (768000 * 4) (614400 * 32)>;
+ };
+
+ opp-1075200000 {
+ opp-hz = /bits/ 64 <1075200000>;
+ opp-peak-kBps = <(466000 * 16) (768000 * 4) (883200 * 32)>;
+ };
+
+ opp-1209600000 {
+ opp-hz = /bits/ 64 <1209600000>;
+ opp-peak-kBps = <(600000 * 16) (1555000 * 4) (883200 * 32)>;
+ };
+
+ opp-1324800000 {
+ opp-hz = /bits/ 64 <1324800000>;
+ opp-peak-kBps = <(600000 * 16) (1555000 * 4) (1056000 * 32)>;
+ };
+
+ opp-1440000000 {
+ opp-hz = /bits/ 64 <1440000000>;
+ opp-peak-kBps = <(806000 * 16) (1555000 * 4) (1056000 * 32)>;
+ };
+
+ opp-1555200000 {
+ opp-hz = /bits/ 64 <1555200000>;
+ opp-peak-kBps = <(806000 * 16) (1555000 * 4) (1248000 * 32)>;
+ };
+
+ opp-1670400000 {
+ opp-hz = /bits/ 64 <1670400000>;
+ opp-peak-kBps = <(806000 * 16) (1555000 * 4) (1248000 * 32)>;
+ };
+
+ opp-1766400000 {
+ opp-hz = /bits/ 64 <1766400000>;
+ opp-peak-kBps = <(806000 * 16) (1555000 * 4) (1248000 * 32)>;
+ };
+
+ opp-1881600000 {
+ opp-hz = /bits/ 64 <1881600000>;
+ opp-peak-kBps = <(806000 * 16) (1555000 * 4) (1324800 * 32)>;
+ };
+
+ opp-1996800000 {
+ opp-hz = /bits/ 64 <1996800000>;
+ opp-peak-kBps = <(933000 * 16) (2092000 * 4) (1324800 * 32)>;
+ };
+
+ opp-2112000000 {
+ opp-hz = /bits/ 64 <2112000000>;
+ opp-peak-kBps = <(933000 * 16) (2092000 * 4) (1324800 * 32)>;
+ };
+
+ opp-2227200000 {
+ opp-hz = /bits/ 64 <2227200000>;
+ opp-peak-kBps = <(933000 * 16) (2092000 * 4) (1516800 * 32)>;
+ };
+
+ opp-2342400000 {
+ opp-hz = /bits/ 64 <2342400000>;
+ opp-peak-kBps = <(933000 * 16) (2092000 * 4) (1516800 * 32)>;
+ };
+
+ opp-2419200000 {
+ opp-hz = /bits/ 64 <2419200000>;
+ opp-peak-kBps = <(933000 * 16) (2092000 * 4) (1516800 * 32)>;
+ };
+ };
+
+ cpu7_opp_table: opp-table-cpu7 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-844800000 {
+ opp-hz = /bits/ 64 <844800000>;
+ opp-peak-kBps = <(466000 * 16) (547000 * 4) (614400 * 32)>;
+ };
+
+ opp-960000000 {
+ opp-hz = /bits/ 64 <960000000>;
+ opp-peak-kBps = <(466000 * 16) (768000 * 4) (614400 * 32)>;
+ };
+
+ opp-1075200000 {
+ opp-hz = /bits/ 64 <1075200000>;
+ opp-peak-kBps = <(466000 * 16) (768000 * 4) (883200 * 32)>;
+ };
+
+ opp-1190400000 {
+ opp-hz = /bits/ 64 <1190400000>;
+ opp-peak-kBps = <(600000 * 16) (1555000 * 4) (883200 * 32)>;
+ };
+
+ opp-1305600000 {
+ opp-hz = /bits/ 64 <1305600000>;
+ opp-peak-kBps = <(600000 * 16) (1555000 * 4) (1056000 * 32)>;
+ };
+
+ opp-1420800000 {
+ opp-hz = /bits/ 64 <1420800000>;
+ opp-peak-kBps = <(806000 * 16) (1555000 * 4) (1056000 * 32)>;
+ };
+
+ opp-1555200000 {
+ opp-hz = /bits/ 64 <1555200000>;
+ opp-peak-kBps = <(806000 * 16) (1555000 * 4) (1248000 * 32)>;
+ };
+
+ opp-1670400000 {
+ opp-hz = /bits/ 64 <1670400000>;
+ opp-peak-kBps = <(806000 * 16) (1555000 * 4) (1248000 * 32)>;
+ };
+
+ opp-1785600000 {
+ opp-hz = /bits/ 64 <1785600000>;
+ opp-peak-kBps = <(806000 * 16) (1555000 * 4) (1324800 * 32)>;
+ };
+
+ opp-1900800000 {
+ opp-hz = /bits/ 64 <1900800000>;
+ opp-peak-kBps = <(933000 * 16) (2092000 * 4) (1324800 * 32)>;
+ };
+
+ opp-2035200000 {
+ opp-hz = /bits/ 64 <2035200000>;
+ opp-peak-kBps = <(933000 * 16) (2092000 * 4) (1324800 * 32)>;
+ };
+
+ opp-2150400000 {
+ opp-hz = /bits/ 64 <2150400000>;
+ opp-peak-kBps = <(933000 * 16) (2092000 * 4) (1516800 * 32)>;
+ };
+
+ opp-2265600000 {
+ opp-hz = /bits/ 64 <2265600000>;
+ opp-peak-kBps = <(933000 * 16) (2092000 * 4) (1516800 * 32)>;
+ };
+
+ opp-2380800000 {
+ opp-hz = /bits/ 64 <2380800000>;
+ opp-peak-kBps = <(933000 * 16) (2092000 * 4) (1516800 * 32)>;
+ };
+
+ opp-2496000000 {
+ opp-hz = /bits/ 64 <2496000000>;
+ opp-peak-kBps = <(933000 * 16) (2092000 * 4) (1593600 * 32)>;
+ };
+
+ opp-2592000000 {
+ opp-hz = /bits/ 64 <2592000000>;
+ opp-peak-kBps = <(933000 * 16) (2092000 * 4) (1593600 * 32)>;
+ };
+
+ opp-2688000000 {
+ opp-hz = /bits/ 64 <2688000000>;
+ opp-peak-kBps = <(1000000 * 16) (3196000 * 4) (1593600 * 32)>;
+ };
+
+ opp-2764800000 {
+ opp-hz = /bits/ 64 <2764800000>;
+ opp-peak-kBps = <(1000000 * 16) (3196000 * 4) (1593600 * 32)>;
+ };
+
+ opp-2841600000 {
+ opp-hz = /bits/ 64 <2841600000>;
+ opp-peak-kBps = <(1000000 * 16) (3196000 * 4) (1593600 * 32)>;
+ };
+
+ opp-2918400000 {
+ opp-hz = /bits/ 64 <2918400000>;
+ opp-peak-kBps = <(1000000 * 16) (3196000 * 4) (1593600 * 32)>;
+ };
+
+ opp-2995200000 {
+ opp-hz = /bits/ 64 <2995200000>;
+ opp-peak-kBps = <(1000000 * 16) (3196000 * 4) (1593600 * 32)>;
+ };
+ };
+
qup_opp_table_100mhz: opp-table-qup100mhz {
compatible = "operating-points-v2";
--
2.53.0
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH 1/2] arm64: dts: qcom: sm8350: Add the EPSS L3 provider
2026-10-16 6:01 ` [PATCH 1/2] arm64: dts: qcom: sm8350: Add the EPSS L3 provider Demeter Barna via B4 Relay
@ 2026-10-16 8:45 ` Konrad Dybcio
0 siblings, 0 replies; 5+ messages in thread
From: Konrad Dybcio @ 2026-10-16 8:45 UTC (permalink / raw)
To: me, Bjorn Andersson, Konrad Dybcio, Abel Vesa, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel
On 10/16/26 8:01 AM, Demeter Barna via B4 Relay wrote:
> From: Demeter Barna <me@fromdisposition.org>
>
> Add the EPSS L3 block, already documented as qcom,sm8350-epss-l3, so
> that the CPUs can vote for the L3 frequency.
>
> Unlike on SM8250, the L3 is voted through the L3_VOTE register, as the
> downstream driver for this SoC does. The generic qcom,epss-l3 fallback
> selects that, so no driver change is needed.
This pargraph is mildly useful in the context of this commit
anywho
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Konrad
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH 2/2] arm64: dts: qcom: sm8350: Add CPU OPP tables with memory bandwidth
2026-10-16 6:01 ` [PATCH 2/2] arm64: dts: qcom: sm8350: Add CPU OPP tables with memory bandwidth Demeter Barna via B4 Relay
@ 2026-10-16 8:45 ` Konrad Dybcio
0 siblings, 0 replies; 5+ messages in thread
From: Konrad Dybcio @ 2026-10-16 8:45 UTC (permalink / raw)
To: me, Bjorn Andersson, Konrad Dybcio, Abel Vesa, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel
On 10/16/26 8:01 AM, Demeter Barna via B4 Relay wrote:
> From: Demeter Barna <me@fromdisposition.org>
>
> Without them nothing votes for the CPUs' memory paths and DDR stays at
> what other clients request. Vote for CPU-to-LLCC, LLCC-to-DDR and L3
> with the CPU frequency, as on SM8550 and SM8650.
>
> The frequencies are the cpufreq-hw LUT; the LLCC, DDR (LPDDR5) and L3
> levels follow the downstream memory latency tables.
>
> Assisted-by: LLM
> Signed-off-by: Demeter Barna <me@fromdisposition.org>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Konrad
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2026-10-16 8:46 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2026-10-16 6:01 [PATCH 0/2] arm64: dts: qcom: sm8350: Scale L3 and memory bandwidth with the CPUs Demeter Barna via B4 Relay
2026-10-16 6:01 ` [PATCH 1/2] arm64: dts: qcom: sm8350: Add the EPSS L3 provider Demeter Barna via B4 Relay
2026-10-16 8:45 ` Konrad Dybcio
2026-10-16 6:01 ` [PATCH 2/2] arm64: dts: qcom: sm8350: Add CPU OPP tables with memory bandwidth Demeter Barna via B4 Relay
2026-10-16 8:45 ` Konrad Dybcio
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