[PATCH] arm64: dts: qcom: sm8750: Enable download mode register write

[PATCH] arm64: dts: qcom: sm8750: Enable download mode register write

[Mukesh Ojha]

Enable download mode setting for sm8750 which can help collect
ramdump for this SoC.

Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com>
---
 arch/arm64/boot/dts/qcom/sm8750.dtsi | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi
index c0734f6185e1..c812b2d26483 100644
--- a/arch/arm64/boot/dts/qcom/sm8750.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi
@@ -203,6 +203,7 @@ domain_ss3: domain-sleep-0 {
 	firmware {
 		scm: scm {
 			compatible = "qcom,scm-sm8750", "qcom,scm";
+			qcom,dload-mode = <&tcsr 0x19000>;
 			interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS
 					 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
 		};
@@ -2097,6 +2098,11 @@ tcsr_mutex: hwlock@1f40000 {
 			#hwlock-cells = <1>;
 		};
 
+		tcsr: syscon@1fc0000 {
+			compatible = "qcom,sm8750-tcsr", "syscon";
+			reg = <0 0x01fc0000 0 0x30000>;
+		};
+
 		remoteproc_mpss: remoteproc@4080000 {
 			compatible = "qcom,sm8750-mpss-pas";
 			reg = <0x0 0x04080000 0x0 0x10000>;
-- 
2.50.1

Re: [PATCH] arm64: dts: qcom: sm8750: Enable download mode register write

[Rob Herring]

On Mon, 12 Jan 2026 20:47:25 +0530, Mukesh Ojha wrote:
> Enable download mode setting for sm8750 which can help collect
> ramdump for this SoC.
> 
> Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com>
> ---
>  arch/arm64/boot/dts/qcom/sm8750.dtsi | 6 ++++++
>  1 file changed, 6 insertions(+)
> 


My bot found new DTB warnings on the .dts files added or changed in this
series.

Some warnings may be from an existing SoC .dtsi. Or perhaps the warnings
are fixed by another series. Ultimately, it is up to the platform
maintainer whether these warnings are acceptable or not. No need to reply
unless the platform maintainer has comments.

If you already ran DT checks and didn't see these error(s), then
make sure dt-schema is up to date:

  pip3 install dtschema --upgrade


This patch series was applied (using b4) to base:
 Base: attempting to guess base-commit...
 Base: tags/v6.19-rc1-51-g65ce09d2f164 (exact match)
 Base: tags/v6.19-rc1-51-g65ce09d2f164 (use --merge-base to override)

If this is not the correct base, please add 'base-commit' tag
(or use b4 which does this automatically)

New warnings running 'make CHECK_DTBS=y for arch/arm64/boot/dts/qcom/' for 20260112151725.2308971-1-mukesh.ojha@oss.qualcomm.com:

arch/arm64/boot/dts/qcom/sm8750-mtp.dtb: syscon@1fc0000 (qcom,sm8750-tcsr): 'clocks' is a required property
	from schema $id: http://devicetree.org/schemas/clock/qcom,sm8550-tcsr.yaml
arch/arm64/boot/dts/qcom/sm8750-qrd.dtb: syscon@1fc0000 (qcom,sm8750-tcsr): 'clocks' is a required property
	from schema $id: http://devicetree.org/schemas/clock/qcom,sm8550-tcsr.yaml

Re: [PATCH] arm64: dts: qcom: sm8750: Enable download mode register write

[Konrad Dybcio]

On 1/12/26 4:17 PM, Mukesh Ojha wrote:
> Enable download mode setting for sm8750 which can help collect
> ramdump for this SoC.
> 
> Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com>
> ---

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Konrad

Re: [PATCH] arm64: dts: qcom: sm8750: Enable download mode register write

[Konrad Dybcio]

On 1/13/26 10:16 AM, Konrad Dybcio wrote:
> On 1/12/26 4:17 PM, Mukesh Ojha wrote:
>> Enable download mode setting for sm8750 which can help collect
>> ramdump for this SoC.
>>
>> Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com>
>> ---
> 
> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Actually no, we have a mess to undo..

There's already this node:

tcsrcc: clock-controller@f204008 {
        compatible = "qcom,sm8750-tcsr", "syscon";
        reg = <0x0 0x0f204008 0x0 0x3004>;

        clocks = <&rpmhcc RPMH_CXO_CLK>;

        #clock-cells = <1>;
        #reset-cells = <1>;
};

That's located at the rear end of TLMM (someone had a funny idea to
move registers around when designing this specific SoC)

Problem is, those registers aren't actually "TCSRCC", not even "TCSR"
Physically, they belong to the TLMM register window (which starts at
the base it promises under the TLMM node today and is 0xf0_0000-long.

What we should have done for a fairer representation is make TLMM a
clock provider on this specific platform

qcom,sm8750-tcsr binds the tcsrcc driver, so we can't describe the
actual TCSR (as in this patch).. we'll have to break something..

Konrad

Re: [PATCH] arm64: dts: qcom: sm8750: Enable download mode register write

[Mukesh Ojha]

On Tue, Jan 13, 2026 at 10:20:58AM +0100, Konrad Dybcio wrote:
> On 1/13/26 10:16 AM, Konrad Dybcio wrote:
> > On 1/12/26 4:17 PM, Mukesh Ojha wrote:
> >> Enable download mode setting for sm8750 which can help collect
> >> ramdump for this SoC.
> >>
> >> Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com>
> >> ---
> > 
> > Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> 
> Actually no, we have a mess to undo..
> 
> There's already this node:
> 
> tcsrcc: clock-controller@f204008 {
>         compatible = "qcom,sm8750-tcsr", "syscon";
>         reg = <0x0 0x0f204008 0x0 0x3004>;
> 
>         clocks = <&rpmhcc RPMH_CXO_CLK>;
> 
>         #clock-cells = <1>;
>         #reset-cells = <1>;
> };
> 
> That's located at the rear end of TLMM (someone had a funny idea to
> move registers around when designing this specific SoC)
> 
> Problem is, those registers aren't actually "TCSRCC", not even "TCSR"
> Physically, they belong to the TLMM register window (which starts at
> the base it promises under the TLMM node today and is 0xf0_0000-long.
> 
> What we should have done for a fairer representation is make TLMM a
> clock provider on this specific platform
> 
> qcom,sm8750-tcsr binds the tcsrcc driver, so we can't describe the
> actual TCSR (as in this patch).. we'll have to break something..
> 

+               syscon: syscon@1fc0000 {
+                       compatible = "syscon";
+                       reg = <0 0x01fc0000 0 0x30000>;
+               };


What about above ?


> Konrad

-- 
-Mukesh Ojha

Re: [PATCH] arm64: dts: qcom: sm8750: Enable download mode register write

[Rob Herring]

On Tue, Jan 13, 2026 at 7:04 AM Mukesh Ojha
<mukesh.ojha@oss.qualcomm.com> wrote:
>
> On Tue, Jan 13, 2026 at 10:20:58AM +0100, Konrad Dybcio wrote:
> > On 1/13/26 10:16 AM, Konrad Dybcio wrote:
> > > On 1/12/26 4:17 PM, Mukesh Ojha wrote:
> > >> Enable download mode setting for sm8750 which can help collect
> > >> ramdump for this SoC.
> > >>
> > >> Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com>
> > >> ---
> > >
> > > Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> >
> > Actually no, we have a mess to undo..
> >
> > There's already this node:
> >
> > tcsrcc: clock-controller@f204008 {
> >         compatible = "qcom,sm8750-tcsr", "syscon";
> >         reg = <0x0 0x0f204008 0x0 0x3004>;
> >
> >         clocks = <&rpmhcc RPMH_CXO_CLK>;
> >
> >         #clock-cells = <1>;
> >         #reset-cells = <1>;
> > };
> >
> > That's located at the rear end of TLMM (someone had a funny idea to
> > move registers around when designing this specific SoC)
> >
> > Problem is, those registers aren't actually "TCSRCC", not even "TCSR"
> > Physically, they belong to the TLMM register window (which starts at
> > the base it promises under the TLMM node today and is 0xf0_0000-long.
> >
> > What we should have done for a fairer representation is make TLMM a
> > clock provider on this specific platform
> >
> > qcom,sm8750-tcsr binds the tcsrcc driver, so we can't describe the
> > actual TCSR (as in this patch).. we'll have to break something..
> >
>
> +               syscon: syscon@1fc0000 {
> +                       compatible = "syscon";
> +                       reg = <0 0x01fc0000 0 0x30000>;
> +               };
>
>
> What about above ?

What does validation say?

Rob

Re: [PATCH] arm64: dts: qcom: sm8750: Enable download mode register write

[Dmitry Baryshkov]

On Tue, Jan 13, 2026 at 06:34:28PM +0530, Mukesh Ojha wrote:
> On Tue, Jan 13, 2026 at 10:20:58AM +0100, Konrad Dybcio wrote:
> > On 1/13/26 10:16 AM, Konrad Dybcio wrote:
> > > On 1/12/26 4:17 PM, Mukesh Ojha wrote:
> > >> Enable download mode setting for sm8750 which can help collect
> > >> ramdump for this SoC.
> > >>
> > >> Signed-off-by: Mukesh Ojha <mukesh.ojha@oss.qualcomm.com>
> > >> ---
> > > 
> > > Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> > 
> > Actually no, we have a mess to undo..
> > 
> > There's already this node:
> > 
> > tcsrcc: clock-controller@f204008 {
> >         compatible = "qcom,sm8750-tcsr", "syscon";
> >         reg = <0x0 0x0f204008 0x0 0x3004>;
> > 
> >         clocks = <&rpmhcc RPMH_CXO_CLK>;
> > 
> >         #clock-cells = <1>;
> >         #reset-cells = <1>;
> > };
> > 
> > That's located at the rear end of TLMM (someone had a funny idea to
> > move registers around when designing this specific SoC)
> > 
> > Problem is, those registers aren't actually "TCSRCC", not even "TCSR"
> > Physically, they belong to the TLMM register window (which starts at
> > the base it promises under the TLMM node today and is 0xf0_0000-long.
> > 
> > What we should have done for a fairer representation is make TLMM a
> > clock provider on this specific platform
> > 
> > qcom,sm8750-tcsr binds the tcsrcc driver, so we can't describe the
> > actual TCSR (as in this patch).. we'll have to break something..
> > 
> 
> +               syscon: syscon@1fc0000 {
> +                       compatible = "syscon";

You can't have just a "syscon", you need a defining compat. 

> +                       reg = <0 0x01fc0000 0 0x30000>;
> +               };
> 
> 
> What about above ?
> 
> 
> > Konrad
> 
> -- 
> -Mukesh Ojha

-- 
With best wishes
Dmitry