From: Shrikanth Hegde <sshegde@linux.ibm.com>
To: Andrea Righi <arighi@nvidia.com>, Ingo Molnar <mingo@redhat.com>,
Peter Zijlstra <peterz@infradead.org>,
Juri Lelli <juri.lelli@redhat.com>,
Vincent Guittot <vincent.guittot@linaro.org>
Cc: Dietmar Eggemann <dietmar.eggemann@arm.com>,
Steven Rostedt <rostedt@goodmis.org>,
Ben Segall <bsegall@google.com>, Mel Gorman <mgorman@suse.de>,
Valentin Schneider <vschneid@redhat.com>,
Christian Loehle <christian.loehle@arm.com>,
Koba Ko <kobak@nvidia.com>,
Felix Abecassis <fabecassis@nvidia.com>,
Balbir Singh <balbirs@nvidia.com>,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH 4/4] sched/fair: Prefer fully-idle SMT core for NOHZ idle load balancer
Date: Fri, 27 Mar 2026 19:14:09 +0530 [thread overview]
Message-ID: <44483f44-b2cc-4b5d-aedc-2972fd8ccfe7@linux.ibm.com> (raw)
In-Reply-To: <20260326151211.1862600-5-arighi@nvidia.com>
On 3/26/26 8:32 PM, Andrea Righi wrote:
> When choosing which idle housekeeping CPU runs the idle load balancer,
> prefer one on a fully idle core if SMT is active, so balance can migrate
> work onto a CPU that still offers full effective capacity. Fall back to
> any idle candidate if none qualify.
>
> Cc: Vincent Guittot <vincent.guittot@linaro.org>
> Cc: Dietmar Eggemann <dietmar.eggemann@arm.com>
> Cc: Christian Loehle <christian.loehle@arm.com>
> Cc: Koba Ko <kobak@nvidia.com>
> Reported-by: Felix Abecassis <fabecassis@nvidia.com>
> Signed-off-by: Andrea Righi <arighi@nvidia.com>
> ---
> kernel/sched/fair.c | 19 +++++++++++++++++--
> 1 file changed, 17 insertions(+), 2 deletions(-)
>
> diff --git a/kernel/sched/fair.c b/kernel/sched/fair.c
> index 593a89f688679..a1ee21f7b32f6 100644
> --- a/kernel/sched/fair.c
> +++ b/kernel/sched/fair.c
> @@ -12733,11 +12733,15 @@ static inline int on_null_domain(struct rq *rq)
> * - When one of the busy CPUs notices that there may be an idle rebalancing
> * needed, they will kick the idle load balancer, which then does idle
> * load balancing for all the idle CPUs.
> + *
> + * - When SMT is active, prefer a CPU on a fully idle core as the ILB
> + * target, so that when it runs balance it becomes the destination CPU
> + * and can accept migrated tasks with full effective capacity.
> */
> static inline int find_new_ilb(void)
> {
> const struct cpumask *hk_mask;
> - int ilb_cpu;
> + int ilb_cpu, fallback = -1;
>
> hk_mask = housekeeping_cpumask(HK_TYPE_KERNEL_NOISE);
>
> @@ -12746,11 +12750,22 @@ static inline int find_new_ilb(void)
> if (ilb_cpu == smp_processor_id())
> continue;
>
> +#ifdef CONFIG_SCHED_SMT
> + if (!idle_cpu(ilb_cpu))
> + continue;
> +
> + if (fallback < 0)
> + fallback = ilb_cpu;
> +
> + if (!sched_smt_active() || is_core_idle(ilb_cpu))
is_core_idle does loop for all sublings and nohz.idle_cpus_mask
will have all siblings likely.
So that might turn out be a bit expensive on large SMT system such as SMT=4
Also, this is with interrupt disabled.
Will try to run this on powerpc system and see if simple benchmarks show anything.
> + return ilb_cpu;
> +#else
> if (idle_cpu(ilb_cpu))
> return ilb_cpu;
> +#endif
> }
>
> - return -1;
> + return fallback;
> }
>
> /*
next prev parent reply other threads:[~2026-03-27 13:44 UTC|newest]
Thread overview: 44+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-26 15:02 [PATCH 0/4] sched/fair: SMT-aware asymmetric CPU capacity Andrea Righi
2026-03-26 15:02 ` [PATCH 1/4] sched/fair: Prefer fully-idle SMT cores in asym-capacity idle selection Andrea Righi
2026-03-27 8:09 ` Vincent Guittot
2026-03-27 9:46 ` Andrea Righi
2026-03-27 10:44 ` K Prateek Nayak
2026-03-27 10:58 ` Andrea Righi
2026-03-27 11:14 ` K Prateek Nayak
2026-03-27 16:39 ` Andrea Righi
2026-03-30 10:17 ` K Prateek Nayak
2026-03-30 13:07 ` Vincent Guittot
2026-03-30 13:22 ` Andrea Righi
2026-03-30 13:46 ` Andrea Righi
2026-03-26 15:02 ` [PATCH 2/4] sched/fair: Reject misfit pulls onto busy SMT siblings on asym-capacity Andrea Righi
2026-03-26 15:02 ` [PATCH 3/4] sched/fair: Enable EAS with SMT on SD_ASYM_CPUCAPACITY systems Andrea Righi
2026-03-27 8:09 ` Vincent Guittot
2026-03-27 9:45 ` Andrea Righi
2026-03-26 15:02 ` [PATCH 4/4] sched/fair: Prefer fully-idle SMT core for NOHZ idle load balancer Andrea Righi
2026-03-27 8:45 ` Vincent Guittot
2026-03-27 9:44 ` Andrea Righi
2026-03-27 11:34 ` K Prateek Nayak
2026-03-27 20:36 ` Andrea Righi
2026-03-27 22:45 ` Andrea Righi
2026-03-30 17:29 ` Andrea Righi
2026-03-27 13:44 ` Shrikanth Hegde [this message]
2026-03-26 16:33 ` [PATCH 0/4] sched/fair: SMT-aware asymmetric CPU capacity Christian Loehle
2026-03-27 6:52 ` Andrea Righi
2026-03-27 16:31 ` Shrikanth Hegde
2026-03-27 17:08 ` Andrea Righi
2026-03-28 6:51 ` Shrikanth Hegde
2026-03-28 13:03 ` Balbir Singh
2026-03-28 22:50 ` Andrea Righi
2026-03-29 21:36 ` Balbir Singh
2026-03-30 22:30 ` Dietmar Eggemann
2026-03-31 9:04 ` Andrea Righi
2026-04-01 11:57 ` Dietmar Eggemann
2026-04-01 12:08 ` Vincent Guittot
2026-04-01 12:42 ` Andrea Righi
2026-04-01 13:12 ` Andrea Righi
2026-04-03 11:47 ` Dietmar Eggemann
2026-04-03 14:45 ` Andrea Righi
2026-04-03 20:44 ` Andrea Righi
2026-04-07 11:50 ` Dietmar Eggemann
2026-04-07 19:16 ` Andrea Righi
2026-04-03 11:47 ` Dietmar Eggemann
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