[PATCH] MIPS: Cobalt: Include legacy IDE ports in the PCI I/O window

[PATCH] MIPS: Cobalt: Include legacy IDE ports in the PCI I/O window

[Florian Fainelli]

The Cobalt PCI I/O window starts at 0x1000, excluding the VIA IDE
controller's fixed compatibility-mode ports at 0x170, 0x1f0, 0x376 and
0x3f6. These resources cannot be claimed under the host bridge window.

Since pcibios_enable_device() was converted to pci_enable_resources(),
the unclaimed IDE resources cause device enable to fail with -EINVAL:

  pata_via 0000:00:09.1: BAR 0 [io  0x01f0-0x01f7]: not claimed; can't enable device
  pata_via 0000:00:09.1: probe with driver pata_via failed with error -22

Lower the PCI I/O window start to 0x100 so the fixed IDE resources can
be claimed. Keep the reserved ISA resources below 0x100 outside the PCI
window.

On Qube2, the relevant I/O resources change as follows:

                         Before             After
  Host bridge window     1000-ffffff        0100-ffffff
  IDE BARs 0-3           Outside window     Inside window
  IDE BAR 4 (DMA)        1420-142f          0820-082f

With the fix, both pata_via hosts initialize and the ST380012A 80 GB
hard disk is detected as sda. The MIPS64 kernel reaches a root shell and
passes all eight boot-smoke checks.

Fixes: ae81aad5c2e1 ("MIPS: PCI: Use pci_enable_resources()")
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
 arch/mips/cobalt/pci.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/mips/cobalt/pci.c b/arch/mips/cobalt/pci.c
index 85ec9cc31d66..293c02e151d3 100644
--- a/arch/mips/cobalt/pci.c
+++ b/arch/mips/cobalt/pci.c
@@ -24,7 +24,8 @@ static struct resource cobalt_mem_resource = {
 };
 
 static struct resource cobalt_io_resource = {
-	.start	= 0x1000,
+	/* Include legacy IDE ports, but exclude the reserved ISA ports. */
+	.start	= 0x100,
 	.end	= 0xffffffUL,
 	.name	= "PCI I/O",
 	.flags	= IORESOURCE_IO,
-- 
2.53.0

Re: [PATCH] MIPS: Cobalt: Include legacy IDE ports in the PCI I/O window

[Maciej W. Rozycki]

On Thu, 15 Oct 2026, Florian Fainelli wrote:

> The Cobalt PCI I/O window starts at 0x1000, excluding the VIA IDE
> controller's fixed compatibility-mode ports at 0x170, 0x1f0, 0x376 and
> 0x3f6. These resources cannot be claimed under the host bridge window.
> 
> Since pcibios_enable_device() was converted to pci_enable_resources(),
> the unclaimed IDE resources cause device enable to fail with -EINVAL:
> 
>   pata_via 0000:00:09.1: BAR 0 [io  0x01f0-0x01f7]: not claimed; can't enable device
>   pata_via 0000:00:09.1: probe with driver pata_via failed with error -22
> 
> Lower the PCI I/O window start to 0x100 so the fixed IDE resources can
> be claimed. Keep the reserved ISA resources below 0x100 outside the PCI
> window.

 Why not go with 0 (unless that's not what the system controller supports 
as the bottom of the PCI I/O space), and just set PCIBIOS_MIN_IO correctly 
as several platforms do instead?  Is there a southbridge in your system?

  Maciej

Re: [PATCH] MIPS: Cobalt: Include legacy IDE ports in the PCI I/O window

[Florian Fainelli]

On 10/20/26 10:13, Maciej W. Rozycki wrote:
> On Thu, 15 Oct 2026, Florian Fainelli wrote:
> 
>> The Cobalt PCI I/O window starts at 0x1000, excluding the VIA IDE
>> controller's fixed compatibility-mode ports at 0x170, 0x1f0, 0x376 and
>> 0x3f6. These resources cannot be claimed under the host bridge window.
>>
>> Since pcibios_enable_device() was converted to pci_enable_resources(),
>> the unclaimed IDE resources cause device enable to fail with -EINVAL:
>>
>>    pata_via 0000:00:09.1: BAR 0 [io  0x01f0-0x01f7]: not claimed; can't enable device
>>    pata_via 0000:00:09.1: probe with driver pata_via failed with error -22
>>
>> Lower the PCI I/O window start to 0x100 so the fixed IDE resources can
>> be claimed. Keep the reserved ISA resources below 0x100 outside the PCI
>> window.
> 
>   Why not go with 0 (unless that's not what the system controller supports
> as the bottom of the PCI I/O space), and just set PCIBIOS_MIN_IO correctly
> as several platforms do instead?  Is there a southbridge in your system?

0 does not work and gives me:

[    0.205993] Skipping PCI bus scan due to resource conflict

There is no south bridge AFAICT, the CPU connection to the GT-64111.
-- 
Florian