Re: [PATCH v3 4/4] x86/cpufeatures: Use AWK to generate {REQUIRED|DISABLED}_MASK_BIT_SET

[Xin Li <xin@zytor.com>]

On 6/24/2024 3:24 AM, Andrew Cooper wrote:
> On 24/06/2024 8:29 am, Xin Li wrote:
>> On 6/23/2024 1:28 PM, Brian Gerst wrote:
>>> On Sat, Jun 22, 2024 at 1:14 PM Xin Li (Intel) <xin@zytor.com> wrote:
>>>> -               printf "#define %s_MASK_CHECK
>>>> BUILD_BUG_ON_ZERO(NCAPINTS != %d)\n\n", s, ncapints;
>>>> +               printf "\n#define %s_FEATURE(x)\t\t\t\t\\\n", s;
>>>> +               printf "\t((\t\t\t\t\t";
>>>> +               for (i = 0; i < ncapints; i++) {
>>>> +                       if (masks[i])
>>>> +                               printf "\t\\\n\t\t((x) >> 5) == %2d
>>>> ? %s_MASK%d :", i, s, i;
>>>> +               }
>>>> +               printf " 0\t\\\n";
>>>> +               printf "\t) & (1 << ((x) & 31)))\n";
>>>
>>> The original macro had 1UL here.  I don't know if it is strictly
>>> necessary in this case since we're using 32-bit masks, but it would
>>> probably be safer.
>>
>> I did notice it, but don't think UL is needed.
> 
> You do need 1U, or you'll trip UBSAN every time you test feature 31 in a
> word.

This is so obvious, how come I totally missed it!

> I'll note that the hypervisor bit is one such example.

What's more, generally bit 31 is nothing special, I find:
#define X86_FEATURE_PBE		( 0*32+31) /* Pending Break Enable */
#define X86_FEATURE_3DNOW	( 1*32+31) /* 3DNow */
#define X86_FEATURE_TSC_KNOWN_FREQ	( 3*32+31) /* TSC has known frequency */
...

Definitely I must append "U".

Thanks!
     Xin